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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
05/21/2015 > 23 patent applications in 15 patent subcategories.

20150143304 - Target point generation for optical proximity correction: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150143305 - Reticle data decomposition for focal plane determination in lithographic processes: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different... Agent: International Business Machines Corporation

20150143306 - Methods for fabricating high-density integrated circuit devices: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall... Agent: Synopsys, Inc.

20150143307 - Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis... Agent: Atrenta, Inc.

20150143309 - Computer implemented system and method for generating a layout of a cell defining a circuit component: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules... Agent:

20150143310 - P-cell caching: In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced... Agent:

20150143308 - Simulation system and method for testing a simulation of a device against one or more violation rules: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one... Agent: Freescale Semiconductor, Inc.

20150143312 - Method of designing patterns of semiconductor devices: A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design... Agent:

20150143311 - Method, system and computer program product for designing semiconductor device: A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150143315 - Fault injection of finfet devices: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured... Agent:

20150143313 - Grouping layout features for directed self assembly: Aspects of the invention relate to techniques of grouping layout features for directed self-assembly (DSA). Via-type features in a layout design are separated into via-type feature groups and isolated via-type features. The derived via-type feature groups are analyzed to determine whether the via-type feature groups are DSA-compliant. The layout design... Agent: Mentor Graphics Corporation

20150143314 - Method of designing fin field effect transistor (finfet)-based circuit and system for implementing the same: A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150143316 - Apparatus and methods for partitioning an integrated circuit design into multiple programmable devices: Methods and systems for partitioning a design across a plurality of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) are provided. The systems include SerDes (SERializer DESerializer) interfaces, such as PCIe, (Peripheral Component Interconnect Express) in the programmable logic devices operably connecting logic blocks of the design. Embodiments... Agent:

20150143317 - Determination of electromigration features: For one or more geometric elements partitioned into a plurality of geometric element portions, the expected current directions through each geometric element portion are determined. Using the expected current directions, each expected current path through the geometric element portions is determined. Based upon the expected current paths, and the physical... Agent: Mentor Graphics Corporation

20150143318 - Determination of electromigration susceptibility based on hydrostatic stress analysis: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions... Agent: Mentor Graphics Corporation

20150143319 - Different scaling ratio in feol / mol/ beol: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that... Agent: Taiwan Semicondutor Manufacturing Co., Ltd.

20150143320 - Method for producing mrom memory based on otp memory: A method of producing a MROM memory based on an OTP memory is provided. The method includes: removing the floating gate of the second PMOS transistor of the OTP memory cell for storing data “0” in the OTP memory map, such that the OTP memory cell being transferred to a... Agent:

20150143321 - Methods for cell phasing and placement in dynamic array architecture and implementation of the same: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists... Agent:

20150143322 - Switch cell: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option... Agent:

20150143323 - Generating guiding patterns for directed self-assembly: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on... Agent: Mentor Graphics Corporation

20150143324 - Semiconductor device design methods and conductive bump pattern enhancement methods: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern... Agent:

20150143326 - Efficient ceff model for gate output slew computation in early synthesis: A slew-based effective capacitance (Ceff) is used to compute gate output slew during early synthesis of an integrated circuit design. A π model is constructed for the gate and reduced to two parameters which are used to compute a slew value for the model, given a slew definition. A capacitance... Agent: International Business Machines Corporation

20150143325 - Method, system, and computer program product for modeling resistance of a multi-layered conductive component: Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined... Agent: International Business Machines Corporation

05/14/2015 > 12 patent applications in 8 patent subcategories.

20150135146 - Three-dimensional mask model for photolithography simulation: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved... Agent: Asml Netherlands B.v.

20150135148 - Decision modules: The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module... Agent:

20150135147 - Generating a circuit description for a multi-die field-programmable gate array: A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned... Agent:

20150135150 - Formal verification coverage metrics for circuit design properties: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals... Agent:

20150135149 - Monitoring coverage for static modelling of an electronic device: A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a solver, that identifies whether the mathematical relationships of the static model can be reconciled, given a set of user-defined... Agent: Freescale Semiconductor Inc.

20150135151 - Canonical forms of layout patterns: Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming... Agent: Mentor Graphics Corporation

20150135154 - Apparatus and methods for optimization of integrated circuits: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).... Agent:

20150135152 - Clock tree design: A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an indication of an output clock frequency. The tool also detects selection by the user of a soft control and, as a result of... Agent: Texas Instruments Incorporated

20150135153 - Method of validating timing issues in gate-level simulation: A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a... Agent: Freescale Semiconductor, Inc.

20150135155 - Design support device, semiconductor device, and non-transitory computer readable medium: According to an embodiment, a semiconductor device switches circuit forms and circuit configurations of a plurality of analog functional circuits by rearranging a command execution order according to the command execution order set in advance irrespectively of a command execution order specified by a user and executing the commands.... Agent:

20150135156 - Semiconductor structures with deep trench capacitor and methods of manufacture: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and... Agent:

20150135157 - Circuit-design simulation system and circuit-design method for pcb: A circuit-design method for a PCB is provided. A first user input is obtained via a user interface of a layout tool, wherein the first user input indicates that an object of a circuit diagram of the PCB is selected in the user interface. A plurality of constraint settings corresponding... Agent: Wistron Corp

05/07/2015 > 5 patent applications in 5 patent subcategories.

20150128098 - Method and system for repairing wafer defects: A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150128099 - Mask and method of forming pattern by using the same: A method of forming a pattern is disclosed. At first, a layout pattern is provided to a computer system. The layout pattern includes at least a first strip pattern and at least a second strip pattern, and a width of the second strip pattern is substantially larger than a width... Agent:

20150128100 - Cycle-accurate replay and debugging of running fpga systems: As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible... Agent:

20150128101 - Promoting efficient cell usage to boost qor in automated design: A method of designing integrated circuits includes forming a restricted cell library from a first cell library by selecting only those cells in the first cell library that are most efficient according to predetermined efficiency criteria and executing an integrated circuit design operation in an electronic design automation program while... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150128102 - Circuit design synthesis tool with export to a computer-aided design format: A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input and a printed circuit board (PCB) layout based on the circuit. The method further includes generating a bill of material (BOM) for the circuit,... Agent:

04/30/2015 > 15 patent applications in 12 patent subcategories.

20150121317 - Multi-patterning system and method: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150121318 - Automated generation of mask file from three dimensional model for use in grayscale lithography: A method, apparatus and program product automatically generate a grayscale lithography mask file (76) from a three dimensional (3D) model (72) of a desired topography, e.g., as generated by a three dimensional computer aided design (CAD) tool (70).... Agent:

20150121319 - Methods and tools for designing integrated circuits with auto-pipelining capabilities: A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the... Agent: Altera Corporation

20150121321 - Configuring a programmable device using high-level language: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. the compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations... Agent:

20150121320 - System and method for universal control of electronic devices: A system and method for providing an integrated circuit that integrates with and controls a device wherein the integrated circuit design is developed based on a selection of characteristics of the device. The system and method also provide software for establishing interoperability between the integrated circuit and a controller.... Agent:

20150121322 - Circuit design porting between process design types: Among other things, one or more systems and techniques for porting a circuit design from a first process design type to a second process design type are provided. A circuit design comprises one or more components, such as transistors, that are arranged and sized according to a first process design... Agent: Taiwan Semiconductor Manufacturing Company Limited

20150121323 - Determining a quality parameter for a verification environment: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list... Agent:

20150121324 - Cell library and method for designing an asynchronous integrated circuit: The invention relates to a rocket engine with an extendable divergent which includes an exhaust nozzle for the gases coming from a combustion chamber, the nozzle having a longitudinal axis (ZZ′) including a first portion defining a nozzle throat and a first fixed divergent section (12), at least one second... Agent:

20150121325 - Simulation system and method for testing a simulation of a device against one or more violation rules: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one... Agent: Freescale Semiconductor, Inc.

20150121326 - Functional verification of a circuit description: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and... Agent:

20150121327 - Monolithic three dimensional (3d) integrated circuit (ic) (3dic) cross-tier clock skew management systems, methods and related components: Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay... Agent: Qualcomm Incorporated

20150121328 - Path-based floorplan analysis: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.... Agent:

20150121329 - Method and system for designing fin-fet semiconductor device: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150121330 - Hierarchical electromigration analysis using intelligent connectivity: Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration... Agent: Oracle International Corporation

20150121331 - Surface region selection for heat sink placement: A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that... Agent:

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