|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor maskBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/05/2013 > 30 patent applications in 17 patent subcategories.
20130326435 - Distance metric for accurate lithographic hotspot classification using radial and angular functions: An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function... Agent:
20130326434 - Integrated circuit design method with dynamic target point: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130326436 - Method for checking die seal ring on layout and computer system: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received.... Agent: United Microelectronics Corp.
20130326437 - Gradient-based pattern and evaluation point selection: Described herein is a method for a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic imaging apparatus, the lithographic process having a plurality of design variables, the method comprising: calculating a gradient of each of a plurality of evaluation points or patterns... Agent: Asml Netherlands B.v.
20130326439 - Image processing device and computer program for performing image processing: It is an object of the present invention to provide an image processing device for allowing an actual-image-closer pattern to be formed based on the design data, or its simulation image. In order to accomplish the above-described object, the proposal is made concerning an image processing device which includes an... Agent: Hitachi High Technologies Corporation
20130326438 - Layout modification method and system: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130326440 - Analog/digital partitioning of circuit designs for simulation: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as... Agent: Cadence Design Systems, Inc.
20130326441 - Machine-learning based datapath extraction: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is... Agent: International Business Machines Corporation
20130326442 - Reliability evaluation and system fail warning methods using on chip parametric monitors: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can... Agent: Mentor Graphics Corporation
20130326443 - Method of generating a recipe for a manufacturing tool and system thereof: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity... Agent: Applied Materials Israel Ltd.
20130326444 - Recording medium for generation program, generation method, and generation apparatus: In a generation method, the computer detects a contact between a pin data group of a first connection destination included in three-dimensional shape data and a pin data group of a first connection source included in three-dimensional shape data of a connector, and determines first contact information that indicates combinations... Agent: Fujitsu Limited
20130326445 - Categorization of design rule errors: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by... Agent: International Business Machines Corporation
20130326447 - Method and system for layout parasitic estimation: A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130326446 - Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules: A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an... Agent: Freescale Semiconductor, Inc.
20130326448 - Techniques for electromigration stress determination in interconnects of an integrated circuit: In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated... Agent: Freescale Semiconductor, Inc.
20130326450 - Early design cycle optimzation: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of... Agent: International Business Machines Corporation
20130326449 - Incremental elmore delay calculation: Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based... Agent: Synopsys, Inc.
20130326451 - Structured latch and local-clock-buffer planning: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined... Agent: International Business Machines Corporation
20130326453 - Circuit layout method for printed circuit board, eletronic device and computer readable recording media: The present disclosure illustrates a circuit layout method for printed circuit board which is adapted for an electronic device. The circuit layout method includes the following steps. A parameters configuration interface is provided for receiving corresponding stack-up parameters and a plurality of layout parameters. A radio frequency layer, a first... Agent: Wistron Corp.
20130326452 - Method, device, and a computer-readable recording medium having stored program for information processing for noise suppression design check: A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality... Agent: Fujitsu Limited
20130326454 - Apparatus and method for reducing peak power using asynchronous circuit design technology: Disclosed herein are an apparatus and method for reducing peak power using an asynchronous circuit design technology. The apparatus includes a combinational circuit unit and an asynchronous control circuit unit. The combinational circuit unit divides a combinational circuit into a plurality of partial circuits based on the depth of input... Agent:
20130326456 - Designing a robust power efficient clock distribution network: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and... Agent: International Business Machines Corporation
20130326455 - Element placement in circuit design based on preferred location: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element.... Agent: International Business Machines Corporation
20130326457 - Integrated electronic design automation system: An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and have manufactured a specific class of custom electronic device, namely a computer processing unit with embedded software. A Graphical User Interface (GUI) is... Agent: Gumstix, Inc.
20130326458 - Timing refinement re-routing: A design tool can automatically improve timing of nets of a fully routed physical design solution. Nets of a netlist are evaluated against a plurality of re-routing criteria to identify the nets that satisfy at least one of the plurality of re-routing criteria. For each of the nets that satisfy... Agent: International Business Machines Corporation
20130326460 - Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected... Agent:
20130326459 - Power/performance optimization through temperature/voltage control: A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects... Agent: International Business Machines Corporation
20130326462 - Method and device for reconstructing scan chains based on bidirectional preference selection in physical design: Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of... Agent: Synopsys (shanghai) Co., Ltd.
20130326461 - Method for detecting interference in spatial structure: A method for detecting interference in spatial structure is provided. The method includes the following steps. A circuit board is obtained, wherein the circuit board has set a first height limit, and parts of the coordinate areas have set a plurality of second height limits respectively. The second height limits... Agent: Inventec Corporation
20130326463 - Method to determine optimal micro-bump-probe pad pairing for efficient pgd testing in interposer designs: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.11/28/2013 > 9 patent applications in 6 patent subcategories.
20130318483 - Standardized topographical arrangements for template regions that orient self-assembly: This disclosure relates generally to systems and methods of providing standardized topographical configurations for template regions. In one embodiment, a set of array arrangements is selected. Arrays of template structures are then formed on at least one substrate. Each of the arrays is arranged in accordance with an array arrangement... Agent: Massachusetts Institure Of Technology
20130318485 - Design alteration for wafer inspection: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by... Agent: Kla-tencor Corporation
20130318484 - Third party component debugging for integrated circuit design: The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and... Agent: Mentor Graphics Corporation
20130318486 - Method and system for generating verification environments: A method and system for a verification of a DUT is provided. The method and system is configured to generate a verification environment using a rules based metalanguage. The rules are converted into components in the verification environment. The method and system is configured to, for example, generating constraints in... Agent:
20130318487 - Programmable circuit characteristics analysis: Techniques for analysis of an electrical circuit design are described, which techniques employ two phases: an initialization phase, and a check phase. During the initialization phase, a circuit design is examined to determine the predicted operating characteristics at various nodes within the design. If the design is hierarchically arranged, then... Agent: Mentor Graphics Corporation
20130318488 - Excluding library cells for delay optimization in numerical synthesis: Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the... Agent: Synopsys, Inc.
20130318489 - Active net and parasitic net based approach for circuit simulation and characterization: A computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. Active nets are interconnections between circuit components showing a level of activity during the simulation. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a... Agent:
20130318490 - Method and system for design and modeling of vertical interconnects for 3di applications: A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that represent the frequency dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus... Agent: International Business Machines Corporation
20130318491 - Method and apparatus for performing parallel routing using a multi-threaded routing procedure: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of... Agent: Altera Corporation11/21/2013 > 10 patent applications in 9 patent subcategories.
20130311957 - Semiconductor device design system and method of using the same: A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130311959 - Multivariable solver for optical proximity correction: The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of... Agent: Asml Netherlands B.v.
20130311958 - Pattern selection for full-chip source and mask optimization: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set... Agent: Asml Netherlands B.v.
20130311960 - Method and apparatus for enhancing signal strength for improved generation and placement of model-based sub-resolution assist features (mb-sraf): Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior... Agent: Asml Netherlands B.v.
20130311961 - Timing exact design conversions from fpga to asic: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor... Agent:
20130311962 - Instruction-by-instruction checking on acceleration platforms: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction... Agent: International Business Machines Corporation
20130311963 - Sub-circuit models with corner instances for vlsi designs: An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance... Agent: Globalfoundries Inc.
20130311964 - Modified design rules to improve device performance: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130311965 - Apparatus and method for optimized power cell synthesizer: Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes... Agent:
20130311966 - Circuit design support apparatus, computer-readable recording medium, and circuit design support method: A circuit design support apparatus includes a simulating unit that simulates the operation of each circuit in a predetermined network on the basis of circuit information indicating the network, and generates simulated waveform information; a control unit that performs control so that simulated waveform information, which is information indicating a... Agent: Fujitsu Limited11/14/2013 > 15 patent applications in 10 patent subcategories.
20130305195 - Analysis optimizer: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined... Agent: Mentor Graphics Corporation
20130305194 - Validation of integrated circuit designs built with encrypted silicon ip blocks: A method and system for validating integrated circuit designs that are built with encrypted silicon IP blocks decrypts the encrypted silicon IP blocks in the integrated circuit designs with the keys from IP providers. After decryption, various validation checks on the integrated circuit designs are done, such as design rule... Agent:
20130305196 - Systems and methods for creating frequency-dependent netlist: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of... Agent:
20130305197 - Method and system for optimal diameter bounding of designs with complex feed-forward components: A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for... Agent: Ibm Corporation
20130305198 - Circuit design support device, circuit design support method and program: A processing part inputs a behavior description code in which a write access array to be accessed to write and a read access array to be accessed to read are used. The processing part analyzes the behavior description code, and determines an order of using each write access address and... Agent:
20130305199 - In-place resynthesis and remapping techniques for soft error mitigation in fpga: In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which have a low overheard and improve FPGA designs without the need of rerouting LUTs of the FPGA. These methods include in-place reconfiguration (IPR), in-place... Agent: The Regents Of The University Of California
20130305200 - Computer-aided design system to automate scan synthesis at register-transfer level: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection,... Agent:
20130305201 - Integrated circuit simulation using fundamental and derivative circuit runs: A system that simulates an integrated circuit is formed of a plurality of devices. The system initially performs a fundamental circuit simulation run using original parameters for the plurality of devices and an initial time step. The system generates one or more fundamental time steps from the fundamental circuit simulation... Agent: Oracle International Corporation
20130305202 - Mismatch verification device and methods thereof: A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device... Agent: Freescale Semiconductor, Inc.
20130305204 - Hierarchical feature extraction for electrical interaction calculations: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the... Agent: Mentor Graphics Corporation
20130305203 - Multi-pass routing to reduce crosstalk: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed... Agent: Lsi Corporation
20130305205 - Program binding system, method and software for a resilient integrated circuit architecture: The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by... Agent:
20130305206 - Measurement model optimization based on parameter variations across a wafer: An optimized measurement model is determined based a model of parameter variations across a semiconductor wafer. A global, cross-wafer model characterizes a structural parameter as a function of location on the wafer. A measurement model is optimized by constraining the measurement model with the cross-wafer model of process variations. In... Agent: Kla-tencor Corporation
20130305207 - Method for detecting and debugging design errors in low power ic design: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain... Agent: Synopsys, Inc.
20130305208 - Semiconductor integrated circuit and method for desigining the same: A semiconductor integrated circuit according to one embodiment includes a plurality of flip-flop groups configured by dividing a plurality of flip-flops, connected in series, for carrying out a serial operation of serially transferring data, a continuous signal determination circuit configured to output a first signal if outputs of the flip-flops... Agent:Previous industry: Data processing: presentation processing of document
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