Data processing: design and analysis of circuit or semiconductor mask inventions

20080104548 - Method and system for tuning a circuit: The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that... Agent: Morrison & Foerster LLP

20080104549 - Read-only memory device and related method of design: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address... Agent: Fox Rothschild, LLP

20080104550 - Compensating for layout dimension effects in semiconductor device modeling: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance... Agent: Williams, Morgan & Amerson

20080104551 - Design structure for providing optimal field programming of electronic fuses: A design structure for providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in... Agent: Greenblum & Bernstein, P.L.C

20080104552 - Power consumption optimizing method for semiconductor integrated circuit and semiconductor designing apparatus: Disclosed in a power consumption optimizing method for optimizing the power consumption in a semiconductor integrated circuit, which is employed in circuit designing in which the specification of the semiconductor integrated circuit is described in HDL and from the source described in said HDL, logic composition and layout design are... Agent: Mcdermott Will & Emery LLP

20080104554 - Esd analysis device and esd analysis program used for designing semiconductor device and method of designing semiconductor device: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate... Agent: Foley And Lardner LLP Suite 500

20080104553 - Method and apparatus for integrated hierarchical electronics analysis: A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies are for use with chassis... Agent: Duke W. Yee

20080104556 - Assertion generating system, program thereof, circuit verifying system, and assertion generating method: An assertion generating system is disclosed. In an assertion generating system 207, a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state... Agent: Dickstein Shapiro LLP

20080104557 - Integrated sizing, layout, and extractor tool for circuit design: Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of design points, where a design point comprises a design of the circuit that meets a set of predefined design... Agent: Morrison & Foerster LLP

20080104561 - Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit: A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080104562 - Method and program for designing semiconductor integrated circuit: The method of designing a semiconductor integrated circuit of the embodiment is characterized in: reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which a variation of a property value is not taken into consideration, and reading from... Agent: Staas & Halsey LLP

20080104563 - Timing verification method and timing verification apparatus: Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Then, in a first-time timing verification process, voltage drop... Agent: Staas & Halsey LLP

20080104565 - Design data dependency managing apparatus, design data dependency managing method and program: A design data dependency managing apparatus comprises an input/output data storing unit for storing design input/output dependency information indicating a dependency between design input/output data, which becomes an input/output of a design, and other design input/output data in association with the design input/output data, and a design execution environment constructing... Agent: Staas & Halsey LLP

20080104566 - Optimization of rom structure by splitting: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets... Agent: Fox Rothschild, LLP

20080104555 - Testing pattern sensitive algorithms for semiconductor design: A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving... Agent: Hoffman, Warnick & D'alessandro LLC

20080104558 - Method and system for enhanced verification through structural target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more... Agent: Dillon & Yudell LLP

20080104559 - Method and system for enhanced verification through structural target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more... Agent: Dillon & Yudell LLP

20080104560 - Method and system for parametric reduction of sequential designs: A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut... Agent: Dillon & Yudell LLP

20080104564 - Clustering circuit paths in electronic circuit design: Techniques are disclosed for clustering circuit paths in an electronic design automation process for use in improving the timing characteristics of the overall circuit design. Circuit paths included in the cluster may be subjected to placing and routing as a group to relocate instances of circuit components included in the... Agent: Klarquist Sparkman, LLP

20080104567 - Apparatus and method for allocating component, and computer readable medium: There is provided an apparatus that creates a component allocation plan for an electronic apparatus including first and second allocation layers in which components are allocated, including: a storage configured to store first and second component information indicating sizes of a plurality of first components and a plurality of second... Agent: Amin, Turocy & Calvin, LLP

20080104568 - Systematic yield in semiconductor manufacture: Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on... Agent: Andrew M. Calderon Greenblum And Bernstein P.L.C

20080098335 - Automatic voltage drop optimization: To minimize the voltage drops in an electronic circuit, existing instances are moved and decoupling capacitors are automatically inserted according to an algorithm. A model of the voltage drop on a row of gate elements is presented. The model allows for rapid computations of the effect of a particular move... Agent: Macpherson Kwok Chen & Heid LLP

20080098341 - Design layout generating method for semiconductor integrated circuits: A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080098334 - Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080098336 - Compiler and logic circuit design method: A compiler in which pseudo C descriptions (1) that are capable of describing parallel operations at a statement level and at a cycle precision by clock boundaries and register assignment statements are input, the register assignment statements are identified (S2), so as to generate executable C descriptions (3), to extract... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080098337 - Method of forming guard ring parameterized cell structure in a hierarchical parameterized cell design, checking and verification system: The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guard ring either graphically, semantically, or symbolically in a single display.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080098338 - Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits: A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then... Agent: Sughrue Mion, PLLC

20080098339 - Racecheck: a race logic analyzer program for digital integrated circuits: Techniques a race logic analysis on an integrated circuit (IC) design are described herein. In one embodiment, all hardware description language (HDL) defined system functions and/or tasks that have one or more side-effects when invoked in a first HDL language, but not when the same HDL-defined system functions/tasks are invoked... Agent: Blakely Sokoloff Taylor & Zafman

20080098340 - Method for designing block placement and power distribution of semiconductor integrated circuit: The present invention relates to a method for designing initial placement of functional blocks and designing power distribution network of a semiconductor integrated circuit in the next stage of architecture level design of integrated circuit, which estimates the area and the quantity of power consumption of functional blocks and integrated... Agent: Harness, Dickey & Pierce, P.L.C

20080098342 - Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device: A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having a high-potential power supply end connected to VDD and a low potential power supply end connected... Agent: Mcdermott Will & Emery LLP

20080098343 - System and method for text based placement engine for custom circuit design: A system and method that uses a text-based script file to capture a circuit design and allows a circuit designer to manipulate the script file. The circuit designer can add, delete, or move components using various tags and commands that are stored in the script file. When the design is... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080092089 - Cad data processing apparatus, cad data processing method, and computer product: A CAD data processing apparatus acquires first net information and second net information through an input unit, and stores the information in a storage unit. A correlation processor creates an association table that associates components, terminals, and nets contained in the first net information with components, terminals, and nets contained... Agent: Staas & Halsey LLP

20080092088 - Process monitoring system and method: The invention provides a system that includes: (i) an interface for receiving design information representative of a portion of a layer of an object that includes sub micron measurement targets; and (ii) a processor, coupled to the interface, for processing the received design information to provide a large number of... Agent: Applied Materials, Inc. C/o Sonnenschein Nath & Rosenthal LLP

20080092090 - Operation analysis method of semiconductor integrated circuit: Operation analysis is performed for a semiconductor integrated circuit designed by using substrate bias control technology. Power supply potential and substrate potential are analyzed by using circuit information of the semiconductor integrated circuit, and from obtained power supply potential waveform information and substrate potential waveform information, potential difference information indicating... Agent: Mcdermott Will & Emery LLP

20080092092 - Method and processor for power analysis in digital circuits: This invention relates to a method and processor (19) for power analysis in digital circuits. The method incorporates a main processor (19) and an associative memory mechanism (101a, 101b, 102, 104, 105, 106), the associative memory mechanism comprising a plurality of associative arrays (101a, 101b), an input value register (102),... Agent: Holland & Knight LLP

20080092093 - Register transfer level (rtl) test point insertion method to reduce delay test volume: A method includes inserting test points into a circuit for reducing the number of specified bits required for transition fault testing of the circuit by reducing the dependency of a second time-frame pattern of the circuit on a first time-frame pattern of the circuit. Preferably, inserting the test points includes... Agent: Nec Laboratories America, Inc.

20080092094 - Semiconductor structure and method of manufacture: The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped... Agent: Greenblum & Bernstein, P.L.C

20080092099 - Analog and mixed signal ic layout system: A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide... Agent: Smith-hill And Bedell, P.C.

20080092100 - System and method for electromigration tolerant cell synthesis: A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one... Agent: Freescale - Jvl C/o Vanleeuwen & Vanleeuwen

20080092102 - Multitasking circuit layout diagram silkscreen text handling method and system: A multitasking circuit layout diagram silkscreen text handling method and system is proposed, which is designed for use in conjunction with a computer platform that runs a CAD (Computer-Aided Design) circuit layout design program, for providing a CAD-created circuit layout diagram with a multitasking silkscreen text handling capability, which is... Agent: Law Offices Of Mikio Ishimaru

20080092103 - System, method, and program for generating circuit: An aspect of the invention provides a circuit generation system that can automatically generate a power control circuit. In the circuit generation system according to the aspect of the invention includes a behavioral synthesis unit that generates synthesis-attached information and RT-level circuit information based on behavioral-level description information in which... Agent: Mcginn Intellectual Property Law Group, PLLC

20080092091 - Method and system for reduction of xor/xnor subexpressions in structural design representations: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set... Agent: Dillon & Yudell LLP

20080092095 - Design structure and system for identification of defects on circuits or other arrayed products: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample... Agent: Harrington & Smith, PC

20080092097 - Method and system for case-splitting on nodes in a symbolic simulation framework: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the... Agent: Dillon & Yudell LLP

20080092098 - Method and system for case-splitting on nodes in a symbolic simulation framework: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the... Agent: Dillon & Yudell LLP

20080092096 - Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework: A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the... Agent: Dillon & Yudell LLP

20080092101 - Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080092104 - Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables: A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate... Agent: Dillon & Yudell LLP

20080092105 - Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables: A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate... Agent: Dillon & Yudell LLP

20080092106 - Method for performing pattern pitch-split decomposition utilizing anchoring features: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of: (a) determining a minimum critical dimension and pitch associated with a process to be utilized to image the multiple patterns; (b) generating an anchoring feature; (c)... Agent: Mcdermott Will & Emery LLP

20080086705 - Automatic translation of simulink models into the input language of a model checker: A translator converts an input model, such as resulting from a simulation of a design to be verified, into an output model suitable for verification by a model checker. The input model, for example, may be produced using Simulink, and the output model, for example, may be a NuSMV model.... Agent: Honeywell International Inc.

20080086710 - Method and system for the modular design and layout of integrated circuits: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions.... Agent: Imperium Patent Works

20080086709 - System and method for automatic elimination of electromigration and self heat violations during construction of a mask layout block, maintaining the process design rules (drc clean) and layout connectivity (lvs clean) correctness: A system and method for automatic elimination of electromigration (EM) and self heat (SH) violations during construction of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness, are disclosed. The method includes analyzing a selected polygon for space, width and length, in... Agent: Danny Rittman

20080086708 - System and method for automatic elimination of electromigration and self heat violations of a mask layout block, maintaining the process design rules correctness: A system and method for automatic correction of electromigration (EM) and self heat (SH) violations of a mask layout block, maintaining the process design rules correctness are disclosed. The method includes analyzing polygons for space, width and length, in a mask layout block and obtaining one or more electromigration and/or... Agent: Danny Rittman

20080086711 - Method and apparatus for designing integrated circuit: In the present invention, a block level net list is separated from a chip level net list so that the chip level net list can be created in a form in which a block is transparent to a designer. The present invention determines a destination block for circuit elements that... Agent: Staas & Halsey LLP

20080086712 - Method of designing a pattern: A method of designing a pattern of a hole pattern having a configuration, in which grid of interval smaller than a minimum permissible pitch according to a design rule for a semiconductor integrated circuit is provided in a pattern drawing, a hole pattern is arranged on a first lattice point... Agent: Young & Thompson

20080086713 - Method and apparatus for automatic synthesis of an electronic circuit model: Method and apparatus for synthesizing (constructing) an electronic circuit model in response to electromagnetic analysis data. The invention provides rapid automation of the synthesis of an electronic circuit model by incorporating one or more synthesized electronic model components that are selected from a larger plurality of synthesized (candidate) electronic components... Agent: Hiscock & Barclay, LLP

20080086714 - Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks: A method and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. The method and system comprises locating regions in a finished semiconductor design that do not contain as-designed shapes. The method and system... Agent: Greenblum & Bernstein, P.L.C

20080086707 - Method and system for enchanced verification through binary decision diagram-based target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is... Agent: Dillon & Yudell LLP

20080086706 - Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of... Agent: Schmeiser, Olsen & Watts

20080086715 - Method for interlayer and yield based optical proximity correction: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with... Agent: John A. Jordan, Esq.