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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/22/2015 > 8 patent applications in 6 patent subcategories.

20150026650 - Integrated circuit manufacture using direct write lithography: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step... Agent:

20150026651 - Preventing double patterning odd cycles: A method, system or computer usable program product for preventing odd cycles caused by design modifications to a double patterning layout including utilizing a processor to identify a set of double patterning cycles in the layout for storage in a memory; receiving a set of design modifications to the layout;... Agent:

20150026652 - System, method, and computer program product for correlating transactions within a simulation of a hardware platform for post-simulation debugging: A system, method, and computer program product for correlating transaction within a simulation of a hardware platform for post-simulation debugging is disclosed. The method includes the steps of initializing state information associated with a hardware simulation for a register-transfer level model representing a digital circuit design, executing the hardware simulation... Agent:

20150026654 - Hierarchical verification of clock domain crossings: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level... Agent:

20150026653 - Relative timing characterization: Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point... Agent:

20150026655 - Determining a set of timing paths for creating a circuit abstraction: Systems and techniques for determining a set of timing paths for creating a circuit abstraction are described. During operation, an embodiment can receive a set of circuit elements in the circuit design that are candidates for optimization. Next, the embodiment can determine a set of timing paths by identifying critical... Agent:

20150026656 - Updating pin locations in a graphical user interface of an electronic design automation tool: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects... Agent:

20150026657 - 3d device modeling for finfet devices: Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin... Agent:

  
01/15/2015 > 5 patent applications in 5 patent subcategories.

20150020037 - Method and system for design of a reticle to be manufactured using variable shaped beam lithography: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle... Agent:

20150020038 - Method for efficient fpga packing: A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing... Agent:

20150020039 - Cascode cmos structure: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and... Agent:

20150020040 - Method for automatic design of an electronic circuit, corresponding system and computer program product: A method for the automatic design of an electronic circuit includes operations for evaluation of the thermal effects in the electronic circuit. The method generates a layout of the electronic circuit. Abstract data at the substrate level associated to the layout of the electronic circuit is then generated. A grid... Agent: Stmicroelectronics S.r.l.

20150020041 - Method and system for enhanced integrated circuit layout: An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a minor of the first cell. The method further includes dividing the first cell into a first plurality of... Agent:

  
01/08/2015 > 10 patent applications in 9 patent subcategories.

20150012895 - Double patterning technology (dpt) layout routing: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on... Agent:

20150012896 - Methods for fabricating integrated circuits including generating photomasks for directed self-assembly: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to... Agent:

20150012897 - Methods for fabricating integrated circuits including generating photomasks for directed self-assembly: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to... Agent:

20150012898 - Automated bottom-up and top-down partitioned design synthesis: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions... Agent:

20150012899 - Method for deriving equivalent circuit model of capacitor: A method for deriving an equivalent circuit model of a capacitor which makes it possible to derive, with high accuracy and with ease, an equivalent circuit model having characteristics in accordance with a direct current voltage applied to a capacitor. Characteristic values of predetermined resistive elements and capacitive elements forming... Agent: Murata Manufacturing Co., Ltd.

20150012900 - Methods and systems for detecting repeating defects on semiconductor wafers using design data: Systems and methods for detecting defects on a wafer are provided. One method includes determining locations of all instances of a weak geometry in a design for a wafer. The locations include random, aperiodic locations. The weak geometry includes one or more features that are more prone to defects than... Agent:

20150012901 - Fixed-outline floorplanning approach for mixed-size modules: A fixed-outline floorplanning approach for mixed-size modules is disclosed. Firstly, evenly distribute mixed-size circuit modules to whole chip area based on different requirements such as wire-length, routability, or thermal in the global distribution stage. To maintain the global distribution result and satisfy the fixed-outline constraint, generate a slicing tree by... Agent: National Cheng Kung University

20150012902 - Automatic mapping method for a distribution network based on logical layout: The invention provides an automatic mapping method for a distribution network based on logical layout, comprising (1) pretreating a model of the distribution network model by analyzing it, and partitioning and striping the distribution network model to generate a plurality of partial models; (2) analyzing an automatic mapping algorithm to... Agent: Jiangsu Electric Power Company

20150012903 - Non-intrusive monitoring and control of integrated circuits: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based... Agent: Tabula, Inc.

20150012904 - System and method for setting electrical specification of signal transmission line: A computer-based method for setting electrical specification of signal transmission lines of a printed circuit board (PCB) layout is provided. Data recorded in an electrical specification file is imported. The electrical specification file records a number of chips, pins of each chip, and electrical specification corresponding to each chip. The... Agent: Hon Hai Precision Industry Co., Ltd.

  
01/01/2015 > 6 patent applications in 5 patent subcategories.

20150007119 - Method of forming a semiconductor circuit: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of... Agent: International Business Machines Corporation

20150007120 - Clustering using n-dimensional placement: A method and apparatus to cluster nodes of a hypergraph is described. The method improves the clustering by placing the hypergraph into an N-dimensional space. The method receives a design represented by a hypergraph with a plurality of nodes. The method places the plurality of nodes of the hypergraph into... Agent:

20150007121 - Chip cross-section identification and rendering during failure analysis: A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where potential electrical defect might be... Agent:

20150007122 - Generating a semiconductor component layout: A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components.... Agent:

20150007123 - Systems and methods for designing and making integrated circuits with consideration of wiring demand ration: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand... Agent:

20150007124 - Method and system of change evaluation of an electronic design for verification confirmation: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature... Agent:

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