Data processing: design and analysis of circuit or semiconductor mask inventions

20090271747 - Logic circuit designing device, logic circuit designing method and logic circuit designing program for asynchronous logic circuit: A logic circuit designing device for designing an asynchronous logic circuit which satisfies characteristic constraints of a state holding element represented by a latch or a flip-flop is provided. A signal transition series which generates a control signal pulse of the state holding element is extracted by the state storage... Agent: Nec Corporation Of America

20090271746 - Method of circuit power tuning through post-process flattening: A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of the at least one reused cell are... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090271748 - Method and apparatus for simulating behavioral constructs using indeterminate values: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090271749 - Pattern-clip-based hotspot database system for layout verification: One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090271751 - Method and apparatus for statistical path selection for at-speed testing: In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip... Agent: Wall & Tong, LLP IBM Corporation

20090271750 - Timing constraint merging in hierarchical soc designs: A method for propagating timing constraints from lower level design blocks to higher level design blocks includes o the steps of designing a circuit containing a plurality of design blocks. Each of the plurality of design blocks has a set of timing constraints associated therewith. A composite set of timing... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090271752 - Legalization of vlsi circuit placement with blockages using hierarchical row slicing: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and... Agent: Ibm Corporation (jvm)

20090271753 - Methods for cell phasing and placement in dynamic array architecture and implementation of the same: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists... Agent: Martine Penilla & Gencarella, LLP

20090271754 - Method and apparatus for computing a detailed routability estimation: One embodiment of the present invention provides a system that computes a routability estimation across a collection of local routing regions associated with a circuit layout. This system first selects a first local routing region associated with a route overflow, wherein a respective local routing region is associated with an... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090271755 - Unified layer stack architecture: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090271756 - Minimal leakage-power standard cell library: A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090271759 - Contrast-based resolution enhancement for photolithographic processing: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.... Agent: Klarquist Sparkman, LLP

20090271757 - Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation: A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers... Agent: Hoffman Warnick LLC

20090271758 - Methods for forming arrays of small, closely spaced features: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed... Agent: Knobbe Martens Olson & Bear LLP

20090265673 - Intersect area based ground rule for semiconductor design: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical... Agent: Scully, Scott, Murphy & Presser, P.C.

20090265672 - Method and system for entry and verification of parasitic design constraints for analog integrated circuits: A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on... Agent: Texas Instruments Incorporated

20090265674 - Methods for identifying failing timing requirements in a digital design: Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090265675 - On chip local mosfet sizing: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090265676 - Method for designing semiconductor integrated circuit: A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090265677 - Integrated test waveform generator (twg) and customer waveform generator (cwg), design structure and method: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090265678 - System and method of resistance based memory circuit parameter adjustment: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting... Agent: Qualcomm Incorporated

20090265679 - System and method of predicting problematic areas for lithography in a circuit design: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking... Agent: Greenblum & Bernstein, P.L.C

20090265680 - Method and system for correcting a mask pattern design: A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090259978 - Arrangement verification apparatus: An arrangement verification apparatus that makes it possible to shorten a time it takes to complete a failure/no-failure test on the arrangement of control circuits that control block circuits is provided. The arrangement verification apparatus arranges block circuits to be controlled comprising a semiconductor device and control circuits that control... Agent: Mcdermott Will & Emery LLP

20090259977 - Assessing resources required to complete a vlsi design: A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections,... Agent: Ibm-rochester C/o Toler Law Group

20090259979 - Design tool and method for automatically identifying minimum timing violation corrections in an integrated circuit design: A design tool for automatically identifying minimum timing violation corrections in an integrated circuit (IC) design includes program instructions executable by a processor to identify locations to add a delay along each circuit path having a minimum timing violation. The tool may also sequentially try each of a plurality of... Agent: Mhkkg/sun

20090259981 - Integrated circuit with areas having uniform voltage drop and method therefor: A method that determines the maximum number of logic cells that can be placed in a predetermined area on the base of an integrated circuit, and meet a voltage drop requirement. The method iteratively changes the logic cell spacing until the voltage drop requirement is made. This is done prior... Agent: Vedder Price P.C.

20090259980 - Method and system for concurrent buffering and layer assignment in integrated circuit layout: A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to... Agent: Dillon & Yudell LLP

20090259983 - Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning: A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090259982 - Netlist cell identification and classificiation to reduce power consumption: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured... Agent: Nvidia C/o Murabito, Hao & Barnes LLP

20090259984 - Method of printed circuit boards: A design method of printed circuit boards includes the following steps. First, simulate a printed circuit board including power layers, and vias connected to all the power layers. Then, change connections of the vias that tend to draw too much current to be connected to fewer power layers, than the... Agent: PCe Industry, Inc. Att. Steven Reiss

20090254870 - Automatic transistor arrangement device to arrange serially connected transistors, and method thereof: When first and second hard macro transistors are arranged adjacently to each other, based on a circuit connection information and potentials of the first and second hard macro transistors are equal, a first programmable transistor is obtained by removing an unwanted diffusion region or an unwanted contact in the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20090254872 - Method for designing and manufacturing a pmos device with drain junction breakdown point located for reduced drain breakdown voltage walk-in: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far... Agent: Girard & Equitz LLP

20090254871 - Methods for hierarchical noise analysis: Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic... Agent: Law Offices Of Mark L. Berrier

20090254873 - Circuit board analyzer and analysis method: A circuit board analyzer includes a storage unit for storing mesh position information on an analyzed mesh-division model and extracted circuit constants in relation to each other; a division-model configuration unit for dividing the layout of a circuit board into meshes to configure a new mesh-division model; an identical-mesh determination... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090254874 - Methods and systems for placement and routing: Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20090254875 - Proactive routing system and method: There is provided a proactive routing system and method. In some embodiments, the method includes determining slack for a net in a netlist, applying a routing condition to the net, calculating an extra delay related to the routing condition, determining a criticality of the net considering the extra delay and... Agent: Fish & Richardson P.C.