|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor maskBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/16/2015 > 10 patent applications in 10 patent subcategories.
20150106771 - Method of lithographic process evaluation: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding... Agent:
20150106772 - Method for fracturing and forming a pattern using shaped beam charged particle beam lithography: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of... Agent:
20150106773 - Methodology for pattern correction: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having... Agent:
20150106774 - High-level synthesis data generation apparatus, high-level synthesis apparatus, and high-level synthesis data generation method: An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (CDFG information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates... Agent:
20150106775 - Method and system of change evaluation of an electronic design for verification confirmation: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature... Agent:
20150106776 - Techniques for generating microcontroller configuration information: A method and apparatus for configuring a programmable device, wherein a user may select from pre-defined user modules to select a configuration and corresponding function, representations of which are each displayed to the user, and instructions, based on the selected module, are automatically generated and used by the programmable device... Agent:
20150106777 - Method and system for three-dimensional layout design of integrated circuit elements in stacked cmos: A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20150106778 - System for designing network on chip interconnect arrangements: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional... Agent:
20150106779 - Methodology for pattern density optimization: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more... Agent:
20150106780 - Semiconductor device reliability model and methodologies for use thereof: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when... Agent:04/09/2015 > 13 patent applications in 11 patent subcategories.
20150100927 - Chip level critical point analysis with manufacturer specific data: A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20150100928 - Complex layout-based topological data analysis of analog netlists to extract hierarchy and functionality: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein... Agent:
20150100929 - Reverse synthesis of digital netlists: A method and method of extracting information from a netlist. The netlist for a device under test (DUT) is read and a circuit selected to be transformed. Transformation candidates are identified using transformation specific criteria and verification methods are applied to prove the transformation is equivalent to the circuit being... Agent:
20150100931 - Adaptive clock management in emulation: Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software... Agent: Mentor Graphics Corporation
20150100930 - Sustainable differentially reliable architecture for dark silicon: For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map... Agent: Utah State University
20150100932 - Manipulation of traces for debugging a circuit design: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables... Agent: Jasper Design Automation, Inc.
20150100933 - Manipulation of traces for debugging behaviors of a circuit design: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables... Agent: Jasper Design Automation, Inc.
20150100934 - Integrated transformer synthesis and optimization: A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired... Agent: Helic S.a
20150100935 - Method of determining if layout design is n-colorable: A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a layout design. Each candidate cell of the set of candidate cells is one of the set of base... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20150100936 - Register clustering for clock network topology generation: In some embodiments, in a method, a physical netlist of a placed IC chip design is received. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained. Weights to the register pairs are assigned based on the timing criticalities of the register... Agent:
20150100937 - Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros: A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets... Agent: International Business Machines Corporation
20150100938 - Spine routing with multiple main spines: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins... Agent:
20150100939 - Semiconductor device burn-in stress method and system: Burn-in (BI) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from BI board (BIB) contacts to device under test (DUT) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller. The control devices can be included in the BIB or... Agent: International Business Machines Corporation04/02/2015 > 17 patent applications in 13 patent subcategories.
20150095857 - Method and system for multi-patterning layout decomposition: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph.... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20150095858 - Method, program product and apparatus for performing double exposure lithography: A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process. In embodiments, the invention provides a double exposure lithography method which trims (i.e., removes) unwanted SB residues from the substrate, that is suitable... Agent:
20150095859 - Photolithography mask synthesis for spacer patterning: Photolithography mask synthesis is disclosed for spacer patterning masks. In one example, backbone features are extracted from a target layout of a mask design. A connectivity graph is generated based on the target layout in which lines of the backbone features are represented as nodes on the connectivity graph. The... Agent:
20150095860 - Method for arranging and wiring reconfigurable semiconductor device, program therefor, and arranging and wiring apparatus: An arrangement and wiring method of a reconfigurable semiconductor device, including: generating a net list based on a circuit description in which a circuit configuration is described; extracting a sequential circuit data set which is to be scanned from the net list; generating a first truth value table data set... Agent:
20150095861 - Method for producing a dpa-resistant logic circuit: In an application-specific integrated circuit (ASIC), a description of the logic circuit is formulated in a hardware description language and then converted into a description of a corresponding physical circuit, i.e., into a netlist, using a conversion program, i.e., a synthesis tool. The description at least largely consisting of standard... Agent: Siemens Ag Ö Sterreich
20150095862 - Visualization constraints for circuit designs: A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform... Agent: Jasper Design Automation, Inc.
20150095863 - Integrated circuit design using dynamic voltage scaling: A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply... Agent:
20150095864 - Power rail for preventing dc electromigration: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20150095865 - Legalizing a multi-patterning integrated circuit layout: In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints... Agent:
20150095866 - Vlsi circuit signal compression: An embedded agent (104) of an integrated circuit (102) includes a collector (220) configured to receive from a tested target circuit a plurality of single bit lines of signals and a signal canceller (322) configured to receive an indication of lines that are not to be exported, for a given... Agent:
20150095867 - Semiconductor circuit design method, memory compiler and computer program product: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to... Agent:
20150095868 - Method of converting between non-volatile memory technologies and system for implementing the method: A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge... Agent:
20150095869 - Method of making semiconductor device and a control system for performing the same: A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20150095870 - Methods for double-patterning-compliant standard cell design: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning... Agent:
20150095871 - Circuit design support method, computer product, circuit design support apparatus, and semiconductor integrated circuit: A circuit design support method includes obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit; and calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to... Agent: Fujitsu Optical Components Limited
20150095872 - Global router using graphics processing unit: For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing... Agent: Utah State University
20150095873 - Metal lines for preventing ac electromigration: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.03/26/2015 > 9 patent applications in 6 patent subcategories.
20150089457 - Hierarchical approach to triple patterning decomposition: A mechanism is provided in a data processing system for hierarchical triple patterning decomposition. The mechanism receives an integrated circuit design. The mechanism enforces boundary conditions on three-color mapping of shapes in a layer of the integrated circuit design at the cell level. The mechanism places cells in the layer... Agent: International Business Machines Corporation
20150089458 - Systems and methods for mitigating print-out defects: The present disclosure provides methods and systems for mitigating print-out defects that result during semiconductor simulation and/or fabrication. One of the methods disclosed herein includes steps of receiving a first desired sub-layout and a second desired sub-layout and of optimizing the first desired sub-layout and the second desired sub-layout to... Agent:
20150089459 - Design rule and lithographic process co-optimization: A computer-implemented method for obtaining values of one or more design variables of one or more design rules for a pattern transfer process comprising a lithographic projection apparatus, the method comprising. simultaneously optimizing one or more design variables of the pattern transfer process and the one or more design variables... Agent: Asml Netherlands B.v.
20150089460 - Method of performing optical proximity correction for preparing mask projected onto wafer by photolithography: A method of performing optical proximity correction for preparing a mask projected onto a wafer by photolithography includes the following steps. An integrated circuit layout design including a first feature and a second feature is obtained, wherein the first feature overlaps a first boundary of two structures in the wafer.... Agent:
20150089461 - Methods for generating schematic diagrams and apparatuses using the same: An embodiment of the invention introduces a method for generating schematic diagrams, executed by a processing unit of an apparatus, which comprises the following steps. A pin-editing interface comprising a data table is generated to assist a user to configure pin settings. A user setting is obtained via the pin-editing... Agent: Wistron Corp.
20150089462 - Concurrent optimization of timing, area, and leakage power: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is... Agent:
20150089463 - Method of failure analysis: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the... Agent:
20150089465 - Separation and minimum wire length constrained maze routing method and system: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path... Agent:
20150089464 - System and method for generating a field effect transistor corner model: Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within... Agent: International Business Machines CorporationPrevious industry: Data processing: presentation processing of document
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