|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor maskBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/07/2014 > 17 patent applications in 13 patent subcategories.
20140223391 - Recognition of template patterns with mask information: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140223390 - Retargeting semiconductor device shapes for multiple patterning processes: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in... Agent: Globalfoundries Inc.
20140223389 - System and method to design and test a yield sensitive circuit: A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between... Agent: Qualcomm Incorporated
20140223393 - Method and system for forming high accuracy patterns using charged particle beam lithography: A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the... Agent: D2s, Inc.
20140223392 - Optimized optical proximity correction handling for lithographic fills: An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar... Agent: Globalfoundries Inc.
20140223395 - Boosting transistor performance with non-rectangular channels: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate... Agent: Synopsys, Inc.
20140223394 - Methods for manufacturing integrated circuit devices having features with reduced edge curvature: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line... Agent: Synopsys, Inc.
20140223396 - Pattern-based replacement for layout regularization: Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout. The regularized layout is then subjected to additional mask data preparation processing, such... Agent:
20140223397 - Automatic generation of wire tag lists for a metal stack: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers... Agent: International Business Machines Corporation
20140223398 - Method for determining interface timing of integrated circuit automatically and related machine readable medium thereof: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path... Agent: Realtek Semiconductor Corp.
20140223399 - Circuit analysis device and circuit analysis method: A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a... Agent: Fujitsu Limited
20140223400 - Numerical delay model for a technology library cell type: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a... Agent: Synopsys, Inc.
20140223401 - High-frequency vlsi interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy... Agent: Mentor Graphics Corporation
20140223402 - Multi-board design apparatus, multi-board design method, program and computer-readable recording medium: In order to always maintain connection relationships between substrates of the multi-board, a multi-board design apparatus for designing a multi-board comprising a plurality of substrates which are electrically connected is made to have: setting means by which a designer sets connection information indicating a connection relationship between each substrate configuring... Agent: Zuken Inc.
20140223403 - Method and apparatus for performing parallel routing using a multi-threaded routing procedure: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of... Agent: Altera Corporation
20140223404 - Gate-length biasing for digital circuit optimization: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.... Agent: Tela Innovations, Inc.
20140223405 - Method and apparatus for providing a layout defining a structure to be patterned onto a substrate: A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.... Agent: Infineon Technologies Ag07/31/2014 > 17 patent applications in 13 patent subcategories.
07/24/2014 > 10 patent applications in 8 patent subcategories.
20140208278 - Pattern selection for lithographic model calibration: The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects... Agent: Asml Netherlands B.v.
20140208279 - System and method of testing through-silicon vias of a semiconductor die: A method includes contacting a first group of through-silicon vias (TSVs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The... Agent: Qualcomm Incorporated
20140208282 - Conflict detection for self-aligned multiple patterning compliance: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing... Agent: Taiwan Semiconductor Manufacturing Compnay Limited
20140208280 - Modeling mechanical behavior with layout-dependent material properties: Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated... Agent: Synopsys, Inc.
20140208281 - Real-time display of electronic device design changes between schematic and/or physical representation and simplified physical representation of design: A logical design component permits an electronic device design to be modified from a logical perspective on a schematic of the device showing device components in logical form, and displays a logical window of the schematic. A physical design component permits the design to be modified from a circuit board... Agent: International Business Machines Corporation
20140208283 - Dummy shoulder structure for line stress reduction: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140208284 - Method and system for designing 3d semiconductor package: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first... Agent:
20140208285 - Self-aligned double patterning via enclosure design: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and... Agent: Globalfoundries Inc.
20140208286 - System and method for designing via of printed circuit board: A via design method includes doing a simulation according to input data to obtain the impedance of the via of the reference printed circuit board (PCB). An optimal via model is determined according to a group of input data. Simulating is performed according to the thickness of a PCB to-be-designed... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.
20140208287 - Energy consumption simulation and evaluation system for embedded device: An energy consumption simulation and evaluation system for embedded device in energy consumption evaluation technology for electronic devices, which solves the problem that the energy consumption cannot be simulated under tasks operation condition with the existing systems. The present invention includes a graphical configuration management module for inputting graphical configuration... Agent: Harbin Institute Of Technology07/17/2014 > 10 patent applications in 9 patent subcategories.
20140201691 - Layout decomposition method and method for manufacturing semiconductor device applying the same: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including... Agent: United Microelectronics Corp.
20140201692 - Pre-colored methodology of multiple patterning: Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140201693 - Automating integrated circuit device library generation in model based metrology: Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and... Agent: International Business Machines Corporation
20140201694 - Wrap based fill in layout designs: Techniques for “wrapping” functional geometric elements with fill geometric elements are provided. With some implementations, functional geometric elements, such as geometric elements representing metal contact and interconnect structures, are identified in layout design data. Next, fill regions requiring fill geometric elements are identified. If a portion of a functional geometric... Agent: Mentor Graphics Corporation
20140201695 - Power grid design for integrated circuits: A method of generating a power grid to supply current to a plurality of cells of an integrated circuit includes routing an initial power grid representing a power usage estimate for the plurality of cells. The method also includes performing power grid analysis prior to routing of signal wires to... Agent: International Business Machines Corporation
20140201696 - Support apparatus and design support method: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving... Agent: Fujitsu Limited
20140201697 - Determining overall optimal yield point for a semiconductor wafer: A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where... Agent: International Business Machines Corporation
20140201698 - Area efficient power switch: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the... Agent: Apple Inc.
20140201700 - Apparatus for modeling of finfet width quantization: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes... Agent: International Business Machines Corporation
20140201699 - Methods for modeling of finfet width quantization: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes... Agent: International Business Machines CorporationPrevious industry: Data processing: presentation processing of document
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