Data processing: design and analysis of circuit or semiconductor mask inventions

20100023896 - Method of designing a multi-winding device: A method for designing a transformer using three secondary winding phase shift angles and a minimized core cross-sections. The method includes receiving an indication of an acceptable level of total harmonic distortion (THD) for the transformer, identifying a desired number of secondary windings per output phase of the transformer, simulating... Agent: Siemens Corporation Intellectual Property Department

20100023899 - Analysis of stress impact on transistor performance: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20100023900 - Analysis of stress impact on transistor performance: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20100023901 - Analysis of stress impact on transistor performance: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20100023902 - Analysis of stress impact on transistor performance: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20100023898 - Circuit design assisting apparatus, computer-readable medium storing circuit design assisting program, and circuit design assisting method: A circuit design assisting apparatus for assisting designing of a circuit is provided. The apparatus includes a storage unit that stores information regarding a configuration of components used in a design-target circuit and wirings between the components, an acquiring unit that acquires label setting information that associates a label with... Agent: Staas & Halsey LLP

20100023897 - Property-based classification in electronic design automation: One or more properties can be associated with a design object in a microdevice design. These properties then can be used to classify relationships in a circuit design, such as a layout circuit design. In some implementations, the various relationships can be classified based upon the similarity or dissimilarity of... Agent: Mentor Graphics Corp. Patent Group

20100023903 - Method and apparatus for multi-die thermal analysis: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the... Agent: Adeli & Tollen, LLP

20100023904 - Method and apparatus for generating memory models and timing database: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are... Agent: Westman Champlin & Kelly, P.A.

20100023905 - Critical area deterministic sampling: A layout design for a portion of a microdevice design is partitioned into sections or “bins.” Next, a critical area value is estimated for one or more of the bins. One or more of these estimated bins is then selected for a more detailed analysis. After the estimated bins have... Agent: Mentor Graphics Corp. Patent Group

20100023906 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that... Agent: Martine Penilla & Gencarella, LLP

20100023907 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding p-type and n-type diffusion regions separated by central: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that... Agent: Martine Penilla & Gencarella, LLP

20100023908 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors and having corresponding p-type and n-type diffusion regions separated by central inac: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped... Agent: Martine Penilla & Gencarella, LLP

20100023909 - Voltage fluctuation estimating method and apparatus, semiconductor device operation verification apparatus, semiconductor device designing method, printed circuit board designing method, and program: A computer determines a first relationship between a maximum frequency of the semiconductor device and an internal power supply voltage of the semiconductor device. Then, the computer determines a second relationship between the maximum frequency and an amount of noise, based on a number of the input/output signal pins. In... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100023911 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel... Agent: Martine Penilla & Gencarella, LLP

20100023910 - Method of packing-based macro placement and semiconductor chip using the same: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100023912 - Lead frame design support apparatus and lead frame design support method: A lead frame design support apparatus and method include measuring a signal waveform transition time, calculating a distributed parameter unit length based on the transition time measured, calculating a division number for a lead frame by dividing the lead frame by the distributed parameter unit length calculated, and determining a... Agent: Staas & Halsey LLP

20100023913 - Method for ic wiring yield optimization, including wire widening during and after routing: Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20100023915 - Calculation system for inverse masks: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares... Agent: Mentor Graphics Corp. Patent Group

20100023916 - Model based hint generation for lithographic friendly design: In various implementations of the invention, a model of an optical proximity correction process is employed to determine potential adjustments to a layout design for a mask that might resolve potential errors an image resulting from application of the mask in an optical lithographic process. In various implementations of the... Agent: Mentor Graphics Corp. Patent Group

20100023917 - Tool for modifying mask design layout: An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to... Agent: Greer, Burns & Crain

20100023914 - Use of graphs to decompose layout design data: Techniques are disclosed for determining if the decomposition of layout design data is feasible, and for optimizing the segmentation of polygons in decomposable layout design data. Layout design data is analyzed to identify the edges of polygons that should be imaged by separate lithographic masks. In addition, proposed cut paths... Agent: Mentor Graphics Corp. Patent Group

20100017760 - Test design optimizer for configurable scan architectures: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20100017761 - Data conversion apparatus, data conversion method, and computer-readable recording medium storing program: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the... Agent: Fujitsu Patent Center C/o Cpa Global

20100017762 - Implementing integrated circuit yield estimation using voronoi diagrams: A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment,... Agent: Cantor Colburn LLP - IBM Fishkill

20100017763 - Stochastic steady state circuit analyses: A method for simulating a system without a time invariant or periodically time-varying steady state is provided. The method limits the number of states included in a Markov chain model by discretizing the states based on Gaussian decomposition, utilizes a state exploration algorithm that discovers only recurrent states, and/or utilizes... Agent: Hickman, Palermo, Truong, & Becker/ Rambus

20100017764 - Functional verification of power gated designs by compositional reasoning: A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look... Agent: Ibm Corporation, T.j. Watson Research Center

20100017765 - Monitor position determining apparatus and monitor position determining method: A monitor position determining apparatus includes an acquiring unit that acquires design data concerning circuit elements arranged in a layout of a semiconductor device and for each of the circuit elements, yield sensitivity data indicative of a percentage of change with respect to a yield ratio of the semiconductor device;... Agent: Greer, Burns & Crain

20100017771 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout defined to include a number of linear-shaped... Agent: Martine Penilla & Gencarella, LLP

20100017772 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors with corresponding p-type and n-type diffusion regions separated by central inactive region: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout... Agent: Martine Penilla & Gencarella, LLP

20100017769 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout is defined to include a number of... Agent: Martine Penilla & Gencarella, LLP

20100017770 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors with corresponding p-type and n-type diffusion regions separated by central inactive region: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout... Agent: Martine Penilla & Gencarella, LLP

20100017767 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features defined along at least four gate electrode tracks: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The layout of the cell also includes a gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend... Agent: Martine Penilla & Gencarella, LLP

20100017768 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding p-type and n-type diffusion regions separated by central inactive region: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes to be formed within a portion of a substrate, including a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by... Agent: Martine Penilla & Gencarella, LLP

20100017766 - Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors: A restricted layout region includes a diffusion level layout including diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout... Agent: Martine Penilla & Gencarella, LLP

20100017773 - Method for minimizing impact of design changes for integrated circuit designs: A method is provided for updating an existing netlist to reflect a design change. A design incorporating the design change and the existing netlist are provided to a synthesis tool. The design and the existing netlist are processed with the synthesis tool reusing logic structures from the existing netlist. A... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20100017774 - Method and system for mounting circuit design on reconfigurable device: There is provided a system for generating configuration data for implementing a circuit design in a segmented reconfigurable device. A placement and routing design aiding system (30) includes a database (31) for storing hardware information (89) including data of PEs included in each segment and data of a first-level and... Agent: Marshall, Gerstein & Borun LLP

20100017775 - Semiconductor integrated circuit device: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are... Agent: Miles & Stockbridge PC

20100017776 - Design program, design apparatus, and design method for dynamic reconfigurable circuit: A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network... Agent: Arent Fox LLP

20100017777 - Method and apparatus for synthesizing a hardware system from a software: A method and an apparatus take software source code to synthesize a hardware platform for running the software. The method determines which processor is suitable for running the code and meeting the performance parameters determined by the user. The method also determines which hardware devices are accessed by software. If... Agent: Robert Marc Zeidman

20100017778 - Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same: Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of a rectangular target geometry may comprise predicting a contour of an image to be produced in an optical proximity... Agent: Trask Britt, P.C./ Micron Technology

20100017780 - Differential alternating phase shift mask optimization: A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width... Agent: Law Office Of Delio & Peterson, LLC.

20100017779 - Method for decomposing designed pattern layout and method for fabricating exposure mask using the same: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct... Agent: Marshall, Gerstein & Borun LLP

20100011324 - Structured placement for bit slices: Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100011325 - Method and apparatus for determining the effect of process variations: Embodiments of the present invention provide systems and techniques for determining the effect of process variations. During operation, the system can receive a layout which includes multiple instances of a pattern. Next, the system can correct the pattern instances using different photolithography process models which model the photolithography process at... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20100011326 - Printed circuit board design support program, recording medium, and printed circuit board design support method: To automatically arrange vias on a printed circuit board so as to satisfy a predetermined condition. A printed circuit board design support method for causing a computer to execute a ground conductive area identifying conductive areas which can be used as grounds of a printed circuit board having a plurality... Agent: Canon U.s.a. Inc. Intellectual Property Division

20100011327 - Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features and at least eight transistors: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The... Agent: Martine Penilla & Gencarella, LLP

20100011328 - Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is defined above the diffusion level layout... Agent: Martine Penilla & Gencarella, LLP

20100011330 - Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing with corresponding non-symmetric diffusion regions: A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level... Agent: Martine Penilla & Gencarella, LLP

20100011333 - Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a substrate portion of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode... Agent: Martine Penilla & Gencarella, LLP

20100011332 - Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region.... Agent: Martine Penilla & Gencarella, LLP

20100011331 - Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing with corresponding non-symm: A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout... Agent: Martine Penilla & Gencarella, LLP

20100011329 - Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region.... Agent: Martine Penilla & Gencarella, LLP

20100011334 - Method and system for designing a probe card: A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer... Agent: N. Kenneth Burraston Kirton & Mcconkie

20100011335 - Grid-based fragmentation for optical proximity correction in photolithography mask applications: An optical proximity correction (OPC) method for photolithography applications can be utilized to reduce the processing time, cost, and post-OPC file size associated with conventional methods. The OPC method provides a target layout pattern that represents a corresponding mask pattern for a photolithography mask, and aligns the target layout pattern... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20100005429 - Integrated single spice deck sensitization for gate level tools: One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20100005431 - Converting a synchronous circuit design into an asynchronous design: Methods and systems for converting synchronous circuit designs to asynchronous circuit designs are described. A method may include converting a synchronous circuit design to an asynchronous dataflow design. Functional characteristics of the synchronous circuit design may be determined. The synchronous circuit design may include multiple synchronous logic blocks and a... Agent: Schwegman, Lundberg & Woessner, P.A.

20100005430 - Ddcc and fdccii-grounded resistor and capacitor filter structures: A voltage-mode nth-order differential difference current conveyor (DDCC) and fully differential current conveyor (FDCCII)-resistor and capacitor filter structures are proposed using a new effective analytical synthesis method (ASM), a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and... Agent: Hdls Ipr Services

20100005432 - Floating net inspection method: A floating net inspection method includes: providing a netlist which describes a circuit structure of an application circuit, the application circuit including a plurality of transistors; coupling a power supply port and a signal input port of the application circuit to voltage sources, respectively; generating test voltages respectively through the... Agent: Pearl Cohen Zedek Latzer, LLP

20100005433 - Circuit design apparatus and circuit design method: A circuit design apparatus for designing an LSI including a memory circuit for storing data and an error protection circuit for performing an error protection over the data stored in the memory circuit on the basis of design information, the circuit design apparatus includes: an extracting unit for extracting information... Agent: Greer, Burns & Crain

20100005434 - Verifying an ic layout in individual regions and combining results: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across... Agent: Silicon Valley Patent Group LLP Attn: Syn

20100005435 - System and method for modeling i/o simultaneous switching noise: The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20100005436 - Method and apparatus for characterizing an integrated circuit manufacturing process: A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout,... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20100005437 - Methods and systems for computer aided design of 3d integrated circuits: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two... Agent: Seyfarth Shaw LLP

20100005438 - Processing method. processing equipment, program and computer-readable storage medium: Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100005439 - Designing method of semiconductor integrated circuit: A designing method of a semiconductor integrated circuit is provided, the method including a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping... Agent: Arent Fox LLP

20100005440 - Calibration and verificataion structures for use in optical proximity correction: A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging... Agent: International Business Machines Corporation Dept. 18g

20100005441 - Method of designing a mask layout: In a method of designing a mask layout, a wiring region for forming a metal wire is established, the wiring region having at least a standard width. Contact regions for forming contacts electrically connected to the metal wire are established in the wiring region. The contact regions adjacent to each... Agent: Myers Bigel Sibley & Sajovec

20100005442 - Apparatus and methods for determining overlay and uses of same: Disclosed are techniques and apparatus are provided for determining overlay error or pattern placement error (PPE) across the field of a scanner which is used to pattern a sample, such as a semiconductor wafer or device. This determination is performed in-line on the product wafer or device. That is, the... Agent: Weaver Austin Villeneuve Sampson LLP - Kla Tencor Kla Tencor