|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
USPTO Class 716 | Browse by Industry: Previous - Next | All
Recent | 13: May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Data processing: design and analysis of circuit or semiconductor maskBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/16/2013 > 16 patent applications in 13 patent subcategories.
20130125070 - Opc checking and classification: A technique for selecting a subset of determined defects in a mask pattern is described. In this technique, defects in the mask pattern may be determined based on differences between a pattern produced at an image plane in a photolithographic process, when the mask pattern, illuminated by an associated source... Agent:
20130125071 - Circuit component migration apparatus, circuit component migration program, and circuit component migration method: An circuit-component-migration-apparatus includes a storage unit that stores correspondence information indicating a circuit component of a migration destination corresponding to a circuit component of a migration source, an identification unit that identifies a circuit component of the migration destination corresponding to a circuit component that is a target to be... Agent: Fujitsu Limited
20130125072 - System and method of detecting design rule noncompliant subgraphs in circuit netlists: An automated system and method of performing electronic design rule checking on the netlist of an integrated circuit composed of a plurality of subgraphs. The electronic design rule is embodied as a two part template with a target subgraph specification and a design rule compliance check specification. The target subgraph... Agent:
20130125073 - Test path selection and test program generation for performance testing integrated circuit chips: A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains;... Agent: International Business Machines Corporation
20130125075 - Method for rapid estimation of layout-dependent threshold voltage variation in a mosfet array: An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si... Agent: Synopsys, Inc.
20130125074 - System and method for designing digital circuitry with an activity sensor: A system for designing digital circuitry comprising: a digital circuit simulator based on a file containing a functional description of this digital circuit; means for estimating an output variable from the digital circuit when executing a test bench supplied to the simulator; event counters, the events being detected using control... Agent: Commissariat A L'energie Atomique Et Aux Energies Alternatives
20130125076 - Disposition of integrated circuits using performance sort ring oscillator and performance path testing: A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock... Agent: International Business Machines Corporation
20130125077 - Method for optimising cell variant selection within a design process for an integrated circuit device: A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further... Agent: Freescale Semiconductor, Inc.
20130125078 - Interactive routing editor with symbolic and geometric views for integrated circuit layout: An automated system, and method of operating the same, for interactively routing interconnections in a layout of an integrated circuit. Interconnections among subchips in the integrated circuit, specified by a netlist, are displayed by the system by way of airlines. The system provides a symbolic view of the bus, showing... Agent: Texas Instruments Incorporated
20130125079 - On chip inductor with frequency dependent inductance: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on... Agent: International Business Machines Corporation
20130125080 - Circuit optimization method and apparatus for analog circuit migration: A circuit optimization apparatus and a circuit optimization method used in analog circuit migration which migrates a source circuit to a target circuit are disclosed. The circuit optimization method comprises: dividing the source circuit into at least one direct current path; determining an adaptation sequence of the at least one... Agent:
20130125081 - Automated circuit design using active set solving process: A method is described that involves solving a family of equations for a circuit being designed over a subset of operational scenarios, thereby producing numeric values for design parameters of the circuit. The family of equations is enhanced with the numeric values are solved over a second subset of the... Agent:
20130125082 - Computing device and method for automatically checking wiring information: In a computing device, a computerized method and a non-transitory storage medium are applied in checking a stored wiring diagram for high-noise components in close proximity to signal lines. An electronic component is selected in a PCB wiring file. A checking range of the selected electronic component is determined for... Agent: Hon Hai Precision Industry Co., Ltd.
20130125083 - Power-supply design system, power-supply design method, and program for power-supply design: A power-supply design system for designing a power supply of electronic equipment apparatuses. The system includes an input device for inputting circuit information about the power supply of the electronic equipment apparatus; a current deviation computation unit that computes an electric current deviation which indicates electric current variation of the... Agent:
20130125084 - Wiring-design support device, recording medium for wiring-design support program, and method for wiring-design support: A wiring-design support device supports wiring design of a printed circuit board. The processor executes a process that includes holding, in the memory, wiring information including information relating to a plurality of signal wires to be wired in parallel between two components on the printed circuit board, generating a wiring... Agent: Fujitsu Limited
20130125085 - Development support apparatus of semiconductor device, development support method, and development support program product: Disclosed is a development support apparatus of a semiconductor device that makes it possible to easily develop the semiconductor device, a development support method, and a program product. A design evaluation apparatus is a design evaluation apparatus having an analog front-end unit for inputting a measurement signal of a sensor... Agent: Renesas Electronics Corporation05/09/2013 > 5 patent applications in 5 patent subcategories.
20130117720 - Computer product for supporting design and verification of integrated circuit: Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step;... Agent: Fujitsu Limited
20130117721 - Method and system for verification of electrical circuit designs at process, voltage, and temperature corners: A method for finding the process, voltage, temperature, parasitics, and power settings (PVTPP) corner at which an electrical circuit design has the worst-case optimum simulated output performance. The method uses a global optimization process in a series of iterations that aim to uncover the PVTPP corner at which the ECD... Agent: Solido Design Automation Inc.
20130117722 - Accelerating coverage convergence and debug using symbolic properties and local multi-path analysis: In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided... Agent: Synopsys, Inc.
20130117723 - Pattern shape evaluation method, pattern shape evaluation device, pattern shape evaluating data generation device and semiconductor shape evaluation system using the same: A pattern shape evaluation method and semiconductor inspection system having a unit for extracting contour data of a pattern from an image obtained by photographing a semiconductor pattern, a unit for generating pattern direction data from design data of the semiconductor pattern, and a unit for detecting a defect of... Agent: Hitachi High-technologies Corporation
20130117724 - Method for structuring a function plan into function plan sections: A method is disclosed for structuring a function plan into function plan sections. The function plan includes function modules. Individual function modules are connected to at least one other function module of at least one function module connection. If the function plan exceeds the predefined area of the function plan... Agent: Siemens Aktiengesellschaft05/02/2013 > 11 patent applications in 8 patent subcategories.
20130111417 - Database-driven cell-to-cell reticle inspection: A semiconductor inspection apparatus identifies regions of a reticle or semiconductor wafer appropriate for cell-to-cell inspection by analyzing a semiconductor design database. Appropriate regions can be identified in a region map for use by offline inspection tools.... Agent: Kla-tencor Corporation
20130111416 - Design data optimization method, storage medium including program for design data optimization method and photomask manufacturing method: According to one embodiment, a design data optimization method includes forming an angular aperture model, in first design data including a first and a second line patterns indicating an interconnect layout, based on an angular aperture between the first line pattern in which a conversion difference prediction point is set... Agent:
20130111418 - Method, system and software for accessing design rules and library of design features while designing semiconductor device layout: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130111420 - Mask data producing method and mask data producing program: Obtaining a function by convoluting a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of a projection optical system and a pupil function of the projection optical system. Calculating a Fourier transformed function by Fourier transforming the product of the obtained function and... Agent: Canon Kabushiki Kaisha
20130111419 - Method and system for modifying doped region design layout during mask preparation to tune device performance: The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130111421 - Method and apparatus for model based flexible mrc: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the... Agent: Asml Netherlands B.v.
20130111422 - Managing consistency of multiple-source fabrication data in an electronic design environment: Techniques and structures relating to consistency management for fabrication data are disclosed. A plurality of data sources may contain different values for a variety of design parameters usable by electronic circuit design tools to physically lay out at least a portion of an integrated circuit (such as minimum spacing rules,... Agent:
20130111424 - Logical repartitioning in design compiler: During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or... Agent:
20130111423 - Tool suite for rtl-level reconfiguration and repartitioning: A novel set of reconfiguration tools combine the RTL (Register Transfer Language) construct detection of synthesis compilers with a more advanced implementation of expansion syntax. HDL (Hardware Description Language) coding constructs are automatically detected and recoded and/or modified, for both behavioral and structural HDL code. Configuration file(s) may be used... Agent:
20130111425 - Power balanced pipelines: Power balancing techniques are provided for improving power efficiency of pipelined processors. A design-level implementation can be incorporated during synthesis of pipeline clocks in which a register transfer level (RTL) code, operating frequency, and available voltage domains are used to perform cycle time stealing with, and optimize for, power efficiency.... Agent: The Board Of Trustees Of The University Of Illinois
20130111426 - Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for asip de: Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more... Agent:04/25/2013 > 7 patent applications in 6 patent subcategories.
20130104091 - Tolerable flare difference determination: Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions... Agent: Mentor Graphics Corporation
20130104092 - Method, system and program storage device for performing a parameterized statistical static timing analysis (ssta) of an integrated circuit taking into account setup and hold margin interdependence: In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible... Agent: International Business Machines Corporation
20130104093 - System and method for reducing reconfiguration power usage: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at... Agent: Tabula, Inc.
20130104095 - Integrated circuit routing with compaction: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may... Agent: Pulsic Limited
20130104094 - Routing storage structure based on directional grid points and routing method thereof: The present invention provides a routing storage structure based on directional grid points and a routing method thereof. The routing storage structure includes a grid matrix having N×M grid points for storing a grid identifier corresponding to each grid point, where both N and M are natural numbers; a grid... Agent: Delta Electronics (shanghai) Co., Ltd.
20130104096 - Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics: One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs... Agent: Agere Systems LLC
20130104097 - Programmatic auto-convergent method for \"physical layout power hot-spot\" risk aware asip architecture customization for performance optimization: Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing... Agent:Previous industry: Data processing: presentation processing of document
Next industry: Data processing: software development, installation, and management
RSS FEED for 20130516:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Data processing: design and analysis of circuit or semiconductor mask patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Data processing: design and analysis of circuit or semiconductor mask patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Data processing: design and analysis of circuit or semiconductor mask patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 0.44847 seconds