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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
11/13/2014 > 5 patent applications in 5 patent subcategories.

20140337809 - Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure: A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first... Agent:

20140337810 - Modular platform for integrated circuit design analysis and verification: A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for... Agent: Mentor Graphics Corporation

20140337811 - Sub-module physical refinement flow: A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger... Agent: Synopsys, Inc.

20140337812 - Circuit verification method and circuit verification apparatus: A control section of a circuit verification apparatus acquires waveform data of output in a transient state of a verification target circuit by a circuit simulation and stores the waveform data in a storage section. When the control section detects input to a functional model of the verification target circuit... Agent:

20140337813 - Method and apparatus for extracting delay parameter: A delay parameter extracting apparatus includes a schematic composing unit, a layout composing unit, a verification unit, and a parameter extracting unit. The schematic composing unit is configured to: facilitate design of a schematic circuit; and generate a first net list based on the design of the schematic circuit. The... Agent: Samsung Display Co., Ltd.

11/06/2014 > 9 patent applications in 9 patent subcategories.

20140331191 - Method of correcting assist feature: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form... Agent: United Microelectronics Corp.

20140331192 - Semiconductor device and method for making the same using semiconductor fin density design rules: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The... Agent:

20140331193 - Method and device for increasing fin device density for unaligned fins: A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to... Agent:

20140331194 - Method for manufacturing a chip from a system definition: A method for manufacturing a chip from a system definition, the system definition describing a plurality of cells, buses and external I/O. The cell definitions are defined by providing two libraries, a first containing a superset of cell definitions; and a second a plurality of HDL definitions of cells selected... Agent: Pact Xpp Technologies Ag

20140331195 - Test bench hierarchy and connectivity in a debugging environment: This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding... Agent:

20140331196 - Analyzing sparse wiring areas of an integrated circuit design: A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing tiles. A set of sparse nets are determined from the set of nets, based on the utilization... Agent: International Business Machines Corporation

20140331197 - Sequential state elements in triple-mode redundant (tmr) state machines: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit... Agent: Arizona Board Of Regents On Behalf Of Arizona State University

20140331198 - Method for designing a physical layout of a photovoltaic system: A method for creating a physical layout of a photovoltaic system in a specified field is provided where the photovoltaic system is specified by a plurality of technical properties. The method includes reading out more than 20 pre-calculated, completed layouts for the photovoltaic system from a memory; presenting the completed... Agent: Siemens Aktiengesellschaft

20140331199 - Detecting corresponding paths in combinationally equivalent circuit designs: A method, apparatus and product for detecting corresponding paths in combinationally equivalent circuit designs. The method comprising: obtaining a first circuit design and a second circuit design, the first and second circuit designs have corresponding sets of input and output elements; obtaining a path in the first circuit design, the... Agent: International Business Machines Corporation

10/30/2014 > 10 patent applications in 9 patent subcategories.

20140325460 - Method for simulation of partial vlsi asic design: A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL... Agent: Bae Systems Information And Electronic Systems Intergration Inc.

20140325461 - Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis: A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least... Agent:

20140325462 - Partitioning designs to facilitate certification: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a... Agent:

20140325463 - Integrated circuit design verification through forced clock glitches: A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective... Agent: Freescale Semiconductor, Inc.

20140325464 - Conflict detection for self-aligned multiple patterning compliance: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing... Agent:

20140325465 - Chip with flexible pad sequence manipulation and associated method: A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for... Agent: Mstar Semiconductor, Inc.

20140325466 - Stretch dummy cell insertion in finfet process: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin... Agent:

20140325467 - Multiple-instantiated-module (mim) aware pin assignment: Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then... Agent:

20140325468 - Storage medium, and generation apparatus for generating transactions for performance evaluation: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process comprising: generating a transaction scenario that describes a dependency between operations of semiconductor elements included in a semiconductor circuit, according to a parameter for defining the dependency and waveform data that indicates... Agent: Fujitsu Semiconductor Limited

20140325469 - Apparatus and method for aiding in designing electronic circuits: First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each... Agent:

10/23/2014 > 10 patent applications in 8 patent subcategories.

20140317580 - Methods for performing model-based lithography guided layout design: Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window.... Agent: Asml Netherlands B.v.

20140317581 - Revising layout design through opc to reduce corner rounding effect: The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner... Agent:

20140317582 - Race logic synthesis for esl-based large-scale integrated circuit designs: Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, ESL (electronic system level) and any HDL (hardware description language) design source files of an IC design are compiled into a design database. Race logic analysis is performed on... Agent:

20140317583 - Managing and controlling the use of hardware resources on integrated circuits: Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed... Agent: Mentor Graphics Corporation

20140317584 - Formal fault detection: A method for formal fault detection in a design model includes providing a plurality of faults which are individually activatable in the design model, and providing a plurality of properties for the design model wherein each property of the plurality of properties is valid if none of the plurality of... Agent:

20140317585 - Crosstalk analysis method: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk... Agent:

20140317586 - Support device, design support method, and computer-readable recording medium: A design support device includes placement determination unit, logic extraction unit, and logic placement unit. The placement determination unit performs the process of determining the optimum position of a first terminal of a first cell as a first position in which the inter-terminal wiring between the first cell and a... Agent: Fujitsu Limited

20140317587 - Computing device and method for testing layout of power pin of chipset on circuit board: A testing system for testing a layout of a power pin of a chipset on a circuit board includes a layout information obtaining module, a power pin sorting module, a transmission line sorting module, a transmission line length calculating module, and a report generating module. The layout information obtaining module... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd

20140317588 - Timing operations in an ic with configurable circuits: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions... Agent: Tabula, Inc.

20140317589 - System and method for concurrent multi-user cax workflow: A system for concurrent CAx workflow includes a collaborative server that manages a model of an engineering object, the model comprising at least design data and analysis data corresponding to the design data, a design client for editing of the design data by a design user, an analysis client for... Agent: Brigham Young University

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