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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
02/05/2015 > 20 patent applications in 13 patent subcategories.

20150040077 - Multi-patterning mask decomposition method and system: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150040081 - Method and apparatus for integrated circuit mask patterning: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150040079 - Method for electron beam proximity correction with improved critical dimension accuracy: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150040078 - Methods and systems for designing and manufacturing optical lithography masks: A method of designing an optical photomask includes providing a target pattern, correcting the target pattern with an OPC model, adjusting the target pattern and/or the OPC model, and correcting a first corrected pattern. The target pattern indicates a target shape of a pre-pattern opening in a photoresist layer on... Agent: Globalfoundries, Inc.

20150040080 - Methods for modifying an integrated circuit layout design: Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design,... Agent: Globalfoundries, Inc.

20150040082 - Layout decomposition method: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the... Agent: Taiwan Semiconductor Manufacturing Comapny, Ltd.

20150040084 - Structure, method and system for complementary strain fill for integrated circuit chips: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed... Agent:

20150040083 - System and method for decomposition of a single photoresist mask pattern into 3 photoresist mask patterns: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150040085 - System and method for series and parallel combinations of electrical elements: A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve an arbitrary compound value is disclosed. A recursive algorithm successively adds one or more similar nominal two-terminal elements to generate a series and/or parallel compound combination of nominal elements, the... Agent:

20150040086 - Method and system for reproducing prototyping failures in emulation: A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.... Agent:

20150040087 - Identification of power sensitive scan cells: Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on... Agent: Mentor Graphics Corporation

20150040088 - Hybrid design rule for double patterning: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color... Agent: Taiwan Semiconductor Manufacturing Company Limited

20150040090 - Discretizing gate sizes during numerical synthesis: Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design... Agent: Synopsys, Inc.

20150040089 - Numerical area recovery: Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment... Agent: Synopsys, Inc.

20150040091 - Methods for modifying an integrated circuit layout design: Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer... Agent: Globalfoundries, Inc.

20150040092 - Stress migration mitigation: A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each... Agent: Freescale Semiconductor, Inc.

20150040093 - Robust numerical optimization for optimizing delay, area, and leakage power: Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical... Agent: Synopsys, Inc.

20150040094 - Sequential delay analysis by placement engines: Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes... Agent:

20150040095 - Method of improving timing critical cells for physical design in the presence of local placement congestion: Optimizing circuits having a congested placement with a timing critical placement map includes identifying critical circuit components in the placement map and determining failing circuit components in the placement map; determining “non-critical” circuit components safe to be moved; removing selected non critical from the placement map; and optimizing the critical... Agent: International Business Machines Corporation

20150040096 - Emulation-based functional qualification: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize... Agent: Synopsys, Inc.

  
01/29/2015 > 6 patent applications in 4 patent subcategories.

20150033196 - Clustering for processing of circuit design data: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of... Agent:

20150033197 - Clustering for processing of circuit design data: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of... Agent:

20150033198 - Integrated circuit device configuration methods adapted to account for retiming: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into... Agent:

20150033199 - Systems and methods for single cell product path delay analysis: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring... Agent:

20150033200 - Lsi designing apparatus, lsi designing method, and program: An apparatus and method that improve design efficiency when designing an LSI. A selector module generating section inputs IP connection information describing input/output flows of signals between IPs included in an LSI to be designed, analyzes the inputted IP connection information, and generates a selector module of a selector that... Agent: Mitsubishi Electric Corporation

20150033201 - Systems and methods for fabricating semiconductor device structures: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool... Agent: Globalfoundries, Inc.

  
01/22/2015 > 8 patent applications in 6 patent subcategories.

20150026650 - Integrated circuit manufacture using direct write lithography: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step... Agent:

20150026651 - Preventing double patterning odd cycles: A method, system or computer usable program product for preventing odd cycles caused by design modifications to a double patterning layout including utilizing a processor to identify a set of double patterning cycles in the layout for storage in a memory; receiving a set of design modifications to the layout;... Agent:

20150026652 - System, method, and computer program product for correlating transactions within a simulation of a hardware platform for post-simulation debugging: A system, method, and computer program product for correlating transaction within a simulation of a hardware platform for post-simulation debugging is disclosed. The method includes the steps of initializing state information associated with a hardware simulation for a register-transfer level model representing a digital circuit design, executing the hardware simulation... Agent:

20150026654 - Hierarchical verification of clock domain crossings: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level... Agent:

20150026653 - Relative timing characterization: Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point... Agent:

20150026655 - Determining a set of timing paths for creating a circuit abstraction: Systems and techniques for determining a set of timing paths for creating a circuit abstraction are described. During operation, an embodiment can receive a set of circuit elements in the circuit design that are candidates for optimization. Next, the embodiment can determine a set of timing paths by identifying critical... Agent:

20150026656 - Updating pin locations in a graphical user interface of an electronic design automation tool: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects... Agent:

20150026657 - 3d device modeling for finfet devices: Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin... Agent:

  
01/15/2015 > 5 patent applications in 5 patent subcategories.

20150020037 - Method and system for design of a reticle to be manufactured using variable shaped beam lithography: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle... Agent:

20150020038 - Method for efficient fpga packing: A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing... Agent:

20150020039 - Cascode cmos structure: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and... Agent:

20150020040 - Method for automatic design of an electronic circuit, corresponding system and computer program product: A method for the automatic design of an electronic circuit includes operations for evaluation of the thermal effects in the electronic circuit. The method generates a layout of the electronic circuit. Abstract data at the substrate level associated to the layout of the electronic circuit is then generated. A grid... Agent: Stmicroelectronics S.r.l.

20150020041 - Method and system for enhanced integrated circuit layout: An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a minor of the first cell. The method further includes dividing the first cell into a first plurality of... Agent:

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