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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
04/10/2014 > 9 patent applications in 8 patent subcategories.

20140101623 - Method of merging color sets of layout: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140101622 - Perturbational technique for co-optimizing design rules and illumination conditions for lithography process: A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules,... Agent:

20140101624 - Contour alignment system: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140101625 - Design rule optimization in lithographic imaging based on correlation of functions representing mask and predefined optical conditions: Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination shape, projection optics numerical aperture (NA) etc.) fixed. A cross-correlation function is created by multiplying the diffraction order functions of the mask patterns... Agent: Asml Netherlands B.v.

20140101626 - System and method of electromigration mitigation in stacked ic designs: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140101627 - Design assist apparatus, method for assisting design, and computer-readable recording medium having stored therein program for assisting design: Multiple signal lines in a circuit net the vertex of which is a maximum observation point having a maximum diagnosis difficulty index among a plurality of diagnosis difficulty indexes of all the observation points that are used for observing signal lines in the circuit, each of the plurality of diagnosis... Agent: Fujitsu Limited

20140101628 - Functional testing of a processor design: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test... Agent: International Business Machines Corporation

20140101629 - Early design cycle optimzation: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of... Agent: International Business Machines Corporation

20140101630 - Computer system for generating an integrated and unified view of ip-cores for hierarchical analysis of a system on chip (soc) design: In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted... Agent: Atrenta, Inc.

  
04/03/2014 > 11 patent applications in 10 patent subcategories.

20140096093 - Reliability determination taking into account effect of component failures on circuit operation: A method includes testing to failure a plurality of semiconductor test structures, measuring a parameter of each semiconductor test structure after experiencing a failure, and generating a cumulative probability distribution function (CPDF) of cumulative probability versus the measured parameter after failure for the plurality of semiconductor test structures. The method... Agent: Texas Instruments Incorporated

20140096094 - Breaking up long-channel field effect transistor into smaller segments for reliability modeling: A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second... Agent: Lsi Corporation

20140096095 - Data processing apparatus including reconfiguarable logic circuit: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of... Agent: Fuji Xerox Co., Ltd.

20140096096 - Analog circuit simulator and analog circuit verification method: An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information... Agent: Fujitsu Limited

20140096097 - Core wrapping in the presence of an embedded wrapped core: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may... Agent: Lsi Corporation

20140096098 - Using entire area of chip in tddb checking: A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.... Agent: Lsi Corporation

20140096099 - Generating an equivalent waveform model in static timing analysis: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple... Agent: Cadence Design Systems, Inc.

20140096100 - Method of sharing and re-using timing models in a chip across multiple voltage domains: A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes... Agent: International Business Machines Corporation

20140096101 - Semiconductor device and designing method of semiconductor device: A semiconductor device has: a first signal line formed in a first wiring layer formed on a semiconductor substrate, and disposed in a first direction; first and second shield lines formed in the first wiring layer, disposed on both sides of the first signal line in the first direction, and... Agent: Fujitsu Semiconductor Limited

20140096102 - System and method for across-chip thermal and power management in stacked ic designs: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140096103 - System for optimizing number of dies produced on a wafer: A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of... Agent:

  
03/27/2014 > 18 patent applications in 11 patent subcategories.

20140089868 - Automated repair method and system for double patterning conflicts: A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations... Agent: Synopsys, Inc.

20140089869 - Layout method of semiconductor circuit structure: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is... Agent: United Microelectronics Corporation

20140089870 - Inspection method and apparatus and lithographic processing cell: A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of... Agent: Asml Netherlands B.v.

20140089871 - Hierarchical wafer yield prediction method and hierarchical lifetime prediction method: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With... Agent: United Microelectronics Corp.

20140089872 - Method of proving formal test bench fault detection coverage: Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is covered by a property set. A mutatable RTL design is defined which allows for... Agent: Infineon Technologies Ag

20140089873 - Automatically identifying resettable flops for digital designs: An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all... Agent: Apple Inc.

20140089878 - Determining apparatus, determining method, and computer product: A determining apparatus includes a processor configured to detect from among a group of sectional areas obtained by dividing layout data indicating a design area concerning a circuit-under-design and stored in a storage device, adjacent sectional areas that are adjacent to sectional areas in a design change area and outside... Agent: Fujitsu Limited

20140089877 - Electrical hotspot detection, analysis and correction: Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances... Agent: Mentor Graphics Corporation

20140089874 - Method and apparatus for optimizing memory-built-in-self test: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing... Agent: Cadence Design Systems, Inc.

20140089875 - Method and apparatus for optimizing memory-built-in-self test: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing... Agent: Cadence Design Systems, Inc.

20140089876 - Thermal analysis of integrated circuit packages: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140089879 - Characterization based buffering and sizing for system performance optimization: A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in... Agent: Atrenta, Inc.

20140089881 - Circuit timing analysis incorporating the effects of temperature inversion: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding... Agent: Lsi Corporation

20140089880 - Method and system to fix early mode slacks in a circuit design: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix... Agent: International Business Machines Corporation

20140089882 - Computing device and method for modularizing power supplies placed on pcb: In a method for modularizing power supplies placed on a printed circuit board (PCB) using a computing device, a circuit design drawing of a power supply is obtained from a database. The method acquires circuit design data of the power supply from the circuit design drawing of the power supply,... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.

20140089883 - Area efficient power switch: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the... Agent: Apple Inc.

20140089884 - Design support method and apparatus: A disclosed design support method includes: dividing an circuit element that is included in a circuit to be designed and is provided on a path that connects between memory circuits into plural circuit elements, based on information concerning circuit elements that can be divided into circuit elements; tracing the path... Agent:

20140089885 - Electronic circuit design method: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly... Agent: Stmicroelectronics Sa

  
03/20/2014 > 9 patent applications in 9 patent subcategories.

20140082572 - Method of generating assistant feature: A method of generating an assistant feature is provided. A plurality of main features is provided. A first main feature is selected from the main features. A plurality of rule-based features is disposed around the first main feature. A model-based feature is generated around the first main feature. An overlap... Agent: Nanya Technology Corporation

20140082573 - Circuit design support apparatus, circuit design support method, and computer product: A circuit design support apparatus includes a processor configured to calculate a time period necessary for a transition of a logical state, based on circuit configuration information indicating connection relations of elements of an integrated circuit and input information indicating a logical value input into an input terminal of the... Agent: Fujitsu Limited

20140082574 - Token-based current control to mitigate current delivery limitations in integrated circuits: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at... Agent: International Business Machines Corporation

20140082575 - Method for placing decoupling capacitors: A method comprises selecting a region from a layout pattern of an integrated circuit, wherein the region comprises a plurality of functional units, and wherein the functional units are not coupled to each other through a variety of connection components, identifying hot spots in the region using a first threshold... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140082576 - Gradient aocv methodology enabling graph-based timing closure with aocv timing models: A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist.... Agent: Texas Instruments Incorporated

20140082577 - Uniform-footprint programmable-skew multi-stage delay cell: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a... Agent: Lsi Corporation

20140082578 - Rc extraction methodology for floating silicon substrate with tsv: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140082579 - Architectural physical synthesis: Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with... Agent: Synopsys, Inc.

20140082580 - Current-aware floorplanning to overcome current delivery limitations in integrated circuits: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at... Agent: International Business Machines Corporation

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