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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
06/11/2015 > patent applications in patent subcategories.
06/04/2015 > patent applications in patent subcategories.
05/28/2015 > 9 patent applications in 9 patent subcategories.

20150149969 - Layout design for electron-beam high volume manufacturing: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields.... Agent:

20150149970 - Simulation method, simulation program, process control system, simulator, process design method, and mask design method: A simulation method includes acquiring processing conditions for performing an etching process using plasma on a surface of a wafer covered by a mask having a predetermined mask thickness and aperture ratio, calculating, based on the conditions, a flux amount of a reaction product that enters the surface, calculating, based... Agent:

20150149971 - Optimizing lithography masks for vlsi chip design: In one embodiment, a computer-implemented method includes accessing mask input data. The mask input data includes a mathematical representation of a mask in a mask representation space, where the mask is configured to create an integrated circuit microprocessor. A set of values is obtained based on a derivative of the... Agent: International Business Machines Corporation

20150149972 - Method, design apparatus, and program product for incremental design space exploration: A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a cluster generation task (302) which generates clusters based on the parse tree, each of the clusters including a group of... Agent: Nec Corporation

20150149973 - Third party component debugging for integrated circuit design: The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and... Agent: Mentor Graphics Corporation

20150149974 - Diagnosis device, control method of diagnosis device, and recording medium: A diagnosis device including a storage unit configured to store first circuit configuration information, a circuit unit configured to configure a first plurality of circuits based on the first circuit configuration information and a second plurality of circuits based on second circuit configuration information, and a processor configured to update... Agent:

20150149975 - Method and apparatus for providing a design diagram of a semiconductor device: A method for providing a design diagram of a semiconductor device is provided. The method includes generating a circuit diagram representing connections among a supply voltage, a ground voltage and a plurality of components in the semiconductor device and displaying a plurality of layout restrictions on the circuit diagram by... Agent:

20150149976 - Layout of an integrated circuit: A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150149977 - Partitioning method and system for 3d ic: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected... Agent:

05/21/2015 > 23 patent applications in 15 patent subcategories.

20150143304 - Target point generation for optical proximity correction: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150143305 - Reticle data decomposition for focal plane determination in lithographic processes: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different... Agent: International Business Machines Corporation

20150143306 - Methods for fabricating high-density integrated circuit devices: An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall... Agent: Synopsys, Inc.

20150143307 - Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis... Agent: Atrenta, Inc.

20150143309 - Computer implemented system and method for generating a layout of a cell defining a circuit component: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules... Agent:

20150143310 - P-cell caching: In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced... Agent:

20150143308 - Simulation system and method for testing a simulation of a device against one or more violation rules: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one... Agent: Freescale Semiconductor, Inc.

20150143312 - Method of designing patterns of semiconductor devices: A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design... Agent:

20150143311 - Method, system and computer program product for designing semiconductor device: A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150143315 - Fault injection of finfet devices: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured... Agent:

20150143313 - Grouping layout features for directed self assembly: Aspects of the invention relate to techniques of grouping layout features for directed self-assembly (DSA). Via-type features in a layout design are separated into via-type feature groups and isolated via-type features. The derived via-type feature groups are analyzed to determine whether the via-type feature groups are DSA-compliant. The layout design... Agent: Mentor Graphics Corporation

20150143314 - Method of designing fin field effect transistor (finfet)-based circuit and system for implementing the same: A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150143316 - Apparatus and methods for partitioning an integrated circuit design into multiple programmable devices: Methods and systems for partitioning a design across a plurality of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) are provided. The systems include SerDes (SERializer DESerializer) interfaces, such as PCIe, (Peripheral Component Interconnect Express) in the programmable logic devices operably connecting logic blocks of the design. Embodiments... Agent:

20150143317 - Determination of electromigration features: For one or more geometric elements partitioned into a plurality of geometric element portions, the expected current directions through each geometric element portion are determined. Using the expected current directions, each expected current path through the geometric element portions is determined. Based upon the expected current paths, and the physical... Agent: Mentor Graphics Corporation

20150143318 - Determination of electromigration susceptibility based on hydrostatic stress analysis: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions... Agent: Mentor Graphics Corporation

20150143319 - Different scaling ratio in feol / mol/ beol: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that... Agent: Taiwan Semicondutor Manufacturing Co., Ltd.

20150143320 - Method for producing mrom memory based on otp memory: A method of producing a MROM memory based on an OTP memory is provided. The method includes: removing the floating gate of the second PMOS transistor of the OTP memory cell for storing data “0” in the OTP memory map, such that the OTP memory cell being transferred to a... Agent:

20150143321 - Methods for cell phasing and placement in dynamic array architecture and implementation of the same: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists... Agent:

20150143322 - Switch cell: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option... Agent:

20150143323 - Generating guiding patterns for directed self-assembly: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on... Agent: Mentor Graphics Corporation

20150143324 - Semiconductor device design methods and conductive bump pattern enhancement methods: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern... Agent:

20150143326 - Efficient ceff model for gate output slew computation in early synthesis: A slew-based effective capacitance (Ceff) is used to compute gate output slew during early synthesis of an integrated circuit design. A π model is constructed for the gate and reduced to two parameters which are used to compute a slew value for the model, given a slew definition. A capacitance... Agent: International Business Machines Corporation

20150143325 - Method, system, and computer program product for modeling resistance of a multi-layered conductive component: Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined... Agent: International Business Machines Corporation

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