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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
07/10/2014 > 9 patent applications in 8 patent subcategories.

20140195992 - Determining a position of inspection system output in design data space: Systems and methods for determining a position of output of an inspection system in design data space are provided. One method includes merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged.... Agent: Kla-tencor Corporation

20140195993 - Three-dimensional mask model for photolithography simulation: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved... Agent: Asml Netherlands B.v.

20140195994 - Defective artifact removal in photolithography masks corrected for optical proximity: Defective artifact removal is described in photolithography masks corrected for optical proximity. In one example a method is described in which partitions are identified in a mask design for independent optimization. The partitions are grouped and ordering into stages. The first stage is processed. Geometries are extracted from the periphery... Agent:

20140195995 - Systems and methods for single cell product path delay analysis: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring... Agent: International Business Machines Corporation

20140195996 - Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits: A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at... Agent: International Business Machines Corporation

20140195997 - Method and layout of an integrated circuit: An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140195998 - Automatic generation of wire tag lists for a metal stack: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers... Agent: International Business Machines Corporation

20140195999 - Method of designing semiconductor integrated circuit: A method of designing a semiconductor integrated circuit, includes inserting, between a power supply voltage and a ground voltage, at least two types of capacitor cells which have a different ratio, the ratio being between an inverse number of a capacitance value of a capacitative element and a resistance value... Agent: Fujitsu Limited

20140196000 - System and method for checking signal transmission line: A method for checking signal transmission lines of a printed circuit board (PCB) layout includes determining differential pairs to be checked and dividing the differential pairs to be checked into a first group and a second group. A first reference distance between differential pairs belonging to the same group and... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.

  
07/03/2014 > 25 patent applications in 17 patent subcategories.

20140189611 - Method of decomposable checking approach for mask alignment in multiple patterning: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140189612 - Test coverage of integrated circuits with masking pattern selection: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all... Agent: International Business Machines Corporation

20140189613 - Voltage-related analysis of layout design data: Disclosed are representative embodiments of methods, apparatus, and systems for voltage-related analysis of layout design data. According to embodiments of the disclosed technology, voltage association data objects are generated for drawn layers in a net of a layout design and voltage values or ranges of voltage values associated with the... Agent: Mentor Graphics Corporation

20140189614 - Method and system of mask data preparation for curvilinear mask patterns for a device: A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern,... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140189616 - Incremental concurrent processing for efficient computation of high-volume layout data: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O... Agent: Synopsys, Inc.

20140189615 - Signal path and method of manufacturing a multiple-patterned semiconductor device: A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks... Agent: International Business Machines Corporation

20140189617 - Displaying a congestion indicator for a channel in a circuit design layout: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects... Agent: Synopsys, Inc.

20140189619 - Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set: An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies.... Agent: Ftl Systems, Inc.

20140189618 - Wiring design support apparatus, method and computer-readable recording medium: A wiring design support apparatus includes: an input device with which input data about a wiring design content in a multilayered printed circuit board is input; a storage device includes a stab length limitation value table and a back drill application table stored therein, wherein the stab length limitation value... Agent: Fujitsu Limited

20140189621 - Apparatus and method for modeling controller of can bus simulator: An apparatus and a method for modeling a controller of a CAN bus are provided. The apparatus for modeling a controller of a CAN bus includes a modeling device for modeling a communication unit of a controller of the CAN bus and for evaluating the communication unit in a configuration... Agent: Hyundai Motor Company

20140189620 - Netlist abstraction: Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The... Agent: Synopsys, Inc.

20140189622 - Partitioning designs to facilitate certification: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a... Agent: Altera Corporation

20140189623 - Parasitic component library and method for efficient circuit design and simulation using the same: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140189624 - Abstract creation: Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths. According to one definition, a side load of a timing path is a circuit element that is not on the timing path... Agent: Synopsys, Inc.

20140189625 - Performance-driven and gradient-aware dummy insertion for gradient-sensitive array: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140189626 - Circuit width thinning defect prevention device and method of preventing circuit width thinning defect: The present invention relates to a circuit width thinning defect prevention device and a method of preventing a circuit width thinning defect, and can prevent a circuit width thinning defect, that is, a reduction in circuit width due to excessive etching on a specific portion by including a storage means... Agent: Samsung Electro-mechanics Co., Ltd.

20140189627 - Incremental clock tree synthesis: Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes... Agent: Synopsys, Inc.

20140189628 - System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk: A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to... Agent: Texas Instruments Incorporated

20140189629 - Pattern-based power-and-ground (pg) routing and via creation: Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based... Agent: Synopsys, Inc.

20140189631 - Computer-readable recording medium, circuit design apparatus and circuit design method: A computer-readable recording medium having stored therein a program for causing a computer to execute a circuit design process includes: calculating a maximum number of wirings arrangeable in an adjacent region of a part on a board based on a design rule; and drawing the wirings of the maximum number... Agent: Fujitsu Limited

20140189630 - Soft pin insertion during physical design: A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input... Agent: International Business Machines Corporation

20140189632 - Multiple-instantiated-module (mim) aware pin assignment: Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then... Agent: Synopsys, Inc.

20140189634 - Priori corner and mode reduction: Systems and techniques are described for performing a priori corner and mode reduction. Some embodiments create a synthetic corner in which (1) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple temperature corners, and/or (2) a cell delay for... Agent: Synopsys, Inc.

20140189633 - Semiconductor integrated circuit design supporting apparatus, method, and program: A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires... Agent: Mitsubishi Electric Corporation

20140189635 - Semiconductor device design method, system and computer-readable medium: A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (RC) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

  
06/26/2014 > 22 patent applications in 17 patent subcategories.

20140181761 - Identifying circuit elements for selective inclusion in speed-push processing in an integrated circuit, and related circuit systems, apparatus, and computer-readable media: Embodiments of the disclosure include identifying circuit elements for selective inclusion in speed-push processing and related circuit systems, apparatus, and computer-readable media. A method for altering a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied to identify... Agent: Qualcomm Incorporated

20140181762 - Lithography aware leakage analysis: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a... Agent: Synopsys, Inc.

20140181763 - Methods of forming a mask and methods of correcting intra-field variation across a mask design used in photolithographic processing: A method of forming a mask includes creating a difference map between a desired intra-field pattern that is to be formed on substrates and an intra-field signature pattern. The intra-field signature pattern represents a pattern formed on an example substrate by an exposure field using an example E-beam-written mask. Modifications... Agent: Micron Technology, Inc.

20140181764 - Identifying hierarchical chip design intellectual property through digests: One method implementation disclosed includes detecting matching leaf cells that have functionally identical designs (optionally, similar designs) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names... Agent: Oasis Tooling, Inc.

20140181765 - Look-up based buffer tree synthesis: Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis.... Agent: Synopsys, Inc.

20140181766 - Multi-mode scheduler for clock tree synthesis: Techniques and systems for performing clock tree synthesis (CTS) across multiple modes are described. Some embodiments traverse one or more clock trees from the root of each clock tree to a set of sinks of the clock tree. During the traversal, each clock gate can be marked with a traversal... Agent: Synopsys, Inc.

20140181767 - Method, apparatus, and system for efficient pre-silicon debug: Described are method, apparatus, and system for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit; recognizing method calls associated with the architectural verification environment; and generating a list of recognized method calls,... Agent:

20140181768 - Automated performance verification for integrated circuit design: A method and apparatus for automated performance verification for integrated circuit design is described herein. The method includes test preparation and automated verification stages. The test preparation stage generates design feature-specific performance tests to meet expected performance goals under certain workloads using optimization approaches and for different design configurations. The... Agent:

20140181769 - Netlist cell identification and classification to reduce power consumption: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured... Agent: Nvidia Corporation

20140181770 - Printed substrate design system, and printed substrate design method: A printed substrate design system designs a substrate configuration of a printed substrate on which an IC and a passive component are mounted, and a cable is connected to the printed substrate. The printed substrate design system includes: an input unit that receives input of printed substrate design information; an... Agent: Nec Corporation

20140181771 - Method and apparatus for enhanced static ir drop analysis: Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile... Agent: Qualcomm Incorporated

20140181772 - Determining high quality initial candidate sink locations for robust clock network design: A design tool with an initial sink locator unit determines a number of clock buffers for driving clock signals to loads in a clock distribution network. The design tool determines clusters of loads in the clock distribution network, wherein the number of clusters is equal to the number of clock... Agent: International Business Machines Corporation

20140181773 - Shaping integrated with power network synthesis (pns) for power grid (pg) alignment: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the... Agent: Synopsys, Inc.

20140181774 - Non-integer height standard cell library: A standard cell library for designing integrated circuits is provided. In some aspects, the standard cell library includes a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library. The standard cell library further... Agent: Broadcom Corporation

20140181775 - Unit capacitor module, automatic capacitor layout method thereof and automatic capacitor layout device thereof: A unit capacitor module for automatic capacitor-layout, includes a capacitor unit; at least one first connecting port, coupled to a first side of the capacitor unit; at least one second connecting port, coupled to a second side of the capacitor unit; at least one third connecting port, coupled to a... Agent: Ali Corporation

20140181776 - What-if partitioning and timing: Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a... Agent: Synopsys, Inc.

20140181777 - Automatic clock tree routing rule generation: Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next,... Agent: Synopsys, Inc.

20140181778 - Integrated circuit optimization: A device may identify signal channels for connecting circuit blocks, where each circuit block is associated with a block implementation area corresponding to a substrate. The device may assign a channel priority to each of the signal channels based on at least one channel criteria. The device may allocate a... Agent: Juniper Networks, Inc.

20140181779 - Timing bottleneck analysis across pipelines to guide optimization with useful skew: Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but... Agent: Synopsys, Inc.

20140181781 - Design system for semiconductor device, method for manufacturing semiconductor device, semiconductor device and method for bonding substrates: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in... Agent:

20140181780 - Electromigration analysis for standard cell based designs: Methods and media for analyzing electrical designs are provided. A method includes and the media are configured for providing or loading to an analysis tool a design that includes a plurality of cell instances of a standard cell and estimating a failure rate of the design using in context electrical... Agent: Advanced Micro Devices, Inc.

20140181782 - Wireless energy transfer modeling tool: A method includes defining and storing one or more attributes of a source resonator and a device resonator forming a system, defining and storing the interaction between the source resonator and the device resonator, modeling the electromagnetic performance of the system to derive one or more modeled values and utilizing... Agent: Witricity Corporation

  
06/19/2014 > 17 patent applications in 12 patent subcategories.

20140173533 - Locally optimized coloring for cleaning lithographic hotspots: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon... Agent: Globalfoundries Inc.

20140173534 - Resolution enhancing technology using phase assignment bridges: In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the predictable layout, a bridge structure is generated. Each bridge of the bridge structure connects one of... Agent: Mentor Graphics Corporation

20140173535 - Analysis of chip-mean variation and independent intra-die variation for chip yield determination: Systems and methods for determining a chip yield are disclosed. One method includes obtaining a first probability distribution function modeling variations within a chip and a second probability distribution function modeling variations between dies. Further, a discontinuous first level integration is performed with the first probability distribution function and a... Agent: International Business Machines Corporation

20140173536 - Computer-implemented methods and systems for automatic generation of layout versus schematic (lvs) rule files and regression test data suites: A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite.... Agent: Advanced Micro Devices, Inc.

20140173537 - Methodology for nanoscale technology based mixed-signal system design: A method for designing complex, mixed signal circuits, comprising generating electronic data defining a baseline schematic design. Generating a parameterized parasitic-aware netlist using the baseline schematic design. Performing design and process parameter statistical optimization using the parameterized parasitic-aware netlist and mixed signal component specifications. Determining whether one or more predetermined... Agent: University Of North Texas

20140173538 - Fec decoder dynamic power optimization: A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace,... Agent: Infinera Corporation

20140173540 - Circuit design support method, circuit design support apparatus, and computer product: A circuit design support method that is executed by a computer, includes calculating a first performance value of a circuit under design before a layout process, by inputting into a first function model that represents a performance value of the circuit under design before the layout process, the values of... Agent: Fujitsu Limited

20140173539 - Method and apparatus for isolating and/or debugging defects in integrated circuit designs: Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s).... Agent: Cadence Design Systems, Inc.

20140173541 - Method and apparatus for verifying debugging of integrated circuit designs: Method and apparatus for verifying debugging aspects of integrated circuit (IC) designs. In one aspect, an IP provider(s) can use the same process that isolated IP defect(s) to demonstrate to the customer (whether an IC designer or an IP consumer such as a smartphone manufacturer) that the debugging was successful,... Agent: Cadence Design Systems, Inc.

20140173542 - Method for automatic design of an electronic circuit, corresponding system, and computer program product: A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes... Agent: Stmicroelectronics S.r.l.

20140173543 - Parasitic extraction in an integrated circuit with multi-patterning requirements: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions... Agent: International Business Machines Corporation

20140173544 - Method for generating a topography of an fdsoi integrated circuit: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well... Agent:

20140173545 - Placing transistors in proximity to through-silicon vias: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV... Agent: Synopsys, Inc.

20140173547 - Analysis of chip-mean variation and independent intra-die variation for chip yield determination: Systems and methods for determining a chip yield are disclosed. One system includes a first level integration solver and a second level integration solver. The first level integration solver is configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level... Agent: International Business Machines Corporation

20140173549 - Computing device and method of checking wiring diagrams of pcb: In a method for checking a wiring diagram in a printed circuit board (PCB) design, a pair of differential signal lines in a PCB file is located according to a designation of a user. Components connected by the differential signal lines and vias which the differential signal lines pass through... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd

20140173546 - Method and system to view and analyze state model transition on host/semiconductor equipment for 300mm standards: The embodiments herein disclose a method and system to view and analyze state model transition on host/equipment for 300 mm standards. A state transition module is developed for effectively viewing and analyzing state model transition occurring on the host/equipment using 300 mm standards. The state transition module can be integrated... Agent:

20140173548 - Tool for automation of functional safety metric calculation and prototyping of functional safety systems: A tool for performing a functional safety analysis of an integrated circuit device tailored to a customer's specific application and implementation of the device. Information regarding a user's specific implementation of a given integrated circuit device is provided by the customer as input to the safety analysis tool. The tool... Agent: Texas Instruments Incorporated

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