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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
12/04/2014 > 10 patent applications in 7 patent subcategories.

20140359543 - Method and apparatus for cost function based simultaneous opc and sbar optimization: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that... Agent: Asml Netherlands B.v.

20140359542 - Method and system for dimensional uniformity using charged particle beam lithography: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to... Agent:

20140359544 - Layout re-decomposition for multiple patterning layouts: Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises... Agent: Taiwan Semiconductor Manufacturing Company Limited

20140359545 - Equivalence checking using structural analysis on data flow graphs: A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition... Agent: Synopsys, Inc

20140359547 - Hierarchical design of integrated circuits with multi-patterning requirements: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a... Agent:

20140359546 - Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit: Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement... Agent: International Business Machines Corporation

20140359548 - Orthogonal circuit element routing: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the... Agent:

20140359549 - Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information: A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation.... Agent:

20140359550 - Power delivery network analysis: A method and apparatus for power delivery network (PDN) analysis comprises obtaining time-domain single-pulse current response of the PDN, computing a maximum transient simultaneous switching noise (SSN) of the PDN according to the time-domain single-pulse current response, and determining that noise performance of the PDN conforms to a design requirement... Agent: International Business Machines Corporation

20140359551 - Systems and methods for semiconductor voltage drop analysis: Methods and systems are provided for computing IR drop, i.e., voltage drop, in a semiconductor device. The method includes generating a modeling element corresponding to the plurality of transistors. At least one of the transistors in the modeling element is replaced with a current source. The method also includes performing... Agent: Globalfoundries, Inc.

11/27/2014 > 16 patent applications in 13 patent subcategories.

20140351771 - Scatterometry overlay metrology targets and methods: Scatterometry overlay (SCOL) targets as well as design, production and measurement methods thereof are provided. The SCOL targets have several periodic structures at different measurement directions which share some of their structural target elements or parts thereof. An array of common elements may have symmetry directions which are parallel to... Agent:

20140351772 - Method and apparatus for model based flexible mrc: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the... Agent: Asml Netherlands B.v.

20140351773 - Model-based process simulation systems and methods: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more... Agent: Asml Netherlands B.v.

20140351774 - System and method for universal control of electronic devices: A system and method for providing an integrated circuit that integrates with and controls a device wherein the integrated circuit design is developed based on a selection of characteristics of the device. The system and method also provide software for establishing interoperability between the integrated circuit and a controller.... Agent:

20140351775 - System, method, and computer program product for providing a debugger using a common hardware database: A hardware model database is identified which stores a graph-based common representation of a hardware design that includes hardware module nodes each representative of a unique module of the hardware design and associated with one or more instances of the unique module. Additionally, a signal dump resulting from a simulation... Agent: Nvidia Corporation

20140351776 - Detecting device and method for pcb layout: A detecting device includes an input device, a display, and a computer system. The computer system includes a setting module, a storing module, a detecting module, and a control module. The storing module stores a PCB layout file. The setting module receives detecting parameters inputted by the input device. The... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.

20140351777 - Prototype and emulation system for multiple custom prototype boards: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is... Agent:

20140351778 - Lsi design apparatus and method of designing lsi: According to one embodiment, a LSI design apparatus includes a first logic synthesis portion executing a design of a LSI in a logic gate level, a extraction portion extracting paths from the LSI, a determination portion determining a character of each of the paths, a parameter setting portion setting an... Agent: Kabushiki Kaisha Toshiba

20140351779 - Integrated circuit (ic) design method with enhanced circuit extraction models: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip... Agent: Shanghai Ic R&d Center Co., Ltd.

20140351780 - System and method for configuring a channel: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second... Agent:

20140351781 - Method for placing operational cells in a semiconductor device: There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power... Agent: Freescale Semiconductor, Inc.

20140351782 - Program binding system, method and software for a resilient integrated circuit architecture: The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by... Agent: Element Cxi, LLC

20140351783 - Characterizing tsv structures in a semiconductor chip stack: A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device... Agent: International Business Machines Corporation

20140351784 - Layout modification method and system: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer... Agent:

20140351785 - Dielectric reliability assessment for advanced semiconductors: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro... Agent:

20140351786 - Information processing apparatus, information processing method, program, and board manufacturing system: An information processing apparatus is configured to compute the shape of a conductive pattern to be formed on a board by a drawing apparatus that performs drawing on the board using conductive liquid droplets. The information processing apparatus includes an image data generation unit configured to generate image data in... Agent: Kabushiki Kaisha Zuken

11/20/2014 > 4 patent applications in 4 patent subcategories.

20140344769 - Method for correcting electronic proximity effects using the deconvolution of the pattern to be exposed by means of a probabilistic method: A method of lithography by radiation having critical dimensions of the order of some ten nanometers makes it possible to carry out the correction of the proximity effects by joint optimization of the dose modulation and geometric corrections. Accordingly, a deconvolution of the pattern to be etched is carried out... Agent: Commissariat A L'energie Atomizue Et Aux Energies Alternatives

20140344770 - Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140344771 - Optical semiconductor device, socket, and optical semiconductor unit: An optical semiconductor unit of the present invention has an LED device provided with an LED (Light Emitting Diode) and a socket to which the LED device is mounted, the LED device has a main body to which the LED is mounted, the main body has a first surface to... Agent: Japan Aviation Electronics Industry, Limited

20140344772 - Semi-local ballistic mobility model: A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point.... Agent: Synopsys, Inc.

11/13/2014 > 5 patent applications in 5 patent subcategories.

20140337809 - Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure: A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first... Agent:

20140337810 - Modular platform for integrated circuit design analysis and verification: A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for... Agent: Mentor Graphics Corporation

20140337811 - Sub-module physical refinement flow: A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger... Agent: Synopsys, Inc.

20140337812 - Circuit verification method and circuit verification apparatus: A control section of a circuit verification apparatus acquires waveform data of output in a transient state of a verification target circuit by a circuit simulation and stores the waveform data in a storage section. When the control section detects input to a functional model of the verification target circuit... Agent:

20140337813 - Method and apparatus for extracting delay parameter: A delay parameter extracting apparatus includes a schematic composing unit, a layout composing unit, a verification unit, and a parameter extracting unit. The schematic composing unit is configured to: facilitate design of a schematic circuit; and generate a first net list based on the design of the schematic circuit. The... Agent: Samsung Display Co., Ltd.

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