|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor maskBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/06/2014 > 17 patent applications in 13 patent subcategories.
20140068527 - System and method for modifying a data set of a photomask: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed... Agent: Cadence Design Systems, Inc.
20140068528 - Balancing mask loading: Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy... Agent: Taiwan Semiconductor Manufacturing Company Limited
20140068530 - Fast freeform source and mask co-optimization method: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the... Agent: Asml Netherlands B.v.
20140068529 - Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis: A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern... Agent: International Business Machines Corporation
20140068531 - Pre-colored methodology of multiple patterning: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes.... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140068532 - Integrated circuit characterization based on measured and static apparent resistances: First and second apparent resistance measures are determined for an integrated circuit and utilized to characterize the integrated circuit. The first apparent resistance measure is determined for the integrated circuit based on a first voltage drop and a first current that are measured using test equipment. The second apparent resistance... Agent: Lsi Corporation
20140068533 - Information theoretic subgraph caching: Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process.... Agent: Synopsys, Inc.
20140068534 - Designing photonic switching systems utilizing equalized drivers: Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching system based on a weighted value corresponding to each of the plurality of performance metrics. A switch driver circuit is selected... Agent: International Business Machines Corporation
20140068535 - System and method for configuring a transistor device using rx tuck: The present disclosure relates to methods and systems for designing and fabricating an integrated circuit. In particular, a method includes electronically searching a virtual layout of an integrated circuit to locate a dummy polysilicon structure positioned between adjacent terminals of first and second MOSFET devices that are connected to different... Agent: Advanced Micro Devices, Inc.
20140068536 - Non-transitory computer readable medium storing timing analysis program, timing analysis device, and timing analysis method: A timing analysis device includes a storage unit and a processing unit. The processing unit performs storage processing and analysis processing. The storage processing stores circuit information of a circuit to be analyzed, timing constraint information defining timing constraints on the circuit, delay information defining a plurality of delay values... Agent: Renesas Electronics Corporation
20140068537 - Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140068538 - Automated noise characterization and completeness and correctness of noise deliverables: Methods, systems and processor-readable media for automatic self-tracking of input deliverables for noise characterization. A noise characterization run to generate a noise model thereof can be automatically initiated. The noise model can be delivered into a repository in response to completing the noise characterization run and generating the noise model.... Agent: Lsi Corporation
20140068539 - Electronic apparatus, method of optimizing de-coupling capacitor and computer-readable recording medium: An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to... Agent: Samsung Electronics Co., Ltd
20140068540 - Integrated circuit design flow with layout-dependent effects: A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140068541 - Interconnect structures and methods for back end of the line integration: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to... Agent: International Business Machines Corporation
20140068542 - Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required,... Agent: Springsoft, Inc.
20140068543 - Method to enhance double patterning routing efficiency: A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part,... Agent: Globalfoundries Inc.02/27/2014 > 10 patent applications in 8 patent subcategories.
20140059502 - Pattern data generation method, pattern verification method, and optical image calculation method: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape... Agent: Kabushiki Kaisha Toshiba
20140059504 - Method and system for replacing a pattern in a layout: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140059503 - Method for preparing a pattern to be printed on a plate or mask by electron beam lithography, corresponding printed circuit design system and computer program: A method for preparing a pattern to be printed on a plate or mask by electron beam lithography comprising the following steps: modelling of the pattern by breaking down this pattern into a set of elementary geometric shapes intended to be printed individually in order to reproduce said pattern and,... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt
20140059505 - Method for designing integrated circuits employing correct-by-construction progressive modeling and an apparatus employing the method: Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to... Agent: Lsi Corporation
20140059507 - Defect injection for transistor-level fault simulation: Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic... Agent: Mentor Graphics Corporation
20140059506 - Method and apparatus for applying post graphic data system stream enhancements: An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one... Agent: Globalfoundries Inc.
20140059508 - Determining a design attribute by estimation and by calibration of estimated value: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at... Agent: Synopsys, Inc.
20140059509 - Methodology on developing metal fill as library device: A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model... Agent: International Business Machines Corporation
20140059510 - Sizing method for stand-alone photovoltaic system: m
20140059511 - Generating root cause candidates for yield analysis: Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties... Agent: Mentor Graphics Corporation02/20/2014 > 8 patent applications in 7 patent subcategories.
20140053118 - Compression method and system for use with multi-patterning: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140053117 - Techniques for phase tuning for process optimization: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein... Agent:
20140053119 - Extraction and sharing in high level synthesis: Technology for translating a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the behavior, or other functionality, of multiple circuit portions, with at least some of the multiple circuit portions having multiple components. The... Agent: C2 Design Automation Dba Forte Design Systems
20140053120 - Architectural physical synthesis: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design... Agent: Synopsys, Inc.
20140053121 - Accelerator for a read-channel design and simulation tool: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as... Agent: Lsi Corporation
20140053122 - Method for adjusting a layout of an integrated circuit: A method for adjusting a layout of an integrated circuit includes a first layer, a second layer, a target metal line, and a first non-target metal line. The integrated circuit is configured for a focused ion beam (FIB) detection to the target metal line. The method includes the steps of:... Agent: National Chiao Tung University
20140053123 - Density-based integrated circuit design adjustment: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are... Agent: Mentor Graphics Corporation
20140053124 - Thermal analysis based circuit design: Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the method implemented on a data processing system for circuit design, the method comprises determining... Agent: Synopsys, Inc.02/13/2014 > 10 patent applications in 9 patent subcategories.
20140047396 - P and n region differentiation for image-to-cad alignment: In one embodiment, a method for aligning an image of a semiconductor device with a bitmap representation thereof includes receiving diffusion layer information of at least a portion of the semiconductor device, receiving implant layer information of the at least a portion of the semiconductor device, deriving distinct p- and... Agent: Dcg Systems, Inc.
20140047397 - Lens heating compensation systems and methods: Methods for calibrating a photolithographic system are disclosed. A cold lens contour for a reticle design and at least one hot lens contour for the reticle design are generated from which a process window is defined. Aberrations induced by a lens manipulator are characterized in a manipulator model and the... Agent: Asml Netherlands B.v.
20140047398 - Masks for double patterning photolithography: Improved masks for double patterning lithography are described. In one example, conflict spaces between features of a target design are identified. The conflict spaces are represented as nodes of a graph. Connections are inserted between nodes based on a local search. The connections are cut to determine double patterning mask... Agent:
20140047399 - System and method for inferring higher level descriptions from rtl topology based on naming similarities and dependency: A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances... Agent: Atrenta, Inc.
20140047400 - Logic circuit design method, logic circuit design program, and logic circuit design system: According to one embodiment, a logic circuit design method of an embodiment includes generating logical data corresponding to register transfer level description, based on design data containing the register transfer level description, and generating constraint conditions designating circuit data which satisfies a predetermined condition among plural gate level circuit data... Agent: Kabushiki Kaisha Toshiba
20140047401 - Reconfigurable logic block: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM)... Agent: Altera Corporation
20140047402 - Lsi design method and lsi design device: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of... Agent:
20140047403 - Statistical corner evaluation for complex on-chip variation model: SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being... Agent: Synopsys, Inc.
20140047404 - Timing-aware test generation and fault simulation: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from... Agent: Mentor Graphics Corporation
20140047405 - Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.... Agent: Altera CorporationPrevious industry: Data processing: presentation processing of document
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