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Data processing: design and analysis of circuit or semiconductor mask

20120124528 - Method and device for increasing fin device density for unaligned fins: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120124529 - Pattern-independent and hybrid matching/tuning including light manipulation by projection optics: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing illumination source and projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the... Agent: Asml Netherlands B.v.

20120124531 - I/o cell architecture: A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120124530 - Making a discrete spatial correlation continuous: A mechanism is provided for making a discrete spatial correlation on a 2D grid continuous. The region has given grid points and each of the grid points has its discrete stochastic variable. Additional grid points and associated stochastic variables are established on the boundary and corners of the region. All... Agent: International Business Machines Corporation

20120124532 - Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device: A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a... Agent: International Business Machines Corporation

20120124533 - Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors: A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a... Agent: International Business Machines Corporation

20120124534 - System and method for performing static timing analysis in the presence of correlations between asserted arrival times: A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one... Agent: International Business Machines Corporation

20120124535 - Optimal chip acceptance criterion and its applications: At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at... Agent: International Business Machines Corporation

20120124536 - Method and system for automatic generation of solutions for circuit design rule violations: Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments... Agent:

20120124538 - Method and device for selectively adding timing margin in an integrated circuit: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed”... Agent: International Business Machines Corporation

20120124537 - Slack-based timing budget apportionment: A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential performance optimization opportunities in the logic used to implement such circuits. Logic in various units of an integrated circuit design that is amenable to... Agent: International Business Machines Corporation

20120124539 - Clock optimization with local clock buffer control optimization: A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing... Agent: International Business Machines Corporation

20120124540 - Design assisting apparatus, method, and program: A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and... Agent: Fujitsu Limited

20120124541 - Implementing spare latch placement quality determination: A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of... Agent: International Business Machines Corporation

20120124543 - Flip-flop library development for high frequency designs built in an asic flow: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the... Agent:

20120124542 - Method and system for optimizing a device with current source models: A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch... Agent: International Business Machines Corporation

20120124544 - Method for setting test point: A method for setting a test point is applied to dispose at least one test point on a circuit board in a trace file, which includes steps of reading the trace file, in which the trace file includes at least one trace; determining whether the trace has an initial test... Agent: Inventec Corporation

20120117518 - Designing synthetic biological circuits using optimality and nonequilibrium thermodynamics: In general, the invention relates to a method for designing a biological circuit. The method includes obtaining a target circuit objective for the biological circuit, determining an objective function corresponding to the target circuit objective, obtaining a number of nodes for the biological circuit, obtaining a set of possible circuit... Agent: William Marsh Rice University

20120117519 - Method of transistor matching: A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to forming a photomask. A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting... Agent: Texas Instruments Incorporated

20120117520 - Systems and methods for inspecting and controlling integrated circuit fabrication using a calibrated lithography simulator: A system and method for precise control of fine-line photolithography is disclosed. The system includes a wafer inspector that detects and measures edges and contours of patterns as produced on a wafer and a lithography simulator. The method calibrates the lithography simulator using multiple measurements and/or edges of patterns on... Agent: Ngr, Inc.

20120117522 - Optimization of source, mask and projection optics: Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source... Agent: Asml Netherlands B.v.

20120117521 - Pattern-dependent proximity matching/tuning including light manipulation by projection optics: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be... Agent: Asml Netherlands B.v.

20120117523 - Inverse lithography for high transmission attenuated phase shift mask design and creation: Various implementations of the invention provide for generation of a high transmission phase shift mask layout through inverse lithography techniques. In various implementations of the present invention, a set of mask data having a plurality of pixels is generated. The transmission value associated with each pixel may then be determined... Agent: Imec

20120117524 - Reusable structured hardware description language design component: A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware... Agent: International Business Machines Corporation

20120117525 - Translating a user design in a configurable ic for debugging the user design: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method... Agent:

20120117526 - Computer readable non-transitory medium storing design aiding program, design aiding apparatus, and design aiding method: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within... Agent: Fujitsu Limited

20120117527 - Performing statistical timing analysis with non-separable statistical and deterministic variations: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews... Agent: International Business Machines Corporation

20120117528 - Systems and methods for circuit lifetime evaluation: Systems and methods for estimating the lifetime of an electrical system in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes iteratively performing Worst Case Analysis (WCA) on a system design with respect to different system lifetimes using a computer to determine the lifetime at... Agent: California Institute Of Technology

20120117529 - Apparatus, design method and recording medium: A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the... Agent: Fujitsu Limited

20120117530 - Circuit visualization using flightlines: A system is disclosed for displaying circuitry interconnections as flightlines between a component specified as the local component and the foreign components connecting to the local component. Upon obtaining data of the circuit components and interconnections, a user can designate the local component from among all of the circuit components.... Agent: Chipworks, Incorporated

20120110521 - Split-layer design for double patterning lithography: A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first... Agent: International Business Machines Corporation

20120110522 - Pattern recognition with edge correction for design based metrology: Exemplary embodiments include a method for edge correction in pattern recognition, the method including receiving a design layout, receiving a sample plan based on the design layout, receiving user-generated edge input and generating a recipe output from the design layout, the sample plan and the user-generated edge input. The incorporation... Agent: International Business Machines Corporation

20120110523 - Pattern recognition with edge correction for design based metrology: A method for edge correction in pattern recognition includes generating a pattern recognition output for a pattern recognition process, including receiving, in the processor, a design layout, receiving a sample plan based on the design layout, receiving a first user-generated edge input, generating a pattern recognition recipe output from the... Agent: International Business Machines Corporation

20120110524 - Methods, photomasks and methods of fabricating photomasks for improving damascene wire uniformity without reducing performance: A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes dispersed between damascene wires of the multiplicity... Agent: International Business Machines Corporation

20120110525 - Hybrid electronic design system and reconfigurable connection matrix thereof: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are... Agent: Global Unichip Corporation

20120110526 - Method and apparatus for tracking uncertain signals: A method and an apparatus for tracking uncertain signals in the simulation of chip design are provided. The method comprises: generating a directed graph which contains sequential logic devices and IO devices from the netlist of chip design, wherein the directed graph illustrates the signal association among the sequential logic... Agent: International Business Machines Corporation

20120110527 - Connection verification method, recording medium thereof, and connection verification apparatus: A connection verification method is disclosed. A computer verifies a connection between a first node and a second node by starting from the first node in a designed integrated circuit, based on connection information stored in a storage part. The computer detects whether a module connected to the second node... Agent: Fujitsu Limited

20120110528 - Method of predicting electronic circuit floating gates: Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level... Agent:

20120110529 - Clock domain crossing buffer: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a... Agent:

20120110530 - Computer system and method of preparing a layout: The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120110531 - Defect and yield prediction for segments of an integrated circuit: Defect prediction information is determined for a segment of an integrated circuit layout. Marker information is obtained, for example from user input into a computer design tool, where the marker information defines the segment. A segment can be defined to be any arbitrary portion of the layout and can include... Agent: Qualcomm Incorporated

20120110533 - Implementing enhanced clock tree distributions to decouple across n-level hierarchical entities: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree... Agent: International Business Machines Corporation

20120110532 - Latch clustering with proximity to local clock buffers: A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of... Agent: International Business Machines Corporation

20120110534 - Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow: A method of filling dcaps in an integrated circuit includes identifying a set of dcap-eligible areas of the integrated circuit for areas large enough to accommodate at least one dcap cell having a selected size smaller than a default size. The dcap cell includes at least one built-in power track.... Agent:

20120110535 - Integrated circuit manufacturing method and semiconductor integrated circuit: In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO... Agent:

20120110538 - Clock-tree structure and method for synthesizing the same: A method for synthesizing a clock-tree structure may be applied to a physical design such as an integrated circuit or a printed circuit board to form a symmetrical clock-tree structure, while achieving the effects including minimizing a clock skew, having a process variation tolerance and increasing the synthesizing rate. To... Agent: National Taiwan University

20120110537 - Methods and systems for flexible and repeatable pre-route generation: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated... Agent: Oracle International Corporation

20120110536 - Statistical method for hierarchically routing layout utilizing flat route information: An integrated circuit design is routed by first creating temporary routes in a flattened layout, generating blockage information for sub-blocks in the layout based on the temporary routes, and establishing a routing order for cells using a depth-first search. Cells in the original layout are then routed according to the... Agent: International Business Machines Corporation

20120110539 - Automatically routing nets with variable spacing: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on... Agent: Pulsic Limited

20120110540 - Method of optimizing parameters of electronic components on printed circuit boards: In a method of optimizing parameters of electronic components on printed circuit boards (PCBs), a first experiment table for m variables of one type of parameter of P electronic components on a PCB is designed using n values of each variable and the RSM. P EHs of each first experiment... Agent: Hon Hai Precision Industry Co., Ltd.

20120110541 - Constraint optimization of sub-net level routing in asic design: Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections... Agent: International Business Machines Corporation

20120110542 - Method to scale down ic layout: A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the... Agent:

20120102440 - Method and system for implementing controlled breaks between features using sub-resolution assist features: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or... Agent: Cadence Design Systems, Inc.

20120102441 - Marker layer to facilitate mask build with interactive layers: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to... Agent: Texas Instruments Incorporated

20120102442 - System and method for model based multi-patterning optimization: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize... Agent:

20120102443 - N/p configurable ldmos subcircuit macro model: A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual... Agent: Texas Instruments Incorporated

20120102444 - On-chip tunable transmission lines, methods of manufacture and design structures: An on-chip tunable transmission line (t-line), methods of manufacture and design structures are provided. The structure includes a tunable transmission line (t-line) with fixed characteristic impedance comprising functionally-differentiated switches used for inductance and capacitance, respectively.... Agent: International Business Machines Corporation

20120102445 - Implementing enhanced rlm connectivity on a hierarchical design with top level pipeline registers: A method, system, and computer program product are provided for implementing enhanced random logic macro (RLM) connectivity on a hierarchical design on an integrated circuit chip with top-level pipeline registers. Random logic macros (RLMs) to be connected are identified. Pipeline registers are identified; an input net is connected to an... Agent: International Business Machines Corporation

20120102446 - Implementing net routing with enhanced correlation of pre-buffered and post-buffered routes: A method, system and computer program product are provided for implementing enhanced net routing with improved correlation of pre-buffered and post-buffered routes on a hierarchical design of an integrated circuit chip. In initial wiring steps the nets are routed, and then buffers are add along the net route based upon... Agent: International Business Machines Corporation

20120102447 - System and method for optimizing logic timing: In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of... Agent: Global Unichip Corp.

20120102448 - Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs: A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not... Agent: Avago Technologies EnterpriseIP(singapore) Pte. Ltd.

20120102449 - Method and apparatus for thermal analysis: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of... Agent: