Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents
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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
10/02/2014 > 9 patent applications in 7 patent subcategories.

20140298277 - Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) synthesizing a netlist from the functional IC design that meets the target clock rate, (4)... Agent:

20140298278 - Graphical method and product to assign physical attributes to entities in a high level descriptive language used for vlsi chip design: A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis. A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout... Agent: International Business Machines Corporation

20140298279 - Circuit design support method, computer product, and circuit design support apparatus: A circuit design support method includes obtaining shared circuit information indicating various types of shared circuits each executing at least any one of various types of logical computations and causing plural signal lines to share an observation point at which a signal value is observable; determining for each of the... Agent: Fujitsu Semiconductor Limited

20140298281 - Method of global design closure at top level and driving of downstream implementation flow: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed... Agent: Atrenta, Inc.

20140298280 - Reducing runtime and memory requirements of static timing analysis: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier... Agent: International Business Machines Corporation

20140298283 - Clock tree construction across clock domains: Disclosed is a method and system for clock tree construction across clock domains, an integrated circuit and fabrication method thereof. A method for clock tree construction includes acquiring a netlist describing an integrated circuit (IC), comprising data for describing physical locations and logic connections of clock sinks belonging to multiple... Agent: International Business Machines Corporation

20140298282 - Design structure for stacked cmos circuits: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a pluraility of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a... Agent: International Business Machines Corporation

20140298284 - Standard cell design layout: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell.... Agent:

20140298285 - Design assistance device, design assistance method, and design assistance program: A determination unit determines whether there is error allowance information having the same error identification ID and the same error object as error information, and determines whether error related information is also the same when there is the same error allowance information. As a result, when there is error allowance... Agent: Fujitsu Limited

  
09/25/2014 > 13 patent applications in 9 patent subcategories.

20140289684 - Balancing mask loading: Among other things, techniques for balancing mask loading are provided for herein. In some embodiments, one or more windows are defined within a layout. Based upon polygons comprised within respective windows, a localized mask loading is computed for the layout. In some embodiments, a global mask loading is also computed... Agent:

20140289685 - Dynamic power driven clock tree synthesis (cts): Dynamic power driven clock tree synthesis is described. Some embodiments can select one or more cells from a cell library based on power ratios of cells in the cell library. The embodiments can then construct a clock tree based on the one or more cells.... Agent: Synopsys, Inc.

20140289686 - Single event upset mitigation for electronic design synthesis: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run... Agent: Mentor Graphics Corporation

20140289687 - Information processing apparatus and design verification method: A computation unit locates data of a first component in a first circuit, as well as data of a second component in the second circuit. The computation unit then obtains data of a first portion of the first circuit by tracing wiring lines from component to component in the first... Agent: Fujitsu Limited

20140289688 - Method and system for testing direct current transmission layout of printed circuit board: An system for testing direct current (DC) layout of a printed circuit board, the system includes a layout information obtaining module, a rule loading module, a test script building module, a script executing module, and a report generating module. The layout information obtaining module obtains layout information of the printed... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd

20140289690 - On-chip-variation (ocv) and timing-criticality aware clock tree synthesis (cts): On-chip-variation (OCV) and timing-criticality aware clock tree synthesis (CTS) is described. Some embodiments can construct a first set of clock tree topologies for timing sequential circuit elements in a set of critical paths, wherein said constructing can comprise optimizing the first set of clock tree topologies to reduce an impact... Agent: Synopsys, Inc.

20140289689 - Wiring inspection apparatus and wiring inspection method: A wiring inspection apparatus includes a first calculating unit, a second calculating unit, and an output unit. The first calculating unit calculates the number of components arranged along two sides, one of which extends in a first direction and the other one of which extends in a second direction, of... Agent: Fujitsu Limited

20140289691 - Circuit design support apparatus, circuit design support method, and computer product: A circuit design support apparatus includes a processor that is configured to generate area information that indicates a plurality of areas obtained by dividing a predetermined area in a circuit by a constant interval; generate first layout data that indicates arrangement of buffer cells capable of supplying clock signals to... Agent: Fujitsu Limited

20140289692 - Element removal design in microwave filters: A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter... Agent:

20140289694 - Dual-structure clock tree synthesis (cts): Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on... Agent: Synopsys, Inc.

20140289693 - System and method for improved net routing: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a shape with a perimeter; offsetting at least a part of a segment of the perimeter of the shape from the perimeter to generate an offset segment; forming a route segment in response to the offset... Agent:

20140289695 - Evaluation of pin geometry accessibility in a layer of circuit: Evaluation of electrical accessibility within a layer of a circuit to pin geometries residing within a cell boundary of the circuit is provided. The evaluating includes, for instance, checking along substantially parallel pin geometry access paths of the layer to determine possible points at which a respective pin geometry of... Agent: Globalfoundries Inc.

20140289696 - Wiring inspection apparatus and wiring inspection method: A wiring inspection apparatus includes a dividing unit, a calculating unit, and an output unit. The dividing unit draws a boundary line in a predetermined area between a transmission component and a reception component, to divide the predetermined area into a first area containing the transmission component and a second... Agent: Fujitsu Limited

  
09/18/2014 > 65 patent applications in 23 patent subcategories.

20140282289 - Cell boundaries for self aligned multiple patterning abutments: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140282288 - Design-for-manufacturing - design-enabled-manufacturing (dfm-dem) proactive integrated manufacturing flow: System and methods for design-for-manufacturing and design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow are presented. A method includes receiving design data related to layout of an integrated circuit (IC); extracting information from the design data; and performing analysis on the extracted information. The method also enables DFM-DEM aware manufacturing applications using... Agent:

20140282286 - Etch failure prediction based on wafer resist top loss: An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features... Agent: Globalfoundries Singapore Pte. Ltd.

20140282287 - Reusable cut mask for multiple layers: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140282290 - Sub-resolution assist feature implementation using shot optimization: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run... Agent: Synopsys, Inc.

20140282293 - Eda tool and method for conflict detection during multi-patterning lithography: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282294 - Method, system and software for accessing design rules and library of design features while designing semiconductor device layout: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140282291 - Source-mask optimization for a lithography process: Systems and methods for optimizing a source shape and a mask shape for a lithography process are disclosed. One such method includes performing a mask optimization for the lithography process in accordance with a set of parameters including at least one variable representation, at least one objective and problem constraints.... Agent: International Business Machines Corporation

20140282292 - Surface topography enhanced pattern (step) matching: A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the... Agent: Globalfoundries Singapore Pte. Ltd.

20140282296 - Hybrid method for performing full field optical proximity correction for finfet mandrel layer: A hybrid OPC process and a resulting reticle are disclosed. Embodiments include generating a finfet fin reticle including a first portion having regular pitches and a second portion having irregular pitches, performing rule based OPC on at least the first portion, and performing OPC repair locally at the second portion.... Agent: Globalfoundries Inc.

20140282299 - Method and apparatus for performing optical proximity and photomask correction: An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a... Agent: Globalfoundries Singapore Pte. Ltd.

20140282295 - Method for forming photo-masks and opc method: The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the... Agent: United Microelectronics Corp.

20140282297 - Method for generating post-opc layout in consideration of top loss of etch mask layer: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of... Agent: Samsung Electronics Co., Ltd.

20140282298 - Performing image calculation based on spatial coherence: Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity.... Agent: Synopsys, Inc.

20140282300 - Topography driven opc and lithography flow: Enhancements in lithography for forming an integrated circuit are disclosed. The enhancements include a topography analysis of a design data file to obtain accumulative topography information for different mask levels. The topography information facilitates topography driven optical proximity correction and topography driven lithography.... Agent: Globalfoundries Singapore Pte. Ltd.

20140282302 - Multi-etch process using material-specific behavioral parameters in 3-d virtual fabrication environment: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide... Agent:

20140282303 - Pattern-independent and hybrid matching/tuning including light manipulation by projection optics: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing illumination source and projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the... Agent:

20140282301 - Stitch insertion for reducing color density differences in double patterning technology (dpt): Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of... Agent: Globalfoundries Inc.

20140282305 - Common template for electronic article: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from... Agent: Taiwan Semiconductor Manufacturing Company Limited

20140282306 - Layout optimization for integrated design: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target... Agent:

20140282304 - Method and system for forming a diagonal pattern using charged particle beam lithography: A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed... Agent: D2s, Inc.

20140282307 - Method and apparatus for providing metric relating two or more process parameters to yield: A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture... Agent: Globalfoundries Inc.

20140282310 - Method of performing circuit simulation and generating circuit layout: A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, the portion including a first device. A third netlist is generated based on the first netlist... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282308 - Method of radio-frequency and microwave device generation: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be... Agent:

20140282309 - System, method, and computer program product for constructing a data flow and identifying a construct: A system, method, and computer program product are provided for creating a hardware design. In use, one or more parameters are received, where at least one of the parameters corresponds to an interface protocol. Additionally, a data flow is constructed based on the one or more parameters. Further, an indication... Agent: Nvidia Corporation

20140282311 - Network synthesis design of microwave acoustic wave filters: A method of designing an acoustic microwave filter in accordance with frequency response requirements. The method comprises selecting an initial filter circuit structure including a plurality of circuit elements comprising at least one resonant element and at least one other reactive circuit element, selecting lossless circuit response variables based on... Agent:

20140282315 - Graphical view and debug for coverage-point negative hint: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are... Agent: Synopsys, Inc.

20140282312 - Hardware simulation controller, system and method for functional verification: Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is... Agent:

20140282314 - Intelligent metamodel integrated verilog-ams for fast and accurate analog block design exploration: A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations at a plurality of sample points for the circuit component to generate a plurality of design variable samples for the circuit component. Storing... Agent: University Of North Texas

20140282313 - System, method, and computer program product for applying a callback function to data values: A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified. Additionally, the callback function is recursively applied to the plurality of data values in order to determine a result. Further,... Agent: Nvidia Corporation

20140282316 - Solving multiplication constraints by factorization: A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and... Agent: Synopsys, Inc.

20140282320 - Analyzing timing requirements of a hierarchical integrated circuit design: Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed.... Agent: International Business Machines Corporation

20140282317 - Arrival edge usage in timing analysis: A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing impacts. To reduce pessimism of crosstalk analysis for a victim net, arrival edges are tracked for the victim net.... Agent: Synopsys, Inc.

20140282319 - Semiconductor circuit design method, memory compiler and computer program product: A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282321 - System and method for a hybrid clock domain crossing verification: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded... Agent: Atrenta, Inc.

20140282322 - System and method for filtration of error reports respective of static and quasi-static signals within an integrated circuit design: A system and method identify potentially static and/or quasi-static signals within an integrated circuit (IC), or portion thereof. Static and quasi-static signals may be identified in a design description of the IC by any one or more of: (1) a fan-out size exceeding some threshold, (2) a toggle frequency in... Agent: Atrenta, Inc.

20140282318 - Timing delay characterization method, memory compiler and computer program product: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282323 - Parameterized cell for planar and finfet technology design: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin... Agent: Globalfoundries Inc.

20140282326 - Methods for layout verification for polysilicon cell edge structures in finfet standard cells: Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282325 - Methods for layout verification for polysilicon cell edge structures in finfet standard cells using filters: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282324 - Predictive 3-d virtual fabrication system and method: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements... Agent: Coventor, Inc.

20140282329 - Automated design rule checking (drc) test case generation: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon.... Agent: International Business Machines Corporation

20140282327 - Cutter in diagnosis (cid) a method to improve the throughput of the yield ramp up process: A method for producing candidate fault circuitry in an integrated circuit (IC) is disclosed. The method comprises tracing back from at least one failing output of the IC to determine a corresponding fan-in cone for each failing output using simulation values obtained from a fault free simulation of a design... Agent: Nvidia Corporation

20140282328 - Design rule checks in 3-d virtual fabrication environment: A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact... Agent:

20140282333 - Design support apparatus and design support method: A design support apparatus includes a detecting unit and a removing unit. The detecting unit detects a resistor whose terminals are open except one terminal and which has a resistance less than or equal to a threshold, from among resistors included in a circuit model representing a circuit. The removing... Agent: Fujitsu Limited

20140282332 - Fault injection of finfet devices: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282334 - Method and apparatus for extracting systematic defects: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282330 - Priority based layout versus schematic (lvs): An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the... Agent: Globalfoundries Inc.

20140282331 - Universal design layout compliance: Among other things, one or more techniques and systems for generating a common design rule check (DRC) rule set for verification of a design layout and for generating a common dummy insertion utility for design layout processing are provided. That is, the common DRC rule set comprises a set of... Agent: Taiwan Semiconductor Manufacturing Company Limited

20140282335 - Phase determination for extraction from scattering parameters: Scattering (S) parameters can be evaluated for a plurality of conductors on a semiconductor device to determine phase based on traversal around a Smith chart type representation. A propagation function for the plurality of conductors can be derived from S parameters, which in turn, can be used to derive resistance,... Agent: Synopsys, Inc.

20140282336 - Tool for evaluating clock tree timing and clocked component selection: Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated... Agent: Medtronic, Inc.

20140282337 - Semiconductor device design method, system and computer program product: A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140282338 - System and method for altering circuit design hierarchy to optimize routing and power distribution: Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup,... Agent: Atrenta, Inc.

20140282339 - Automatic tap driver generation in a hybrid clock distribution system: A hybrid clock distribution system uses a distribution fabric to distribute clock signals across longer physical distances and local sub-distribution networks to distribute clock signals more locally and to implement logic functions such as clock gating. A set of tap drivers connect the distribution fabric to the sub-distribution networks. A... Agent: Synopsys, Inc.

20140282341 - Flexible pattern-oriented 3d profile for advanced process nodes: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then... Agent:

20140282340 - Method for provisioning decoupling capacitance in an integrated circuit: A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement... Agent: Freescale Semiconductor, Inc.

20140282343 - Prioritized soft constraint solving: A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied... Agent: Synopsys, Inc.

20140282342 - Systems and methods for tuning technology files: A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector... Agent:

20140282344 - Layout boundary method: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to... Agent:

20140282346 - Mesh planes with alternating spaces for multi-layered ceramic packages: An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes.... Agent: International Business Machines Corporation

20140282345 - Via insertion in integrated circuit (ic) designs: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending... Agent: Globalfoundries Inc.

20140282347 - System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only... Agent: Atrenta, Inc.

20140282350 - Automatic clock tree synthesis exceptions generation: Systems and techniques are described for automatically generating clock tree synthesis (CTS) exceptions. The process can use on one or more criteria to identify sequential circuit elements that can be ignored during clock skew minimization. For example, the process can identify sequential circuit elements whose clock skew cannot be balanced... Agent: Synopsys, Inc.

20140282349 - Method and apparatus for current limit test for high power switching regulator: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses... Agent: Analog Devices Technology

20140282348 - Transistor design for use in advanced nanometer flash memory devices: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.... Agent:

  
09/11/2014 > 38 patent applications in 11 patent subcategories.

20140258946 - Mask set for double exposure process and method of using the mask set: A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of... Agent: United Microelectronics Corp.

20140258948 - Design synthesis of clock gated circuit: Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from... Agent: Cadence Design Systems, Inc.

20140258947 - Finite-state machine encoding during design synthesis: Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible... Agent: Cadence Design Systems, Inc.

20140258949 - Method of designing arrangement of tsv in stacked semiconductor device and designing system for arrangement of tsv in stacked semiconductor device: A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked... Agent: Samsung Electronics Co., Ltd.

20140258952 - Cell having shifted boundary and boundary-shift scheme: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140258950 - Deriving effective corners for complex correlations: Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent. Some implementations account for covariance, and use joint probability as the criteria for the effective... Agent: Oracle International Corporation

20140258953 - High performance design rule checking technique: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner... Agent: Synopsys, Inc.

20140258951 - Prioritized design for manufacturing virtualization with design rule checking filtering: An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit... Agent:

20140258956 - Apparatus and methods for power management in integrated circuits: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.... Agent: Altera Corporation

20140258955 - Metal interconnect modeling: A method for modeling metal routing includes extracting physical parameters of a metal interconnect for a circuit design, determining a resistance value from a database of metal interconnects with the extracted physical parameters, the resistance value being at a maximum frequency of a frequency range to be simulated, modeling the... Agent:

20140258954 - Ranking verification results for root cause analysis: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation... Agent: Synopsys, Inc.

20140258957 - Engineering change order hold time fixing method: An ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report... Agent:

20140258958 - Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications.... Agent: International Business Machines Corporation

20140258959 - Support technique: A present design support method includes: arranging capacitance cells in an entire area of a cell arrangement area of a semiconductor integrated circuit , before arranging logic cells; upon detecting that a position at which a certain logic cell will be arranged is designated, calculating a total sum of capacitance... Agent: Fujitsu Limited

20140258960 - Integrating optimal planar and three-dimensional semiconductor design layouts: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.... Agent: Globalfoundries Inc.

20140258962 - Parasitic capacitance extraction for finfets: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140258961 - Stretch dummy cell insertion in finfet process: A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140258963 - Placement and routing on a circuit: Methods and apparatuses to place and route cells on integrated circuit chips along paths is described. In one embodiment, the method to layout an integrated circuit, the method comprises routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit, and... Agent: Synopsys, Inc.

20140258964 - Automatic synthesis of complex clock systems: A global optimization method to synthesize and balance the clock systems in a multimode, multi-corner, and multi-domain design environment is described. The method builds a graph representation for a clock network. The method determines an optimal clock network balancing solution for the clock network by applying linear programming to the... Agent: Synopsys, Inc.

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