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Data processing: design and analysis of circuit or semiconductor mask

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
08/28/2014 > 16 patent applications in 15 patent subcategories.

20140245237 - Hybrid evolutionary algorithm for triple-patterning: According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using... Agent: Synopsys, Inc.

20140245239 - Detection and removal of self-aligned double patterning artifacts: Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based... Agent: Synopsys, Inc.

20140245238 - Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a... Agent: Globalfoundries Inc.

20140245240 - Free form fracturing method for electronic or optical lithography: The invention discloses a computer implemented method of fracturing a surface into elementary features wherein the desired pattern has a rectilinear or curvilinear form. Depending upon the desired pattern, a first fracturing will be performed of a non-overlapping or an overlapping type. If the desired pattern is resolution critical, it... Agent: Aselta Nanographics

20140245241 - Generation method, storage medium and information processing apparatus: The present invention provides a generation method of generating data of patterns of a plurality of masks used in an exposure apparatus for exposing a substrate, including a step of specifying, from a plurality of points on a grid having pattern elements to be formed on the substrate as intersections,... Agent: Canon Kabushiki Kaisha

20140245242 - Variation factor assignment: One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor... Agent: Taiwan Semiconductor Manufacturing Company Limited

20140245243 - Computing device and method for generating component module files of circuit diagram: A circuit diagram includes a plurality of components. Each component corresponds to a module number and a component number. The components corresponding to a same module number are classified into a same function module. Each function module corresponds to a component module file. The component module file of each function... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.

20140245244 - Setting switch size and transition pattern in a resonant clock distribution system: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode... Agent: International Business Machines Corporation

20140245245 - Standard cells having transistors annotated for gate-length biasing: Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined... Agent: Tela Innovations, Inc.

20140245246 - Configuring a programmable logic device using a configuration bit stream without phantom bits: Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration... Agent: Altera Corporation

20140245247 - Integrated circuit designed and manufactured using diagonal minimum-width patterns: An integrated circuit comprising a plurality of standard cell circuit elements is disclosed, wherein for at least one layer of the integrated circuit, a majority of minimum-width patterns are in a preferred diagonal orientation.... Agent: D2s, Inc.

20140245248 - Cell and macro placement on fin grid: A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140245249 - Systems and methods for solving computational problems: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing... Agent: D-wave Systems Inc.

20140245250 - Setting switch size and transition pattern in a resonant clock distribution system: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode... Agent: International Business Machines Corporation

20140245251 - Design optimization for circuit migration: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140245252 - Method and circuit to implement a static low power retention state: An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating IC device. The apparatus also includes a... Agent: Qualcomm Incorporated

08/21/2014 > 8 patent applications in 7 patent subcategories.

20140237434 - Photolithography mask design simplification: A photolithography mask design in simplified. In one example, a target mask design is optimized for a photolithography mask. Medial axes of the design and assist features on the optimized mask are identified. These are simplified to lines. Lines that are distant from a respective design feature are pruned. The... Agent:

20140237435 - Layout method and system for multi-patterning integrated circuits: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140237436 - Layout decomposition for triple patterning lithography: Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph... Agent: Mentor Graphics Corporation

20140237437 - Look-up based fast logic synthesis: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is... Agent: Synopsys, Inc.

20140237438 - Integrated circuit pad modeling: A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and... Agent: International Business Machines Corporation

20140237439 - Method, system and computer program for hardware design debugging: A plurality of diagnosis methods are provided for enabling hardware debugging, A first diagnosis method enables hardware debugging by means of time abstraction. A second-diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A... Agent:

20140237440 - Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a... Agent: Cadence Design Systems, Inc.

20140237441 - Method and apparatus for placing and routing partial reconfiguration modules: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned.... Agent: Altera Corporation

08/14/2014 > 8 patent applications in 8 patent subcategories.

20140229902 - Eda tool and method, and integrated circuit formed by the method: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140229903 - Optical proximity correction for topographically non-uniform substrates: Aspects of the invention relate to techniques of optical simulation for topographically non-uniform substrates. A layout design is simulated to generate an aerial image based on optical models for different types of substrates and for transition regions, along with models for one or more categories of light signals. The one... Agent: Mentor Graphics Corporation

20140229904 - Method and system for forming patterns with charged particle beam lithography: In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur... Agent: D2s, Inc.

20140229905 - System and method of circuit layout for multiple cells: A circuit layout method comprises inputting layout data into a circuit layout system. The layout data represents a plurality of patterns in a plurality of cells. Each pattern of the plurality of patterns has a plurality of runs, ends, and corners. The method also comprises specifying a plurality of G1-rule... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140229906 - Signal selection apparatus and system, and circuit emulator and method and program: Disclosed is a system in which in order to obtain the operation parameter of a circuit based on an implementable area indicating a circuit scale that can be implemented on a circuit implementation device, circuit area information, and operation parameter measuring circuit area information, an observation signal number determining means... Agent: Nec Corporation

20140229907 - Automated scalable verification for hardware designs at the register transfer level: A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in... Agent: The Regents Of The University Of Michigan

20140229908 - Power routing in standard cells: An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another... Agent: Synopsys, Inc.

20140229909 - Selective voltage binning within a three-dimensional integrated chip stack: Systems and methods for selective voltage binning within a three-dimensional integrated chip stack. A method is provided that includes defining a correlation between at least two parameters. At least one parameter of the at least two parameters is from a first chip of a three-dimensional integrated chip stack and at... Agent: International Business Machines Corporation

08/07/2014 > 17 patent applications in 13 patent subcategories.

20140223391 - Recognition of template patterns with mask information: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140223390 - Retargeting semiconductor device shapes for multiple patterning processes: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in... Agent: Globalfoundries Inc.

20140223389 - System and method to design and test a yield sensitive circuit: A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between... Agent: Qualcomm Incorporated

20140223393 - Method and system for forming high accuracy patterns using charged particle beam lithography: A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the... Agent: D2s, Inc.

20140223392 - Optimized optical proximity correction handling for lithographic fills: An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar... Agent: Globalfoundries Inc.

20140223395 - Boosting transistor performance with non-rectangular channels: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate... Agent: Synopsys, Inc.

20140223394 - Methods for manufacturing integrated circuit devices having features with reduced edge curvature: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line... Agent: Synopsys, Inc.

20140223396 - Pattern-based replacement for layout regularization: Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout. The regularized layout is then subjected to additional mask data preparation processing, such... Agent:

20140223397 - Automatic generation of wire tag lists for a metal stack: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers... Agent: International Business Machines Corporation

20140223398 - Method for determining interface timing of integrated circuit automatically and related machine readable medium thereof: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path... Agent: Realtek Semiconductor Corp.

20140223399 - Circuit analysis device and circuit analysis method: A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a... Agent: Fujitsu Limited

20140223400 - Numerical delay model for a technology library cell type: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a... Agent: Synopsys, Inc.

20140223401 - High-frequency vlsi interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy... Agent: Mentor Graphics Corporation

20140223402 - Multi-board design apparatus, multi-board design method, program and computer-readable recording medium: In order to always maintain connection relationships between substrates of the multi-board, a multi-board design apparatus for designing a multi-board comprising a plurality of substrates which are electrically connected is made to have: setting means by which a designer sets connection information indicating a connection relationship between each substrate configuring... Agent: Zuken Inc.

20140223403 - Method and apparatus for performing parallel routing using a multi-threaded routing procedure: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of... Agent: Altera Corporation

20140223404 - Gate-length biasing for digital circuit optimization: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.... Agent: Tela Innovations, Inc.

20140223405 - Method and apparatus for providing a layout defining a structure to be patterned onto a substrate: A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.... Agent: Infineon Technologies Ag

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