Data processing: design and analysis of circuit or semiconductor mask inventions

20090276735 - System and method of correcting errors in sem-measurements: Embodiments of the invention relate to correcting errors in scanning electron measurements during measuring structural dimensions of an integrated circuit for optical proximity correction by extracting feature edges of a test pattern within an image, calculating at least one scaling error of the image by comparing the extracted feature edges... Agent: Slater & Matsil, L.L.P.

20090276736 - Test pattern based process model calibration: Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes; creating a lumped-process-model incorporating said set of sub-processes; calculating a first set of output patterns from a set of test patterns by using... Agent: International Business Machines Corporation Dept. 18g

20090276737 - Tool for charge trapping memory using simulated programming operations: A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090276742 - Automating power domains in electronic design automation: One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a design element (or to a portion thereof) can indicate, for example, whether the element can be switched... Agent: Klarquist Sparkman, LLP

20090276739 - Ic chip and design structure including stitched circuitry region boundary identification: Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout... Agent: Hoffman Warnick LLC

20090276738 - Method and apparatus for executing a hardware simulation and verification solution: One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090276741 - Verification support apparatus, verification support method, and computer product: In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates... Agent: Greer, Burns & Crain

20090276740 - Verification supporting apparatus, verification supporting method, and computer product: In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data... Agent: Greer, Burns & Crain

20090276746 - Circuit analysis method, semiconductor integrated circuit manufacturing method, circuit analysis program and circuit analyzer: To perform a timing analysis at a high analysis accuracy while reducing a TAT. A circuit analyzer according to the present invention performs a timing analysis on a design target circuit after a layout change. The circuit analyzer includes a storage device in which an extraction range reference is set,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090276745 - Dummy metal insertion processing method and apparatus: A method includes: before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by layout data while changing an origin position of the dummy pattern template to optimize the... Agent: Greer, Burns & Crain

20090276744 - Operation timing verifying apparatus and program: An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition that all delay elements present a maximum delay as an operating condition, performs... Agent: Studebaker & Brackett PC

20090276743 - System and method for computing proxy slack during statistic analysis of digital integrated circuits: A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090276747 - Segmenting integrated circuit layout design files using speculative parsing: A method of parsing integrated circuit layout design data. According to some implementations, the segment boundaries are designated by first identifying data in the integrated circuit layout design data that matches a cell record start value. Next, the subsequent data is parsed, until a threshold amount of subsequent data has... Agent: Mentor Graphics Corp. Patent Group

20090276748 - Stitched circuitry region boundary indentification for stitched ic chip layout: Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout... Agent: Hoffman Warnick LLC

20090276749 - Gate modeling for semiconductor fabrication process effects: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation... Agent: Trellis Intellectual Property Law Group, PC

20090276750 - Method for establishing scattering bar rule: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on... Agent: Jianq Chyun Intellectual Property Office

20090276751 - Method of performing mask-writer tuning and optimization: A model-based tuning method for tuning a first mask writer unit utilizing a reference mask writer unit, each of which has tunable parameters for controlling mask writing performance. The method includes the steps of defining a test pattern and a mask writing model; generating the test pattern utilizing the reference... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090271747 - Logic circuit designing device, logic circuit designing method and logic circuit designing program for asynchronous logic circuit: A logic circuit designing device for designing an asynchronous logic circuit which satisfies characteristic constraints of a state holding element represented by a latch or a flip-flop is provided. A signal transition series which generates a control signal pulse of the state holding element is extracted by the state storage... Agent: Nec Corporation Of America

20090271746 - Method of circuit power tuning through post-process flattening: A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of the at least one reused cell are... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090271748 - Method and apparatus for simulating behavioral constructs using indeterminate values: One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090271749 - Pattern-clip-based hotspot database system for layout verification: One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090271751 - Method and apparatus for statistical path selection for at-speed testing: In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip... Agent: Wall & Tong, LLP IBM Corporation

20090271750 - Timing constraint merging in hierarchical soc designs: A method for propagating timing constraints from lower level design blocks to higher level design blocks includes o the steps of designing a circuit containing a plurality of design blocks. Each of the plurality of design blocks has a set of timing constraints associated therewith. A composite set of timing... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090271752 - Legalization of vlsi circuit placement with blockages using hierarchical row slicing: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and... Agent: Ibm Corporation (jvm)

20090271753 - Methods for cell phasing and placement in dynamic array architecture and implementation of the same: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists... Agent: Martine Penilla & Gencarella, LLP

20090271754 - Method and apparatus for computing a detailed routability estimation: One embodiment of the present invention provides a system that computes a routability estimation across a collection of local routing regions associated with a circuit layout. This system first selects a first local routing region associated with a route overflow, wherein a respective local routing region is associated with an... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090271755 - Unified layer stack architecture: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090271756 - Minimal leakage-power standard cell library: A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090271759 - Contrast-based resolution enhancement for photolithographic processing: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.... Agent: Klarquist Sparkman, LLP

20090271757 - Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation: A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers... Agent: Hoffman Warnick LLC

20090271758 - Methods for forming arrays of small, closely spaced features: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed... Agent: Knobbe Martens Olson & Bear LLP

20090265673 - Intersect area based ground rule for semiconductor design: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical... Agent: Scully, Scott, Murphy & Presser, P.C.

20090265672 - Method and system for entry and verification of parasitic design constraints for analog integrated circuits: A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on... Agent: Texas Instruments Incorporated

20090265674 - Methods for identifying failing timing requirements in a digital design: Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090265675 - On chip local mosfet sizing: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090265676 - Method for designing semiconductor integrated circuit: A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090265677 - Integrated test waveform generator (twg) and customer waveform generator (cwg), design structure and method: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090265678 - System and method of resistance based memory circuit parameter adjustment: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting... Agent: Qualcomm Incorporated

20090265679 - System and method of predicting problematic areas for lithography in a circuit design: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking... Agent: Greenblum & Bernstein, P.L.C

20090265680 - Method and system for correcting a mask pattern design: A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP