|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor mask March listing by industry category 03/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/29/2012 > 11 patent applications in 7 patent subcategories. listing by industry category
20120079436 - Fast photoresist model: A method of modeling an image intended to reside in a photoresist film on a substrate is provided. A simulated latent acid image of the image is produced, the simulated latent acid image is compressed in a predetermined direction, and developed to a pattern that enables (a) transfer of the... Agent: Nikon Corporation
20120079437 - Circuit design systems for replacing flip-flops with pulsed latches: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed... Agent:
20120079438 - Integrated circuit design framework comprising automatic analysis functionality: An embodiment of an integrated circuit design framework comprises a user interface which automatically initializes a three-dimensional simulation tool for simulating or analyzing the characteristics of a complex metallization system. In some illustrative embodiments the user interface may additionally provide electrically simulated parameter values for an input parameter, such as... Agent: Stmicroelectronics S.r.l.
20120079440 - Suspect logical region synthesis and simulation using device design and test information: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of... Agent: Teseda Corporation
20120079439 - Suspect logical region synthesis from device design and test information: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information... Agent: Teseda Corporation
20120079441 - Nonlinear approach to scaling circuit behaviors for electronic design automation: Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based... Agent: Synopsys, Inc.
20120079442 - Correlation of device manufacturing defect data with device electrical test data: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected;... Agent: Teseda Corporation
20120079443 - Printed circuit board design assisting device, method, and program: A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in... Agent: Fujitsu Limited
20120079445 - Circuit board designing device and non-transitory computer-readable medium: A circuit board designing device has a database that stores an another-component arrangement forbidden range table, a related component information table, and a relative-arranging position table, and a processing unit that executes arrangement of the components, determines the another-component arrangement forbidden range which is set to forbid arrangement of another... Agent: Fujitsu Limited
20120079444 - Computer aided design system and method: A computer aided design system comprises a dividing module, a storage, an interface creating module, a selecting module, and a display module. The dividing module divides the names into groups according to a predetermined rule. The group comprises a plurality of the targets set on the different layers. The storage... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.
20120079446 - Semiconductor module design method and semiconductor module: A semiconductor module made from a compound semiconductor or diamond and loaded with high performance power semiconductor devices can be obtained at low cost. In a semiconductor module, four (semiconductor chips) of same specifications are arranged in array, two longitudinally and two transversally, on a single lead frame. Achieving a... Agent:03/22/2012 > 8 patent applications in 5 patent subcategories. listing by industry category
20120072875 - Composition based double-patterning mask planning: Layout design data is analyzed to identify both potential geometric element cuts in the design and instances of an application of a separation directive. Each of the identified separation directive instances and the identified cuts are assigned an analysis value, such as a weight value. The separation directive instances and... Agent:
20120072874 - Dissection splitting with optical proximity correction and mask rule check enforcement: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120072876 - Method and apparatus for reducing x-pessimism in gate-level simulation and verification: Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during... Agent: Synopsys, Inc.
20120072878 - Automated management of verification waivers: Automated management of verification waivers is disclosed. In one embodiment a method is provided comprising issuing a request to perform a verification run on a component of an electric circuit design, receiving configuration data specifying a list of waivers extracted from a plurality of waivers applicable to the electric circuit... Agent: International Business Machines Corporation
20120072877 - Layout verification apparatus and layout verification method: According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be... Agent:
20120072879 - Method and apparatus for synthesis of multimode x-tolerant compressor: Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.... Agent: Synopsys, Inc.
20120072880 - Sensitivity-based complex statistical modeling for random on-chip variation: SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being... Agent:
20120072881 - Design apparatus, method for having computer design semiconductor integrated circuit, and non-transitory computer-readable medium: According to one embodiment, a design apparatus includes an extractor, a regression equation generator and an output module. The extractor extracts a critical part from a net list of a semiconductor integrated circuit. The critical part has a delay value greater than a delay threshold. The regression equation generator generates... Agent: Kabushiki Kaisha Toshiba03/15/2012 > 10 patent applications in 8 patent subcategories. listing by industry category
20120066651 - Technique for repairing a reflective photo-mask: During a calculation technique, a modification to a reflective photo-mask is calculated. In particular, using information associated with different types of analysis techniques a group of one or more potential defects in the reflective photo-mask is determined. Then, the modification to the reflective photo-mask is calculated based on at least... Agent:
20120066653 - Dose-data generating apparatus, dose-data generating method, and manufacturing method of semiconductor device: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a... Agent:
20120066652 - Technique for analyzing a reflective photo-mask: During a calculation technique, contributions to reflected light from multiple discrete cells in a model of a multilayer stack in a reflective photo-mask may be determined based on angles of incidence of light in a light pattern to the multilayer stack, a polarization of the light in the light pattern,... Agent:
20120066655 - Electronic device and method for inspecting electrical rules of circuit boards: An electronic device and method for inspecting electrical rules of circuit boards includes selecting at least two design files that record electrical rules of the circuit boards and searching the electrical rules in the selected design files using preset parameter keywords. Same electrical rules of the selected design files are... Agent: Hon Hai Precision Industry Co., Ltd.
20120066654 - Stability-dependent spare cell insertion: Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the... Agent: International Business Machines Corporation
20120066656 - Parallel parasitic processing in static timing analysis: A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the... Agent: Synopsys, Inc.
20120066657 - Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established... Agent: International Business Machines Corporation
20120066658 - System and method for integrated circuit power and timing optimization: A system for selecting gates for an integrated circuit design may include at least one processing device configured to identify gates of the integrated circuit design having a slack value less than a predefined slack threshold. The at least one processing device may be further configured to, for each of... Agent: Oracle International Corporation
20120066659 - Methods for generating device layouts by combining an automated device layout generator with a script: Methods for generating a device layout are provided. First, design rules corresponding to a specific technology are received. A selection of at least one element and a parameter value corresponding to at least one parameter on the selected element are received. A draft device layout corresponding to the selected element... Agent: Springsoft Inc.
20120066660 - Method of managing process factors that influence electrical properties of printed circuit boards: In a method of managing process factors that influence electrical properties of printed circuit boards (PCBs), n process factors are arranged in an order according to different influence to one kind of electrical property of the PCBs. The different influence is determined by first experiments designed using the Taguchi method.... Agent: Hon Hai Precision Industry Co., Ltd.03/08/2012 > 10 patent applications in 8 patent subcategories. listing by industry category
20120060131 - Method and apparatus for merging multiple geometrical pixel images and generating a single modulator pixel image: The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask... Agent: Micronic Mydata Systems Ab
20120060132 - Non-linear rasterized contour filters: A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values... Agent: Synopsys, Inc.
20120060133 - Annotation of rtl to simplify timing analysis: A method for simulating operation of a design model for a digital system is provided. A library of functional cells is maintained in a storage unit that includes an attribute template with one or more of the functional cells in the library. The attribute template provides fields for specifying design... Agent:
20120060135 - Integrated circuit transformer devices for on-chip millimeter-wave applications: Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.... Agent: International Business Machines Corporation
20120060134 - Wiring design support apparatus and wiring design support method: According to one embodiment, a wiring design support apparatus comprises a display, a drawing module, and a data creation module. The display is configured to display a three-dimensional object. The drawing module is configured to draw a line connecting two points on a surface of the three-dimensional object displayed by... Agent:
20120060136 - Design supporting method, design supporting device, computer product, and semiconductor integrated circuit: A method executed by a computer and for designing a semiconductor integrated circuit, includes detecting, from layout data of a semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers; selecting sequentially data holding elements connected to the detected... Agent: Fujitsu Semiconductor Limited
20120060137 - Method for designing wiring topology for electromigration avoidance and fabrication method of integrate circuits including said method: A method for designing wiring topology for electromigration avoidance, which is composed of multiple sources, multiple sinks and multiple wires, is disclosed. The steps of said method to get an optimal topology includes: 1. calculating the length of all the wires to choose one of the wires with the shortest... Agent: National Chiao Tung University
20120060138 - Method and system for adaptive physical design: A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power... Agent:
20120060139 - Using port obscurity factors to improve routing: An integrated circuit characterized by a netlist may be routed using a routing priority list that may be created using port obscurity factors. A port obscurity factor may indicate how difficult it may be to route to that port and may be calculated as being inversely proportional to the number... Agent: International Business Machines Corporation
20120060140 - Methods and apparatus for single testing stimulus: Methods and apparatus useful for improving the performance of testing and diagnostic operations on user circuit designs potentially across multiple phases of the development lifecycle and across multiple implementation technologies are described. As one example, a single testing and diagnostic stimulus source can variously provide test pattern data to different... Agent: Altera Corporation03/01/2012 > 19 patent applications in 14 patent subcategories. listing by industry category
20120054693 - Incremental concurrent processing for efficient computation of high-volume layout data: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O... Agent: Synopsys, Inc.
20120054694 - Aerial image signatures: Aerial image signatures may be constructed with some combinations of aerial image parameters such as the maximum intensity, the minimum intensity, the image contour curvature, and the intensity profile slope. Aerial image signatures may be applied to lithographic processes for identifying/processing non-litho friendly areas in a design layout.... Agent:
20120054695 - Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method: A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a... Agent: Kabubhsiki Kaisha Toshiba
20120054697 - Light source shape calculation method: According to one embodiment, a light source shape calculation method includes calculating a first light source shape as an exposure illumination light source shape, so that the first light source shape has a light source shape region symmetrical to an X-axis direction and a Y-axis direction, and a process margin... Agent:
20120054696 - Mask-shift-aware rc extraction for double patterning design: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120054699 - Converged large block and structured synthesis for high performance microprocessor designs: Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the... Agent: International Business Machines Corporation
20120054698 - Logic modification synthesis: A computer-executed method is disclosed which recognizes two circuits, an original and a modified circuit, with the original circuit having a first logic and the modified circuit having a second logic. The second logic is obtained by converting a modified specification into a preliminary gate-level form. The second logic contains... Agent: International Business Machines Corporation
20120054700 - Netlist generating apparatus and method: A netlist generating apparatus including a memory configured to store logic design data and a processor configured to execute an operation. The operation including selecting paths with which names of instances after logic synthesis match names of modules before being uniquified during the logic synthesis by referring to violation data... Agent: Fujitsu Limited
20120054701 - Optimal correlated array abstraction: Mechanisms are provided for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design. The mechanisms receive an abstracted netlist corresponding to an original netlist of the integrated circuit design. The mechanisms determine elements already present in the abstracted netlist and refine the abstracted netlist... Agent: International Business Machines Corporation
20120054702 - Techniques for employing retiming and transient simplification on netlists that include memory arrays: A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction... Agent: International Business Machines Corporation
20120054703 - Virtual flat traversal of a hierarchical circuit design: Configuration templates reflect configuration information described in hierarchical circuit design data. The object configure information will include both template generic configuration information and instance specific configuration information. The template generic configuration information is configuration information that is common to all instantiations of a corresponding cell in the hierarchical circuit design... Agent:
20120054704 - Voltage-mode driver with equalization: A voltage-mode differential driver may include a first nominal path that selectively couples a first supply or a second supply to a first output terminal in response to an input data. The voltage-mode differential driver may further include a first capacitive boost path that selectively couples the first supply or... Agent: Mosys, Inc.
20120054705 - Manufacturing method, manufacturing program and manufacturing system for semiconductor device: A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining... Agent: Sony Corporation
20120054706 - Timing analysis method, program and system: A timing analysis method includes: calculating a delay-voltage function that indicates a relationship between a delay variation rate and voltage variation; calculating a voltage-distance function that indicates a relationship between the voltage variation due to IR drop and a distance; and calculating, by combining the delay-voltage function and the voltage-distance... Agent: Renesas Electronics Corporation
20120054707 - Cone-aware spare cell placement using hypergraph connectivity analysis: Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the... Agent: International Business Machines Corporation
20120054709 - Constructing mapping between model parameters and electrical parameters: A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120054708 - Electronic design automation object placement with partially region-constrained objects: A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives... Agent: International Business Machines Corporation
20120054710 - Optical network design apparatus and method: An optical network design apparatus includes a memory and a processor. The memory stores a connection limit corresponding to the number of connections between ports. The processor provisionally designs a traffic path across an optical network independently of a connection limit of an asymmetric optical hub, calculates a penalty allowance... Agent: Fujitsu Limited
20120054711 - Circuit analysis using transverse buckets: A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running... Agent: International Business Machines CorporationPrevious industry: Data processing: presentation processing of document
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