|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor mask February patent applications/inventions, industry category 02/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/23/2012 > 11 patent applications in 9 patent subcategories.
20120047471 - Dynamic provisional decomposition of lithographic patterns having different interaction ranges: A method for obtaining mask and source patterns for printing integrated circuit patterns includes providing initial representations of a plurality of mask and source patterns. The method identifies long-range and short-range factors in the representations of the plurality of mask and source patterns, and provides a plurality of clips including... Agent: International Business Machines Corporation
20120047472 - Dummy-metal-layout evaluating device and dummy-metal-layout evaluating method: A dummy-mesh-information creating unit separates a group of dummy metal blocks that are arranged in a pattern regularly staggered with respect to a direction of a wire object into meshes so that each mesh has the same layout of dummy metal blocks. An overlap determining unit determines whether a dummy... Agent: Fujitsu Limited
20120047473 - Layout decomposition based on partial intensity distribution: Layout design data are decomposed for double dipole lithography based on partial intensity distribution information. The partial intensity distribution information is generated by performing optical simulations on the layout design data. The layout decomposition may further be adjusted during an optical proximity correction process. The adjustment may utilize the partial... Agent: Mentor Graphics Corporation
20120047474 - Method for manufacturing semiconductor devices: A method of manufacturing semiconductor devices is disclosed. The method includes determining fractured shots that do not overlap each other based on a final pattern; determining overlapping shots that are shots that overlap each other based on the final pattern; generating area difference data by comparing the areas of the... Agent: Samsung Electronics Co., Ltd.
20120047475 - Semiconductor device: A semiconductor device is provided having a physical pattern based on a designed pattern, the designed pattern including a target pattern and a correction pattern designed for a pattern to be formed on a wafer; the target pattern includes a first portion of an edge with a first distance, a... Agent: Kabushiki Kaisha Toshiba
20120047476 - Circuit design optimization: A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive... Agent: International Business Machines Corporation
20120047478 - Method for estimating the latency time of a clock tree in an asic design: Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a... Agent: International Business Machines Corporation
20120047477 - Method of measuring the impact of clock skew on slack during a statistical static timing analysis: Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured... Agent: International Business Machines Corporation
20120047479 - Incremental layout analysis: Techniques for incrementally analyzing layout design data are disclose. With various implementations, a subsequent incremental analysis can be made for only portions of layout design data, using a subset of available analysis criteria, or some combination of both. For example, the analysis can be limited to errors identified in a... Agent: Mentor Graphics Corporation
20120047480 - Design method of semiconductor integrated circuit and computer readable medium: According to one embodiment, a design method of a semiconductor integrated circuit is a design method of a semiconductor integrated circuit including a first wiring layer, a second wiring layer formed on the first wiring layer, and a third wiring layer formed on the second wiring layer. This method includes... Agent: Kabushiki Kaisha Toshiba
20120047481 - Implementing phase locked loop (pll) with enhanced locking capability with a wide range dynamic reference clock: A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a... Agent: International Business Machines Corporation02/16/2012 > 9 patent applications in 7 patent subcategories.
20120042291 - Inverse mask design and correction for electronic design: Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by proximity correction.... Agent:
20120042290 - Method of selecting a set of illumination conditions of a lithographic apparatus for optimizing an integrated circuit physical layout: The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An... Agent: Takumi Technology Corporation
20120042292 - Method of synthesis of an electronic circuit: A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device,... Agent: Stmicroelectronics (crolles 2) Sas
20120042293 - Synchronizing tap controller after power is restored: A system includes multiple TAP controllers that can be independently powered up and down. When a first TAP controller is powered up from a powered-down state while a second TAP controller is already in a powered-up state, the first TAP controller is reset causing the first TAP controller to enter... Agent:
20120042294 - Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but... Agent: Atrenta, Inc.
20120042295 - Automated planning in physical synthesis: A method, system, and computer usable program product for automated planning in physical synthesis are provided in the illustrative embodiments. A state of an integrated circuit design is identified where the state is a representation of a particular configuration of circuit components having a particular electrical characteristic. A first operation... Agent: International Business Machines Corporation
20120042296 - Asymmetric segmented channel transistors: Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel... Agent: Infineon Technologies Ag
20120042297 - Computer aided design system and method: A computer aided design system comprises an interface creating module, a selecting module, a filling module and a measuring module. The interface module creates a user interface to display the design on the screen of the device with a plurality of to-be-checked patterns. The selecting module selects a pattern. The... Agent: Hong Fu Jin Precision Industry (shenzhen) Co. Ltd.
20120042298 - Structure having substantially parallel resistor material lengths: A design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a sub-lithographic dimension and may be spacer shaped.... Agent: International Business Machines Corporation02/09/2012 > 6 patent applications in 6 patent subcategories.
20120036486 - Method for resizing pattern to be written by lithography technique, and charged particle beam writing method: A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes... Agent: Nuflare Technology, Inc.
20120036487 - Fracturing continuous photolithography masks: A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such... Agent: International Business Machines Corporation
20120036488 - Method and apparatus for automatic relative placement rule generation: Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.... Agent: Synopsys, Inc.
20120036489 - Design and verification of 3d integrated circuits: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd., ("tsmc")
20120036490 - Information processing device and design supporting method: An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each... Agent: Fujitsu Semiconductor Limited
20120036491 - Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout: Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The... Agent: International Business Machines Corporation02/02/2012 > 7 patent applications in 7 patent subcategories.
20120030638 - Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same: Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of a rectangular target geometry may comprise predicting a contour of an image to be produced in an optical proximity... Agent: Micron Technology, Inc.
20120030639 - Computing device and method for checking signal transmission lines: A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.
20120030640 - Design support apparatus, control method, and control program: A design support apparatus that supports designing of a circuit and is connected to a display unit, the design support apparatus includes a storage unit that stores logical connection information of the circuit and cell information of a plurality of cells included in the circuit, a selection unit that selects... Agent: Fujitsu Limited
20120030641 - Performing scenario reduction using a dominance relation on a set of corners: Some embodiments of the present invention provide techniques and systems for performing scenario reduction using a dominance relation on a set of corners. During operation, the system can receive a design library which specifies gate characteristics at each corner in a set of corners. Next, the system can use the... Agent: Synopsys, Inc.
20120030642 - Hyper-concurrent multi-scenario optimization: Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic... Agent: Synopsys, Inc.
20120030643 - Assessing printability of a very-large-scale integration design: Printability of a very-large-scale integration design is assessed by: during a training phase, generating a training set of very-large-scale integration design shapes representative of a population of very-large-scale integration design shapes, obtaining a set of mathematical representations of respective shapes in the training set, identifying at least two classes of... Agent: International Business Machines Corporation
20120030644 - Method and system for implementing stacked vias: The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical... Agent: Cadence Design Systems, Inc.Previous industry: Data processing: presentation processing of document
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