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Data processing: design and analysis of circuit or semiconductor mask November recently filed with US Patent Office 11/10

20100299643 - Method for manufacturing semiconductor device, apparatus for manufacturing semiconductor device, program for manufacturing semiconductor device, and program for generating mask data: A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to... Agent: Sonnenschein Nath & Rosenthal LLP

20100299645 - Design support computer product, apparatus, and method: A computer-readable recording medium stores a design support program causing a computer to perform: detecting a data path and a clock path corresponding to the data path making up a partial circuit in a circuit-under-design; selecting an object cell from cells on the data path and the clock path detected... Agent: Fujitsu Patent Center Fujitsu Management Services Of America, Inc.

20100299644 - Timing adjustment device and method thereof: A timing adjustment device includes a plurality of receive circuits that receive an input signal based on mutually different timings, a determination circuit that determines a first transition and a second transition of the input signal based on a received result by receive circuits, among the plurality of receive circuits,... Agent: Arent Fox LLP

20100299646 - Uniformity for semiconductor patterning operations: Systems and methods of semiconductor device optimization include a system and method to determine a dataset for a layer of the semiconductor device, where the operation includes receiving a dataset defining a plurality of original patterns of sacrificial material in a layer of a semiconductor device, wherein the original patterns... Agent: Sheppard Mullin Richter & Hampton LLP

20100299647 - Method and apparatus for managing the configuration and functionality of a semiconductor design: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use... Agent: Ropes & Gray LLP

20100299648 - Modular array defined by standard cell logic: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.... Agent: Schwabe Williamson & Wyatt Pacwest Center, Suite 1900

20100299649 - Novel optimization for circuit design: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result.... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100293512 - Chip design and fabrication method optimized for profit: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20100293513 - Method and system for design simplification through implication-based analysis: Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the... Agent: The Brevetto Law Group, PLLC

20100293514 - Design-driven metal critical dimension (cd) biasing: A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of... Agent: Haynes And Boone, LLPIPSection

20100293515 - Method of layout of pattern: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The... Agent: Young & Thompson

20100293516 - Mask system employing substantially circular optical proximity correction target and method of manufacture thereof: A method of manufacture of a mask system includes: providing design data; generating a substantially circular optical proximity correction target from the design data; biasing a segment of the substantially circular optical proximity correction target; and generating mask data based on the shape produced by biasing the segment of the... Agent: Law Offices Of Mikio Ishimaru

20100293517 - Method, system, and computer product for forming a graph structure that describes free and occupied areas: A graph structure is generated to describe an area with a free area and an occupied area. In this case a topological graph structure for the free area is determined. A point of the topological graph structure is selected and for this a nearest adjacent occupied area point is determined.... Agent: Staas & Halsey LLP

20100293518 - Nanoscale interconnection interface: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map... Agent: Hewlett-packard Company Intellectual Property Administration

20100287515 - interactive checker in a layout editor: Methods, articles of manufacture and apparatus for testing design layouts. Design layout software may be configured to display a layout diagram in a first area of a graphical user interface (GUI) screen. Parameters for testing the layout may be entered in a second area of the GUI screen. Upon receiving... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20100287516 - Methods and system for selecting gate sizes, repeater locations, and repeater sizes of an integrated circuit: A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of... Agent: Brooks Kushman P.C. /oracle America/ Sun / Stk

20100287517 - Statistical static timing analysis in non-linear regions: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point... Agent: Texas Instruments Incorporated

20100287518 - Cell circuit and layout with linear finfet structures: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the... Agent: Martine Penilla & Gencarella, LLP

20100287519 - Method and system for constructing a customized layout figure group: A method and a system for constructing a customized layout figure group are disclosed. The method provides improved options for users to flexibly create a customized figure group design. During the layout process, the layout shape, the leaf device and the nest device with design parameters can be created with... Agent: Wpat, PC Intellectual Property Attorneys

20100287520 - Dummy rule generating apparatus: A dummy rule generating apparatus includes a critical pattern estimating unit that determines a wiring pattern whose total perimeter length of wirings is smaller than an appropriate range based on constraints on the wirings for a circuit layout as a critical pattern. The dummy rule generating apparatus also includes a... Agent: Staas & Halsey LLP

20100287521 - Mask creation with hierarchy management using cover cells: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to... Agent: Klarquist Sparkman, LLP

20100287522 - Method and apparatus for automated synthesis of multi-channel circuits: Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100287523 - Design rule management method, design rule management program, rule management apparatus, and rule verification apparatus: A design rule management method implemented in a rule verification apparatus for checking a violation against a design rule which specifies a part shape when there is any change in parameters in a system, the rule verification apparatus including: a processing unit for processing information; an input unit for inputting... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100287524 - Metastability effects simulation for a circuit description: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned... Agent: Klarquist Sparkman, LLP

20100281443 - Change point finding method and apparatus: A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic... Agent: Wpat, PC Intellectual Property Attorneys

20100281442 - Technique for determining circuit interdependencies: Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as... Agent: Pvf -- Oracle America, Inc. C/o Park, Vaughan & Fleming LLP

20100281445 - Efficient exhaustive path-based static timing analysis using a fast estimation technique: One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20100281446 - Integrated circuit design using dfm-enhanced architecture: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first... Agent: Slater & Matsil, L.L.P.

20100281448 - Low-power fpga circuits and methods: Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration... Agent: John P. O'banion O'banion & Ritchey LLP

20100281447 - Method for detecting contradictory timing constraint conflicts: The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and weights of the directed edges according to timing constraints relevant to... Agent: International Business Machines Corporation Dept. 18g

20100281444 - Multiple-power-domain static timing analysis: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20100281449 - Method for forming arbitrary lithographic wavefronts using standard mask technology: A desired set of diffracted waves using mask features whose transmissions are chosen from a set of supported values are generated. A representation of the mask as a set of polygonal elements is created. Constraints which require that the ratio of the spatial frequencies in the representation take on the... Agent: Harrington & Smith

20100281450 - Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells: A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a... Agent: Pillsbury Winthrop Shaw Pittman LLP

20100281451 - Designing an asic based on execution of a software program on a processing system: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at... Agent: Jeffrey C. Hood Meyertons Hood Kivlin Kowert & Goetzel PC

20100281452 - Layout design method, layout design program, and layout design apparatus: It is desired to make it possible to generate a layout whose chip area is small for a semiconductor integrated circuit having a plurality of power supply systems in an internal circuit region. Power supply line of a first power supply is generated in an internal circuit region. Each of... Agent: Young & Thompson

20100281453 - System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices: A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more... Agent: Mahamedi Paradice Kreisman LLP

20100281454 - System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices: A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more... Agent: Mahamedi Paradice Kreisman LLP