|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor mask May archived by USPTO category 05/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/27/2010 > patent applications in patent subcategories. archived by USPTO category
20100131906 - Design method for transmission lines using meta-materials: High frequency circuits for wireless, digital and microwave applications place requirements upon the impedance of their signal lines, interconnects and packaging. In designing and implementing the substrates for these signal lines it is beneficial to employ meta-materials to provide the desired impedance. Such meta-materials providing a means to provide modified... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100131907 - Apparatus, method and computer-readable code for automated design of physical structures of integrated circuits: Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to... Agent: Dr. Mark M. Friedman C/o Bill Polkinghorn - Discovery Dispatch
20100131908 - Sub-circuit pattern recognition in integrated circuit design: A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist... Agent: Texas Instruments Incorporated
20100131909 - Fast lithography compliance check for place and route optimization: A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully... Agent: Silicon Valley Patent Group LLP Attn: Synopsys
20100131911 - Method and system for high speed and low memory footprint static timing analysis: The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing... Agent: Deborah Neville
20100131910 - Simulating scan tests with reduced resources: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a... Agent: Nvidia C/o Murabito, Hao & Barnes LLP
20100131913 - Method and apparatus for scaling i/o-cell placement during die-size optimization: One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP
20100131912 - Retiming of multirate system: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20100131914 - Method to determine process window: A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of... Agent: North America Intellectual Property Corporation
20100131915 - Method, device, and program for predicting a manufacturing defect part of a semiconductor device: Provided is a method of predicting a manufacturing defect part of a semiconductor device, which results from optical pattern displacement in an exposure process. The prediction method includes: performing repetitive processing a plurality of times, the repetitive processing including: a site generating step of setting a site at a predetermined... Agent: Mcginn Intellectual Property Law Group, PLLC05/20/2010 > patent applications in patent subcategories. archived by USPTO category
20100125820 - Unfolding algorithm in multirate system folding: Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit operation level before using optimizing with data flow algorithm... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20100125821 - Design support method: A method for a design support is provided. The method includes a computer that executes processes of detecting a combination of vias comprising a target via and a neighboring via-; calculating a distance between the combination of the target via and the neighboring via, replacing a shape of the target... Agent: Staas & Halsey LLP
20100125822 - Methods, systems, and computer program prodcut for implementing interactive cross-domain package driven i/o planning and placement optimization: Disclosed are a method, a system, and a computer program product for implementing interactive cross-domain package driven I/O planning and placement optimization of an electronic circuit design. In some embodiments, the method identifies an object on a first EDA tool session, determines a drop location for the first object based... Agent: VistaIPLaw Group LLP
20100125823 - Systems and methods for adjusting a lithographic scanner: A system and methods are provide for modeling the behavior of a lithographic scanner and, more particularly, a system and methods are provide using thresholds of an image profile to characterize through-pitch printing behavior of a lithographic scanner. The method includes running a lithographic model for a target tool and... Agent: Greenblum & Bernstein, P.L.C05/13/2010 > patent applications in patent subcategories. archived by USPTO category
20100122221 - Method and apparatus for designing a device for electro-optical modulation of light incident upon the device: A method and apparatus for designing a device to operate in a coupling mode, a detection mode, or a reflection mode for incident light. The incident light has a wavelength λ and is incident upon a semiconductor structure of the device at an angle of incidence (θi). A voltage (V)... Agent: Schmeiser, Olsen & Watts
20100122224 - Method and apparatus for designing an integrated circuit: Method and apparatus for designing an integrated circuit by providing an IC layout design. Adding one or more assist features to the IC layout design. Identifying which of the one or more added assist features in the IC layout design will cause one or more defects in the resultant wafer... Agent: Larson Newman & Abel, LLP
20100122225 - Pattern selection for lithographic model calibration: The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20100122222 - System and method for three-dimensional variational capacitance calculation: Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One... Agent: Michael J. Chang, LLC
20100122223 - Techniques for computing capacitances in a medium with three-dimensional conformal dielectrics: Techniques for capacitance extraction from an integrated circuit design are provided. In one aspect, a method for determining coupling capacitance between conductors within an integrated circuit design is provided comprising the following steps. A three-dimensional representation of the integrated circuit design is generated based on three-dimensional technology and three-dimensional geometric... Agent: Michael J. Chang, LLC
20100122226 - Layout density verification system and layout density verification method: A layout density verification system has: a model generation unit configured to generate a macro model for use in metal density check, with respect to a macro included in a layout data; and a metal density check unit configured to perform the metal density check of the layout data by... Agent: Young & Thompson
20100122227 - System and technique of pattern matching and pattern replacement: A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns.... Agent: Aka Chan LLP
20100122228 - Method and system for conducting design explorations of an integrated circuit: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or... Agent: VistaIPLaw Group LLP
20100122229 - Apparatus and method of preventing congestive placement: An apparatus of preventing congestive placement is provided. The apparatus comprises a judging module, a pattern generating module, and a placement module. The judging module judges whether a circuit layout comprises a congestive region according to a judging rule. When a judgment result of the judging module is affirmative, the... Agent: Wpat, PC Intellectual Property Attorneys
20100122230 - Method to automatically add power line in channel between macros: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.... Agent: Qualcomm Incorporated
20100122231 - Electrically-driven optical proximity correction to compensate for non-optical effects: A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to... Agent: Ibm Corporation (jvm)05/06/2010 > patent applications in patent subcategories. archived by USPTO category
20100115474 - Non-contact power transmission apparatus and method for designing non-contact power transmission apparatus: A non-contact power transmission apparatus having a resonance system is disclosed. The resonance system includes a primary coil to which an alternating-current voltage from an alternating-current source is applied, a primary-side resonance coil, a secondary-side resonance coil, and a secondary coil to which a load is connected. The impedance of... Agent: Woodcock Washburn LLP
20100115476 - Congestion optimization during synthesis: One embodiment of the present invention provides a system that optimizes a circuit design during a logic design stage to reduce routing congestion during a placement and routing stage. During operation, this system identifies a first circuit structure in the circuit design which is expected to cause routing congestion during... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP
20100115475 - Integrated circuit performance enhancement using on-chip adaptive voltage scaling: Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or... Agent: Ryan, Mason & Lewis, LLP
20100115477 - Optimizing integrated circuit design through use of sequential timing information: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for... Agent: Durant Intellectual Property Law Group
20100115479 - Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program: A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100115478 - Methods, systems, and computer program prodcut for parallelizing tasks in processing an electronic circuit design: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on... Agent: VistaIPLaw Group LLP
20100115480 - Logic circuit design verification apparatus, logic circuit design verification method , and medium storing logic circuit design verification program: A logic circuit design verification apparatus includes an inputting unit configured to input a circuit description and an assertion description, an extracting unit configured to extract signal names from the circuit description input by the inputting unit, a lack detector configured to detect a signal name not included in a... Agent: Knobbe Martens Olson & Bear LLP
20100115481 - Shape-based geometry engine to perform smoothing and other layout beautification operations: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously... Agent: Bever Hoffman & Harms, LLP
20100115482 - Method for specifying and validating untimed nets: In accordance with an aspect of the present invention, the method for specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physical... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20100115485 - Circuit design device for conducting failure analysis facilitating design: A circuit design device decides placement of elements and interconnections included in a circuit, on the basis of connection information of the circuit. The circuit design device includes an equivalent fault class extracting unit, a weighting unit, and a placement deciding unit. The equivalent fault class extracting unit extracts one... Agent: Mcginn Intellectual Property Law Group, PLLC
20100115483 - Crossbar structure with mechanism for generating constant outputs: Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of... Agent: Schwabe, Williamson & Wyatt, P.C.
20100115484 - Standard cell placement: A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the... Agent: Nixon & Vanderhye P.C.
20100115486 - Assist feature placement based on a focus-sensitive cost-covariance field: One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP
20100115488 - Circuit design device, circuit design method, and circuit design program: A circuit design device comprises a logic synthesis unit that generates a circuit with reference to a circuit design description, a statistical timing analysis unit that obtains a probability distribution of delay times of a path in a circuit, a relative delay restriction fulfillment rate calculation unit that obtains a... Agent: Mr. Jackson Chen
20100115487 - Method and system for schematic-visualization driven topologically-equivalent layout design in rfsip: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.... Agent: VistaIPLaw Group LLP
20100115489 - Method and system for performing lithography verification for a double-patterning process: One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLPPrevious industry: Data processing: presentation processing of document
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