|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
USPTO Class 716 | Browse by Industry: Previous - Next | All
03/2010 | Recent | 13: Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Data processing: design and analysis of circuit or semiconductor mask March listing by industry category 03/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/25/2010 > patent applications in patent subcategories. listing by industry category
20100077363 - Isolation method and package using a high isolation differential ball grid array (bga) pattern: According to an embodiment an improved Application Specific Integrated Circuit (ASIC) isolation method and system for assigning signal pins in an ASIC package having a plurality of signal pins is disclosed. The method and system comprise identifying an isolation requirement of the ASIC and determining an optimized pattern for substantially... Agent: Sawyer Law Group PC
20100077364 - Method and apparatus for designing an integrated circuit: Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of... Agent: Freescale Semiconductor, Inc. Law Department
20100077365 - Graphic rendering of circuit positioning: A method may include receiving circuit information from a backend circuit test system and grouping components in the circuit information into collections by types, the types including segments, equipment, ports, and connections. The method may further include positioning, based on the grouping by types, the components from the circuit information... Agent: Verizon Patent Management Group
20100077367 - Layout evaluation apparatus and method: An apparatus that evaluates a layout of a semiconductor integrated circuit by estimating a result of planarization in manufacturing the circuit includes a unit that divides the layout into partial areas, a unit that calculates, for each partial area, at least one of a wiring density in the partial area,... Agent: Fujitsu Patent Center C/o Cpa Global
20100077366 - Method and apparatus for word-level netlist reduction and verification using same: A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP
20100077368 - Method for bounded transactional timing analysis: A portion of a gate-level netlist representing an integrated circuit design is selected for optimization. A timing window representing the selected portion is made comprising one or more copies of the selected portion. A checkpoint is created for the timing window and stored in a transaction history. One or more... Agent: Ibm Corporation (swp)
20100077369 - Layout design method, apparatus and storage medium: A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a... Agent: Fujitsu Patent Center C/o Cpa Global
20100077371 - Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same: A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the... Agent: Mcginn Intellectual Property Law Group, PLLC
20100077370 - System and method of connecting a macro cell to a system power supply: A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. The method... Agent: Qualcomm Incorporated
20100077372 - Apparatus, method and computer program product for fast stimulation of manufacturing effects during integrated circuit design: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict... Agent: Harrington & Smith
20100077373 - Wiring information generating apparatus, method and program: A wiring information generating apparatus includes an input unit that inputs a wiring layer number indicating a wiring layer, a via layer number indicating a next via layer to connect the wiring layer, and spacing information based on wiring rules. A storage unit stores a terminal figure table providing terminal... Agent: Staas & Halsey LLP
20100077374 - Automatic alignment of macro cells: In a particular embodiment, a method is disclosed that includes detecting a first pitch between at least two lines (e.g. a power line and a ground line) of a first reference macro. The method also includes generating a virtual grid based on the first pitch and aligning at least a... Agent: Qualcomm Incorporated03/18/2010 > patent applications in patent subcategories. listing by industry category
20100070933 - Method for selectively implementing low threshold voltage transistors in digital logic designs: A system and method for selectively replacing standard threshold voltage devices with low threshold voltage devices in a digital logic design. The system identifies at least one path having a first timing value, the path having a plurality of standard threshold devices. The path is reverse traversed, or otherwise analyzed... Agent: Dorsey & Whitney LLP On Behalf Of Sun Microsystems, Inc.
20100070934 - Analysis of physical systems via model libraries thereof: A model library contains one or more storable models of a physical system each constructed by numerically solving relationships between a characteristic of the physical system given a set of model parameters. Such a model may be retrieved from the library according to values assigned to the model parameters and... Agent: Rosenberg, Klein & Lee
20100070937 - Circuit verification apparatus, circuit verification method, and recording medium: A circuit verification apparatus includes a code coverage measurement point extracting unit which reads a device-under-test circuit description written in a hardware description language and metrics information including information about multiple measurement objects, extracts multiple measurement points for code coverage measurement from the device-under-test circuit description, and generates a database... Agent: Turocy & Watson, LLP
20100070935 - Method and apparatus for merging eda coverage logs of coverage data: Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP
20100070938 - Preconditioning for eda cell library: A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell.... Agent: Bever, Hoffman & Harms, LLP
20100070936 - Waiver mechanism for physical verification of system designs: A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs,... Agent: Christopher P Maiorana, PC Lsi Corporation
20100070940 - Method and apparatus for merging eda coverage logs of coverage data: Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP
20100070939 - Nanotube circuit analysis system and method: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.... Agent: Iv - Suiter Swantz PC Llo
20100070941 - Achieving clock timing closure in designing an integrated circuit: Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing... Agent: The Mueller Law Office, P.C.
20100070942 - Automated metal pattern generation for integrated circuits: An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal... Agent: Raminda U. Madurawe Suite-215
20100070943 - Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of asic and programmable logic device: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal... Agent: Staas & Halsey LLP
20100070944 - Method for constructing opc model: A method for constructing an optical proximity correction (OPC) model is described. A test pattern is provided, and the test pattern is then written on a mask. The pattern on the mask is measured to obtain a modified pattern. An OPC model is constructed according to the modified pattern.... Agent: North America Intellectual Property Corporation03/11/2010 > patent applications in patent subcategories. listing by industry category
20100064263 - Method for compaction of timing exception paths: A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps... Agent: Sughrue Mion, PLLC
20100064264 - Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization: A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design; measuring a slack difference of each of the plurality of... Agent: Cantor Colburn LLP - IBM Rochester Division
20100064268 - Capacitor arrangement method and layout apparatus: A layout apparatus stores a plurality of capacitor cells which are classifiable into a first classification for identifying capacitor cells having different sizes by frequency characteristic correlating with gate width of a capacitor and a second classification for identifying capacitor cells having different frequency characteristics by cell size. The layout... Agent: Mcginn Intellectual Property Law Group, PLLC
20100064265 - Rf circuit, circuit evaluation method, algorithm and recording medium: It is required to qualitatively design a circuitry device in which not only in a small-signal simulation but also in a large-signal simulation, loop oscillation and motorboating oscillation of an amplifier are precisely predicted to suppress oscillation without severing a loop or without inserting a circulator. To remove insertion loss... Agent: Mcginn Intellectual Property Law Group, PLLC
20100064267 - Semiconductor device design support apparatus and substrate netlist generation method: A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconductor device layout into a plurality of segments and generates... Agent: Mcginn Intellectual Property Law Group, PLLC
20100064266 - Verification support apparatus, verification support method, and computer product: A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting... Agent: Greer, Burns & Crain
20100064270 - Cost-benefit optimization for an airgapped integrated circuit: A computer implemented method, apparatus and program product provide automated processes for determining the most cost-effective use of airgaps in a microchip. The performance gains realized by using airgaps for a given net or layer may be calculated. These improvements may be paired to a monetary cost associated with implementing... Agent: Ibm-rochester C/o Toler Law Group
20100064269 - Method and system for design rule checking enhanced with pattern matching: According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing... Agent: Sheppard Mullin Richter & Hampton LLP
20100064271 - Method and system for simulating state retention of an rtl design: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP
20100064272 - System and method for supporting layout design of semiconductor integrated circuit: In a layout design method of a semiconductor integrated circuit, an IR drop data is calculated to indicate a voltage drop for every local area, and a virtual arrangement library is generated which stores data of a circuit cell to be arranged based on the IR drop data for every... Agent: Mcginn Intellectual Property Law Group, PLLC
20100064273 - Method for compensating for variations in structures of an integrated circuit: A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying... Agent: Schmeiser, Olsen & Watts
20100064274 - Proximity correction method and system: A proximity correction method includes creating a first proximity correction model having a focus value and creating a second proximity correction model having a first defocus value. One of the first or second proximity correction models are associated with corresponding first and second layout areas of a semiconductor wafer.... Agent: Dicke, Billig & Czaja03/04/2010 > patent applications in patent subcategories. listing by industry category
20100058256 - Co-optimization of embedded systems utilizing symbolic execution: Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying... Agent: Ibm Corp (rm) C/o Richard Mccain
20100058257 - Topology optimization method using equivalent static loads: A topology optimization method. Characteristics of a structure to be designed are differentiated to calculate equivalent static loads. A relative fraction of material is adopted as a design variable. It is determined whether or not an element exists based on an objective function and constraints. Design topology is derived through... Agent: Kinney & Lange, P.A.
20100058258 - Method of estimating a leakage current in a semiconductor device: In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage... Agent: Myers Bigel Sibley & Sajovec
20100058260 - Integrated design for manufacturing for 1xn vlsi design: Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20100058264 - Logic circuit verifying method and logic circuit verifying apparatus: A logic verification apparatus for verifying a logic circuit includes a line recognition unit that recognizes signal lines in the circuit based on design information regarding the circuit as a starting point; a decoder recognition unit that recognizes an area including an AND gate that outputs a certain logical value... Agent: Fujitsu Patent Center C/o Cpa Global
20100058259 - Optimization of verification of chip design: Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of... Agent: Schwabe, Williamson & Wyatt, P.C.
20100058263 - Scanner based optical proximity correction system and method of use: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against... Agent: Greenblum & Bernstein, P.L.C
20100058261 - Temporally-assisted resource sharing in electronic systems: Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20100058262 - Verification assisting program, verification assisting apparatus, and verification assisting method: A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning... Agent: Greer, Burns & Crain
20100058266 - 3-stack floorplan for floating point unit: A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below... Agent: Cantor Colburn LLP-ibm Europe
20100058265 - Parallel intrusion search in hierarchical vlsi designs with substituting scan line: Mechanisms are provided for performing intrusion searching of a hierarchical integrated circuit design. These mechanisms may receive the hierarchical integrated circuit design and perform a parallel intrusion search operation, that utilizes a substituting scan line, on the hierarchical integrated circuit design to identify intrusions of geometric objects in the hierarchical... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20100058267 - Place-and-route layout method with same footprint cells: This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.... Agent: K&l Gates LLPIPDocketing
20100058268 - Layout determination: A device includes a processor and a computer-readable medium including computer-readable instructions. Upon execution by the processor, the computer-readable instructions cause the device to receive a first request from a second device, where the first request is a layout request that includes an identification of a space. The computer-readable instructions... Agent: Foley & Lardner LLP
20100058269 - Uniquification and parent-child constructs for 1xn vlsi design: Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20100058273 - Automatic wiring device, automatic wiring method, and automatic wiring program: An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value.... Agent: Staas & Halsey LLP
20100058271 - Closed-loop 1xn vlsi design system: Embodiments that design integrated circuits using a closed loop 1xN methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1xN building blocks. The embodiments may alter... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20100058272 - Compiler for closed-loop 1xn vlsi design: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20100058270 - Hierarchy reassembler for 1xn vlsi design: Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20100058274 - Flexible hardware upgrade mechanism for data communications equipment: Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial reconfiguration may enable alteration of a clock frequency without affecting operation of the software. When a new interface is installed, partial reconfiguration will allow a... Agent: Kramer & Amado, P.C.
20100058276 - Method for the integration of an integrated circuit into a standardized software architecture for embedded systems: A method is disclosed for the integration of an integrated circuit into a standardized software architecture for embedded systems. The method includes a definition of a computer readable standardized data structure which is completed with the properties of the integrated circuit. The completed standardized data structure is then used for... Agent: Delphi Technologies, Inc.
20100058275 - Top level hierarchy wiring via 1xn compiler: Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of... Agent: Ibm Corporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20100058278 - Method and apparatus for automated synthesis of multi-channel circuits: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20100058277 - Method and system for organizing data generated by electronic design automation tools: A method and system for organizing a plurality of files generated by an Electronic Design and Automation (EDA) tool into composite objects is disclosed. The system provides a plurality of rules, which may be configured for various EDA tools. These rules may be configured for any EDA tool by specifying... Agent: Lester H. Birnbaum
20100058279 - Method and system for design of a reticle to be manufactured using variable shaped beam lithography: A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are... Agent: The Mueller Law Office, P.C.
20100058280 - Bulk image modeling for optical proximity correction: A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP
20100058282 - Method and system for design of a reticle to be manufactured using character projection lithography: A method for fracturing or mask data preparation or proximity effect correction is disclosed which comprises the steps of inputting patterns to be formed on a surface, a subset of the patterns being slightly different variations of each other and selecting a set of characters some of which are complex... Agent: The Mueller Law Office, P.C.
20100058281 - Method for optical proximity correction of a reticle to be manufactured using character projection lithography: A method for optical proximity correction of a design of a pattern on a surface is disclosed with the method comprising the steps of inputting desired patterns for the substrate and inputting a set of characters some of which are complex characters that may be used for forming the patterns... Agent: The Mueller Law Office, P.C.Previous industry: Data processing: presentation processing of document
Next industry: Data processing: software development, installation, and management
RSS FEED for 20130613:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Data processing: design and analysis of circuit or semiconductor mask patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Data processing: design and analysis of circuit or semiconductor mask patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Data processing: design and analysis of circuit or semiconductor mask patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 0.42184 seconds