Data processing: design and analysis of circuit or semiconductor mask inventions 10/09

20090249260 - Description processing device, description processing method, and recording medium: A receiving unit 20 receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N−1; a dividing unit 30 dividing the states 0, 1, 2, . . . , N−1 into groups 0, 1, 2, . . . , M−1, wherein the dividing... Agent: Nec Corporation Of America

20090249259 - High-speed low-leakage-power standard cell library: A high-speed, low leakage-power Standard Cell Library is provided. The high-speed, low-leakage-power Standard Cell Library provides the extra drive-strength of a taller X-Track library (e.g., 14-Track library) and low leakage-power comparable to that of a smaller, N-Track library (e.g., 10-Track library). The high-speed, low leakage-power Standard Cell Library includes a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090249262 - Behavioral synthesis device, behavioral synthesis method, and computer program product: A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit;... Agent: Nec Corporation Of America

20090249261 - Method and apparatus for optimizing an optical proximity correction model: A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in... Agent: Williams, Morgan & Amerson

20090249263 - Semiconductor circuit design method and semiconductor circuit manufacturing method: A computer converts dimensions of design patterns of components of the transistors configuring the semiconductor circuit or component parameters extracted from in-design physical characteristics of the transistors into simulation parameters inputted to the simulator, organize the plurality of transistors included in the semiconductor circuit into a plurality of groups, selects... Agent: Fujitsu Patent Center C/o Cpa Global

20090249264 - Analyzing device for circuit device, circuit device analyzing method, analyzing program, and electronic medium: A circuit board analyzing method and a circuit board analyzer are provided which can greatly reduce analyzing time. The circuit board analyzer includes a computing unit 110, a memory unit 140 connected to the computing unit 110, and an input unit 160 connected to the computing unit 110. The computing... Agent: Pearne & Gordon LLP

20090249266 - Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment... Agent: Bever Hoffman & Harms, LLP

20090249265 - Printed circuit board designing apparatus and printed circuit board designing method: A method for designing a printed circuit board includes: determining a distance along a conductive line between an electronic component and a signal source which are mounted on the printed circuit board, the signal source transmitting a signal to the electronic component; calculating a maximum distance for preventing a voltage... Agent: Fujitsu Patent Center C/o Cpa Global

20090249267 - Constrained random simulation coverage closure guided by a cover property: One embodiment of the present invention provides a system which verifies a circuit design by biasing input stimuli for the circuit design to satisfy one or more temporal coverage properties to be verified for the circuit design. This system performs a simulation in which random input stimuli are applied to... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090249269 - Property checking system, property checking method, and computer-readable storage medium: Checking efficiency of property checking is improved. The operation synthesis tool synthesizes an RTL circuit description from a behavioral level circuit description. In addition, the property generating unit generates a behavioral level property from the behavioral level circuit description. Subsequently, the property converting unit converts the generated behavioral level property... Agent: Nec Corporation Of America

20090249268 - Warning device and warning method: A warning device checks for errors in design object data and issues a warning for detected errors by storing allowance information, which allows issuance of warning prevention, cancel information, which cancels relevant allowance information to permit issuance of warning for each error identification, and instruction identification, which identifies an edit... Agent: Staas & Halsey LLP

20090249270 - Methods for practical worst test definition and debug during block based statistical static timing analysis: Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090249271 - Microcontroller, control system and design method of microcontroller: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock... Agent: Mattingly & Malur, P.c.

20090249272 - Statistical timing analyzer and statistical timing analysis method: A statistical timing analyzer comprises a statistical static-timing analyzing unit that performs a statistical static timing analysis of a semiconductor integrated circuit; a corner-condition determining unit that determines corner conditions of the semiconductor integrated circuit based on a result of the statistical static timing analysis; and a path-timing analyzing unit... Agent: Turocy & Watson, LLP

20090249273 - Layout circuit having a combined tie cell: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090249274 - Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof: A first library cell and a second library cell each includes a plurality of metal layers, and a metal track direction of the odd metal layers of the first library cell is perpendicular to that of the odd metal layers of the second library cell. An integrated circuit design method... Agent: North America Intellectual Property Corporation

20090249275 - Method of semiconductor integrated circuit, recording medium recording design program of semiconductor integrated circuit, and design support apparatus of semiconductor integrated circuit: A design method of a semiconductor integrated circuit carried out by a computer, including: a DRC step of performing a design rule check (Design Rule Check) with reference to layout information on an internal wiring in a capacitor cell and layout information on a signal wiring in the semiconductor integrated... Agent: Nec Corporation Of America

20090249276 - Methods and systems for fpga rewiring and routing in eda designs: Disclosed are a method and a system for improving FPGA routings of a circuit. The method comprises: identifying candidate alternative wires for a target wire to be replaced in the circuit according to a first preset rule; selecting a first set of alternative wires from the identified candidates according to... Agent: Seed Intellectual Property Law Group Pllc