Data processing: design and analysis of circuit or semiconductor mask inventions 09/09

20090241073 - Radiation tolerance by clock signal interleaving: A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to... Agent: Ibm Corporation (jvm)

20090241074 - Equivalence checking method, equivalence checking program, and generating method for equivalence checking program: To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample... Agent: Miles & Stockbridge PC

20090241075 - Test chip validation and development system: Embodiments of an IC design system for test row/structure layout design are described in this application. The design system may include a test chip complier database, a test chip complier engine (TCCE), and a user interface module. The TCCE may be configured to communicate with at least the test chip... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090241077 - Site selective optical proximity correction: Techniques for performing optical proximity correction on a layout design or portion thereof are provided with various implementations of the invention. With various implementations of the invention, movement and simulation of selected edge fragments is disabled during the optical proximity correction process. The operations of the optical proximity correction process,... Agent: Mentor Graphics Corp. Patent Group

20090241076 - Test-cases for functional verification of system-level interconnect: Generation of test cases for functional verification of a complex system-under-test is achieved by the use of a probability matrix. The probability matrix represents a non-uniform distribution function of resource combinations used in the transactions, and can be created randomly, or by application of various types of testing knowledge. The... Agent: Ibm Corporation, T.j. Watson Research Center

20090241079 - Method and system for achieving power optimization in a hierarchical netlist: The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of... Agent: Greenblum & Bernstein, P.L.C

20090241078 - Methods for conserving memory in statistical static timing analysis: A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090241081 - Reverse donut model: A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified... Agent: Martine Penilla & Gencarella, LLP

20090241080 - Setup and hold time characterization device and method: A method of characterizing a device under test (DUT) includes determining a goal function associated with a setup and hold time for the DUT. A minimum value for the goal function is determined by iteratively adjusting setup and hold times for input data to the DUT, and determining whether the... Agent: Larson Newman & Abel, LLP

20090241082 - Method and system for generating an accurate physical realization for an integrated circuit having incomplete physical constraints: A method, system and program product are described for implementing an integrated circuit. Synthesis tools and a continuum of physical constraints are used to generate a physical realization of a circuit from a hierarchy of logical circuits. Missing physical constraints are generated based on the behavior of the logical circuits,... Agent: Ibm-rochester C/o Toler Law Group

20090241083 - Router-aided post-placement-and-routing-retiming: A method of minimising the longest delay path between two logic elements of a circuit placed on a reconfigurable device, each logic element being associated with a register and the reconfigurable device including logic elements and associated registers which are programmed to be transparent, the method includes the steps of... Agent: Ratnerprestia

20090241084 - Method, system and computer program product for exploiting orthogonal control vectors in timing driven systems: Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090241086 - Method of making pattern data, and medium for storing the program for making the pattern data: A method of making pattern data of a photomask pattern includes: the processes of adding, to each of first cells, information of the first cell higher than the first cell on the basis of a hierarchical structure; selecting, from the first cells included in one level of the hierarchical structure,... Agent: Fujitsu Patent Center C/o Cpa Global

20090241085 - System and method for implementing optical rule checking to identify and quantify corner rounding errors: A method for implementing optical rule checking to identify and quantify corner rounding errors includes receiving corner rounding data based on established ground rules; determining a simulated shape for a semiconductor device feature produced on a wafer, the simulated shape based on a designed shape for the semiconductor device feature;... Agent: Cantor Colburn LLP - IBM Fishkill

20090241087 - System for simplifying layout processing: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design... Agent: William C. Milks, Iii

20090235208 - Lighting apparatus: The lighting apparatus according to the present invention is a lighting apparatus which lights by emitting light through solid-state light-emitting devices using an AC power source, the lighting apparatus including an AC to DC conversion unit which converts AC from the power source into DC, and a power source device... Agent: Greenblum & Bernstein, P.L.C

20090235209 - Manufacturability: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the... Agent: Mentor Graphics Corp. Patent Group

20090235211 - Method of predicting substrate current in high voltage device: A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may be accomplished by modeling a substrate current component in a third region, in which an inconsistency... Agent: Sherr & Vaughn, PLLC

20090235210 - Orientation optimization method of 2-pin logic cell: In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is... Agent: Wpat, PC

20090235212 - Design structure, failure analysis tool and method of determining white bump location using failure analysis tool: A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20090235213 - Layout-versus-schematic analysis for symmetric circuits: Techniques for reducing the complexity of Electronic Design Automation Layout-Versus-Schematic algorithms to approximately O(n) for graphs without type-3 symmetries.... Agent: Mentor Graphics Corp. Patent Group

20090235216 - Combinational equivalence checking for threshold logic circuits: Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second... Agent: Mcandrews Held & Malloy, Ltd

20090235215 - Gridded glyph geometric objects (l3go) design method: A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer... Agent: Law Office Of Charles W. Peterson, Jr. Fishkill

20090235214 - Variable performance ranking and modification in design for manufacturability of circuits: A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of... Agent: Ibm-rochester C/o Toler Law Group

20090235217 - Method to identify timing violations outside of manufacturing specification limits: A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090235218 - Testing phase error of multiple on-die clocks: The phase relationship between two clock signals in an integrated circuit (IC) is determined by transforming each of the clock signals into a data word, where bit transitions in the data word represent signal transitions in the clock signal, and comparing the two data words. For example, in an IC... Agent: Kathy Manke Avago Technologies Limited

20090235219 - Hierarchical analog ic placement subject to symmetry, matching and proximity constraints: A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the... Agent: Smith-hill And Bedell, P.C.

20090235220 - Data processing device, behavioral synthesis device, data processing method, and recording medium: A behavioral synthesis unit generates an intermediate level description that describes a plurality of processes indicated by a behavioral level description and data passed over during the plurality of processes based oil a behavioral level description describing the behavior of an electronic circuit and synthesis constraint information constituting constraints to... Agent: Nec Corporation Of America

20090235221 - Routing channel displaying method and computer-accessible storage medium thereof: A routing channel displaying method and a computer-accessible storage medium are provided. In the method, a circuit board is divided into m×n blocks which form a matrix with size m×n, and m, n are positive integers. Then, a processing direction is determined by a relative position of a first and... Agent: J C Patents, Inc.

20090235222 - Creating a standard cell circuit design from a programmable logic device circuit design: A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist (110), mapping logic gates of the netlist to functionally equivalent standard cells (120), and including the standard cells... Agent: Xilinx, Inc Attn: Legal Department

20090235223 - Program generation apparatus and program generation method: According to one embodiment, a software generation apparatus generates software for verifying a RTL description obtained by high-level synthesis of an operation description describing an LSI operation. The apparatus comprises a judgment function generation module configured to generate a judgment function based on a test program for verifying the operation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090235224 - Method for processing optical proximity correction: A method for processing optical proximity correction includes preparing a chemical mechanical polishing (CMP) map; extracting calibration data depending on a focus degree with the CMP map; and correcting optical proximity with the calibration data.... Agent: Marshall, Gerstein & Borun LLP

20090228844 - Method for reducing power consumption of integrated circuit: A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks,... Agent: Wpat, PC Intellectual Property Attorneys

20090228843 - Method to optimize power by tuning the selective voltage binning cut point: A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090228846 - Global statistical optimization, characterization, and design: For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO can perform global yield optimization on hundreds of variables, with no simplifying assumptions. GSC can capture and display mappings... Agent: Eaton Peabody Patent Group, LLC

20090228847 - High-frequency vlsi interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy... Agent: Klarquist Sparkman, LLP

20090228845 - Method, design program and design system for semiconductor device: A method of designing a semiconductor device includes: calculating a design value of a noise parameter based on design specification of the semiconductor device. The noise parameter contributes to power-supply noise of the semiconductor device. The method further includes: setting the noise parameter variably within a predetermined range including the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090228848 - Circuit verification apparatus, a method of circuit verification and circuit verification program: A circuit verification apparatus for verifying justice of wiring connections of PWB is provided. The circuit verification apparatus includes a net list reduction part for generating a reduction net list in which unnecessary components and connections for verification are eliminated from connection relationships for all components used in the PWB;... Agent: Nec Corporation Of America

20090228849 - Method for using an equivalence checker to reduce verification effort in a system having analog blocks: A computer-implemented method of performing an equivalence check on a mixed-signal circuit is performed on a server system, and includes responding to a verification request. In the method, the following operations are performed. A static analysis is performed on a first netlist, and a synthesizable section and non-synthesizable section of... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20090228851 - Arbitrary waveform propagation through a logic gate using timing analysis results: An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured... Agent: Hoffman Warnick LLC

20090228850 - Method of modeling and employing the cmos gate slew and output load dependent pin capacitance during timing analysis: An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC... Agent: International Business Machines Corporation Dept. 18g

20090228852 - Method and system for verification of multi-voltage circuit design: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090228853 - Methods for defining contact grid in dynamic array architecture: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively.... Agent: Martine Penilla & Gencarella, LLP

20090228854 - Wiring model library constructing device and constructing method, and layout parameter extracting device and extracting method: A wiring model library constructing method includes: obtaining a correction value of wiring widths on the basis of a plurality of first wiring area ratios and a first wiring film thickness of a plurality of first subject wirings in a plurality of first test wiring patterns each having the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20090228855 - Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating... Agent: Christopher P Maiorana, PC Lsi Corporation

20090228857 - Enforcement of semiconductor structure regularity for localized transistors and interconnect: A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating... Agent: Martine Penilla & Gencarella, LLP

20090228856 - Via-node-based electromigration rule-check methodology: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of... Agent: Texas Instruments Incorporated

20090228858 - Circuit-designing support system, method of displaying in circuit- designing support system, and computer-readable recording medium: A circuit-designing support system performs a behavioral synthesis process based on an input behavior level description and creates a register transfer (RT) level description. The system causes a behavior level description display unit to display the behavior level description and causes an RT level description display unit to display the... Agent: Nec Corporation Of America

20090228859 - Synthesis constraint creating device, behavioral synthesis device, synthesis constraint creating method and recording medium: A synthesis constraint creating unit has a process emergence number acquiring unit that acquires, for each process attribute, the emergence number of the process belonging to each process attribute, the process being in the behavior level description, a circuit structure component specifying unit that specifies a kind of a circuit... Agent: Nec Corporation Of America

20090228860 - Photomask data processing method, photomask data processing system and manufacturing method: A computer-implemented method, of processing design data to obtain photomask data, includes: selecting, amongst design data, data representing a first cell; selecting a first area in said first cell for which a configuration of a corresponding first pattern is influenced by patterns arranged outward relative to said first cell area;... Agent: Fujitsu Patent Center C/o Cpa Global

20090222772 - Power gating logic cones: Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power... Agent: Hoffman Warnick LLC

20090222773 - Leakage current analyzing apparatus, leakage current analyzing method, and computer product: A leakage current analyzing apparatus receives input of data used for analysis and indicating intra/inter-chip variation concerning the gate length of transistors constituting cells in a circuit to be designed, where the inter-chip variation is handled as a discrete probability density distribution R. Using the data input, the leakage current... Agent: Greer, Burns & Crain

20090222775 - Characterising circuit cell performance variability in response to pertibations in manufacturing process parameters: A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) resulting from a joint distribution across manufacturing process parameter space is determined. The perturbation in manufacturing... Agent: Nixon & Vanderhye P.C.

20090222776 - Device for and a method of designing a sensor arrangement for a safe automated system, an automated system, a program element and a computer-readable medium: A device for designing a sensor arrangement for an automated system, the device comprising a first input unit for receiving a specification of a plurality of sensor measurements to be carried out by the sensor arrangement, a second input unit for receiving a specification of a confidence region together with... Agent: Smith Frohwein Tempel Greenlee Blaha, LLC

20090222777 - Links and chains verification and validation methodology for digital devices: The links and chains (LNC) of this invention is an applications verification and validation (AVV) methodology. LNC is a hierarchical and systematic approach emphasizing conservation and reuse of effort expended. LNC creates objective metrics for validation. This invention ensures that the device will work in a system environment. LNC is... Agent: Texas Instruments Incorporated

20090222774 - Method for evaluating the quality of a computer program: e

20090222778 - Property generating apparatus, property generating method and program: Disclosed is a property generating apparatus which generates a property representing a specification of an integrated circuit and verifying design information on the integrated circuit described in RTL (Register Transfer Level). The property generating apparatus includes: a storage unit, which stores a register name to identify a register; an address... Agent: Nec Corporation Of America

20090222780 - Half cycle common path pessimism removal method: A design tool for reducing half-cycle common path pessimism includes program instructions storable on a computer readable medium. The program instructions may be executable by a processor to receive a timing report for the IC. For each source clock path and destination clock path of each half-cycle timing path, the... Agent: Mhkkg/sun

20090222781 - Method for designing circuit layout capable of propagating signals synchronously without significant alteration of layout: In a circuit layout design method for designing an integrated circuit having signal lines synchronously propagating signals, delay correction cells having provisional values are inserted into the signal lines extending from respective output drivers to corresponding output pads for a set of signals to be synchronized in the designed original... Agent: Volentine & Whitt PLLC

20090222779 - Methods and apparatuses for generating a random sequence of commands for a semiconductor device: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state... Agent: Dicke, Billig & Czaja

20090222782 - Network analysis with steiner trees: Networks may be analyzed using Steiner trees. In an example embodiment, a method includes acts of receiving, accepting, creating, and analyzing. Data specifying a network is received. Steiner tree parameters are accepted. A Steiner tree model is created on the data specifying the network responsive to the Steiner tree parameters.... Agent: Microsoft Corporation

20090222784 - Design method estimating signal delay time with netlist in light of terminal line in macro, and program: A design method according to an aspect of the present invention includes laying out a plurality of functional blocks of a design circuit based on a first netlist, creating a second netlist by adding a first path information to the first netlist, the first path information corresponding to an inter-block... Agent: Mcginn Intellectual Property Law Group, PLLC

20090222783 - Integrated circuit (ic) design method, system and program product: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high... Agent: Law Office Of Charles W. Peterson, Jr. Fishkill

20090222785 - Method for shape and timing equivalent dimension extraction: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.... Agent: Haynes And Boone, LLPIPSection