Data processing: design and analysis of circuit or semiconductor mask inventions 08/09

20090217215 - Apparatus for giving assistance in analyzing deficiency in rtl-input program and method of doing the same: An apparatus for giving assistance in analyzing deficiency in a RTL-input program, includes a partial RTL creator which creates partial RTL description data containing logic description identical with logic description extracted from successive portions of input RTL description data, and having correspondence in signals identical with the same in the... Agent: Foley And Lardner LLP Suite 500

20090217213 - Reuse of circuit labels for verification of circuit recognition: A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a... Agent: Martine Penilla & Gencarella, LLP

20090217214 - Unidirectional relabeling for subcircuit recognition: A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a... Agent: Martine Penilla & Gencarella, LLP

20090217216 - Carbon nanotube circuits design methodology: A methodology is provided for optimizing circuit parameters of circuits including carbon nanotube transistors. The method comprises mapping (122) selected transistor design parameters (118), based on carbon nanotube process parameters (120) and selected circuit topologies (114), into carbon nanotube physical attributes. A circuit layout is generated (124) from the carbon... Agent: Ingrassia Fisher & Lorenz, P.c. (mot)

20090217217 - Method of correlating silicon stress to device instance parameters for circuit simulation: Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090217218 - Opc simulation model using socs decomposition of edge fragments: A system for estimating image intensity within a window area of a wafer using a SOCS decomposition to determine the horizontal and vertical edge fragments that correspond to objects within the window area. Results of the decomposition are used to access lookup tables that store data related to the contribution... Agent: Christensen, O'connor, Johnson, Kindness, Pllc

20090217219 - Method for designing an integrated circuit: A method for designing an integrated circuit is specified, in which upper and lower limits of dependent component parameters and of environment parameters (3, 4) are determined. The limits of the dependent component parameters are determined in a manner dependent on limits of component fabrication parameters in a worst-case consideration.... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090217220 - Method of designing an electronic device and device thereof: A plurality of sequential nodes in a design file for an electronic device are identified and an effective switching capacitance is determined for a first sequential node of the plurality of sequential nodes based upon statically predicted operation of a first device downstream from the first sequential node. The effective... Agent: Larson Newman Abel & Polansky, LLP

20090217222 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of... Agent: Turocy & Watson, LLP

20090217221 - System and method to optimize semiconductor power by integration of physical design timing and product performance measurements: A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a... Agent: Greenblum & Bernstein, P.L.C

20090217223 - Layout design method of semiconductor integrated circuit: A layout design method of a semiconductor integrated circuit includes degenerating a layout netlist extracted from layout data, comparing the layout netlist after the reduction with a circuit diagram netlist, and creating a layout circuit association table of a layout cell after the reduction and a circuit element. The method... Agent: Mcginn Intellectual Property Law Group, Pllc

20090217224 - Method and system for mask design for double patterning: A method and system for setting up multiple patterning lithographic processing of a pattern in a single layer is disclosed. The multiple patterning lithographic processing comprises a first and second patterning step. In one aspect, a method includes, for at least one process condition, obtaining values for a metric expressing... Agent: Knobbe Martens Olson & Bear LLP

20090217225 - Multi-mode multi-corner clocktree synthesis: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree... Agent: Trellis Intellectual Property Law Group, Pc

20090217226 - Multiple derating factor sets for delay calculation and library generation in multi-corner sta sign-off flow: An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two pairs of off-corners. The approach of the present invention does not add any extra work in cell library... Agent: Lsi Corporation C/o Suiter Swantz Pc Llo

20090217227 - Method and apparatus for parallel processing of semiconductor chip designs: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the... Agent: Wall & Tong, LLP Ibm Corporation

20090217228 - Method of making an integrated circuit using pre-defined interconnect wiring: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or... Agent: Dicke, Billig & Czaja

20090217229 - Wire structures minimizing hostile neighbors and coupling affects: A method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to... Agent: International Business Machines Corporation Richard Lau

20090217230 - Automatic bus routing: Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance between pins and routing layer of the pins. A bus... Agent: Trellis Intellectual Property Law Group, Pc

20090217231 - Integrated circuit design support apparatus, integrated circuit design support method, integrated circuit design support program, and recording medium with said program recorded therein: Provided is an integrated circuit design support apparatus capable of estimating the optimal wiring length and wiring congestion at the stage of implementing a logical design of an integrated circuit, thereby preventing the do-over of the logical design or functional design caused by a wiring delay that is discovered at... Agent: Brundidge & Stanger, P.c.

20090217232 - Logic synthesis of multi-level domino asynchronous pipelines: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to... Agent: Weaver Austin Villeneuve & Sampson LLP

20090217233 - Simulation method and simulation program: A method of simulating an optical intensity distribution on a substrate when a mask pattern formed on the mask is transferred to the substrate through a projection optical system by irradiating an illumination light obliquely on a mask surface of the mask, which comprises setting a phase difference between a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090210831 - Cmos circuit leakage current calculator: This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data... Agent: Ibm Corporation

20090210830 - System and method for estimating test escapes in integrated circuits: A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes... Agent: Texas Instruments Incorporated

20090210832 - Verification of spare latch placement in synthesized macros: A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by... Agent: International Business Machines Corporation Richard Lau

20090210836 - Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs: Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed... Agent: International Business Machines Corporation Richard Lau

20090210834 - Ic chip design modeling using perimeter density to electrical characteristic correlation: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a... Agent: Hoffman Warnick LLC

20090210838 - Interpolation distance for layout desing data correction model: Various implementations of the present invention provide a method of determining is a optical proximity correction process model sufficiently covered the layout design. More particularly, various implementations of the invention provide a method for interpolating between test pattern features relative to layout design features under test.... Agent: Mentor Graphics Corp. Patent Group

20090210835 - Method and apparatus for efficient power region checking of multi-supply voltage microprocessors: A improved method for very-early validation of voltage region physical power distribution networks uses initial floor plan and early power grid data to identify physical power connection problems associated with voltage regions defined in multi-supply voltage microprocessor chip designs. Since all checking algorithms are floor plan-based and do not require... Agent: International Business Machines Corporation Richard Lau

20090210833 - Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors: Method and semiconductor structure to avoid latch-up. Method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when... Agent: Greenblum & Bernstein, P.L.C

20090210837 - Verifying non-deterministic behavior of a design under test: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further... Agent: Greenblum & Bernstein, P.L.C

20090210840 - Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew: A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The... Agent: International Business Machines Corporation Richard Lau

20090210841 - Static timing analysis of template-based asynchronous circuits: Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of... Agent: Mcdermott Will & Emery LLP

20090210839 - Timing closure using multiple timing runs which distribute the frequency of identified fails per timing corner: A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090210842 - Automated method for buffering in a vlsi design: Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins.... Agent: International Business Machines Corporation Richard Lau

20090210843 - Method of automating creation of a clock control distribution network in an integrated circuit floorplan: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture... Agent: International Business Machines Corporation Richard Lau

20090210844 - Systems and methods involving designing integrated circuits: A system comprising, a processor operative to, receive a first input designating a first net segment profile on a first level in an integrated circuit for shielding, determine whether the designated first net segment profile is in electrical communication with other net segment profiles, determine whether the net segment profiles... Agent: Cantor Colburn LLP - IBM Rochester Division

20090210845 - Computer program product, apparatus, and method for inserting components in a hierarchical chip design: Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090210846 - I/o planning with lock and insertion features: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the... Agent: Christopher P Maiorana, PC Lsi Corporation

20090210848 - Logic array devices having complex macro-cell architecture and methods facilitating use of same: Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The... Agent: Tillman Wright, PLLC

20090210847 - Synchronous to asynchronous logic conversion: Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to... Agent: Schwegman, Lundberg & Woessner, P.A.

20090210849 - Accurate parasitics estimation for hierarchical customized vlsi design: Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are... Agent: International Business Machines Corporation Richard Lau

20090210850 - Method for simplifying tie net modeling for router performance: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the... Agent: International Business Machines Corporation Richard Lau

20090210851 - Lithography simulation method and computer program product: A lithography simulation method for simulating a lithography process configured to form a pattern on a wafer in which the pattern corresponds to a pattern of a photomask, the lithography process including disposing the photomask above the wafer, disposing an exposure light source above the photomask, and irradiating the wafer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090204930 - Iphysical design system and method: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20090204932 - Equivalence verification between transaction level models and rtl at the example to processors: A method for formally verifying the equivalence of an architecture description with an implementation description. The method comprises the steps of reading an implementation description, reading an architecture description, demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the... Agent: 24ip Law Group Usa, PLLC

20090204931 - Method and apparatus for processing assertions in assertion-based verification of a logic design: Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by... Agent: MoserIPLaw Group/ Cadence Design Systems Inc.

20090204933 - Single event transient mitigation and measurement in integrated circuits: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating... Agent: Lewis And Roca LLP

20090204934 - Method for compensating length of differential pair and method for calculating compensation length thereof and computer accessible storage media: m

20090204935 - Semiconductor device, design method and structure: A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise... Agent: Haverstock & Owens LLP

20090204936 - Method of performing proximity correction: A method of performing proximity correction of a mask layout is used during the generation of a masking structure for performing a processing step. The masking structure includes at least one opening that is delimited by a sidewall and that exposes an area that is to be processed. The method... Agent: Slater & Matsil, L.L.P.

20090204930 - Iphysical design system and method: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20090204932 - Equivalence verification between transaction level models and rtl at the example to processors: A method for formally verifying the equivalence of an architecture description with an implementation description. The method comprises the steps of reading an implementation description, reading an architecture description, demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the... Agent: 24ip Law Group Usa, PLLC

20090204931 - Method and apparatus for processing assertions in assertion-based verification of a logic design: Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by... Agent: MoserIPLaw Group/ Cadence Design Systems Inc.

20090204933 - Single event transient mitigation and measurement in integrated circuits: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating... Agent: Lewis And Roca LLP

20090204934 - Method for compensating length of differential pair and method for calculating compensation length thereof and computer accessible storage media: m

20090204935 - Semiconductor device, design method and structure: A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise... Agent: Haverstock & Owens LLP

20090204936 - Method of performing proximity correction: A method of performing proximity correction of a mask layout is used during the generation of a masking structure for performing a processing step. The masking structure includes at least one opening that is delimited by a sidewall and that exposes an area that is to be processed. The method... Agent: Slater & Matsil, L.L.P.

20090199136 - Optimization of integrated circuit design and library: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum... Agent: Aka Chan LLP

20090199138 - Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information: A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate... Agent: Mark P. Kahler

20090199139 - Method, system, and computer program product for improved electrical analysis: An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from... Agent: VistaIPLaw Group LLP

20090199137 - System and method for multi-exposure pattern decomposition: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns... Agent: Adeli & Tollen, LLP

20090199142 - Method and apparatus for automatic orientation optimization: Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology.... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090199140 - Method and apparatus for thermal analysis: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments,... Agent: Adeli & Tollen, LLP

20090199141 - Systems and methods for prototyping and testing electrical circuits in near real-time: A system for fabricating, testing, and modifying a prototype of an electrical circuit comprises a materials printer including a holder for positioning a substrate. The materials printer is adapted to receive information describing the prototype and is further adapted to fabricate the prototype on the substrate based on the information.... Agent: Fliesler Meyer LLP

20090199143 - Clock tree synthesis graphical user interface: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a... Agent: Trellis Intellectual Property Law Group, PC

20090199145 - Method for accounting for process variation in the design of integrated circuits: A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.... Agent: VistaIPLaw Group LLP

20090199144 - Method of designing semiconductor integrated circuit having function to adjust delay pass and apparatus for supporting design thereof: A power noise cycle is obtained from a dynamic IR drop analysis and a delay of a delay pass is a multiple of the noise cycle. Thereby, a delay increment and a delay decrement of a power noise amount (delay time×power noise amplitude) received when an internal signal of the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090199146 - System and method for efficient and optimal minimum area retiming: A method for use in electronic design software efficiently and optimally produces minimized or reduced register flip flop area or number of registers/flip flops in a VLSI circuit design without changing circuit timing or functionality. The method dynamically generates constraints; maintains the generated constraints as a regular tree; and incrementally... Agent: Mcandrews Held & Malloy, Ltd

20090199147 - Layout data reduction for use with electronic design automation tools: A system and method which stores a three dimensional physical representation of an electrical circuit such as an integrated circuit design uses a database having a plurality of files to store active trace data and inactive feature data (layout data). The data from each file can be cross mapped with... Agent: Texas Instruments Incorporated

20090199148 - Pattern-producing method for semiconductor device: Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090199149 - Methods and apparatus for layout of multi-layer circuit substrates: Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are proviuded on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second... Agent: Law Office Of James Trosino

20090199150 - Step-walk relaxation method for global optimization of masks: A set of candidate global optima is identified, one of which is a global solution for making a mask for printing a lithographic pattern. A solution space is formed from dominant joint eigenvectors that is constrained for bright and dark areas of the printed pattern. The solution space is mapped... Agent: Harrington & Smith, PC

20090199151 - Electrically driven optical proximity correction: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A... Agent: Hoffman Warnick LLC

20090199153 - Exposure condition setting method and program for setting exposure conditions: There is provided an exposure condition setting method concerning an example of the present invention, the method includes inputting design layout data, extracting a plurality of design patterns having a predetermined dimension from the input design layout data, obtaining a transfer pattern transferred to a transfer target film by exposure... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090199152 - Methods and apparatuses for reducing mura effects in generated patterns: A method for generating a pattern on a workpiece is provided. In one method for generating a pattern on a workpiece, at least two sweeps or exposure fields are calibrated based on at least two different calibration maps. The pattern is generated on the workpiece by exposing the workpiece using... Agent: Harness, Dickey & Pierce, P.L.C