Data processing: design and analysis of circuit or semiconductor mask inventions 07/09

20090193367 - Standard cell including measuring structure: Implementations are presented herein that relate to a standard cell including a measuring structure.... Agent: Infineon Technologies Ag Patent Department

20090193368 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090193370 - bondwire design: A system and method of designing the physical shape of and determining the electromagnetic characteristics of a bondwire in an electrical circuit, comprising the steps of enabling a user to define the position of the bondwire in the electrical circuit layout, defining the position and loop shape of the bondwire... Agent: Fliesler Meyer LLP

20090193371 - Method and devices to assist in determining the feasibility of a computer system: The invention concerns a method and devices for analyzing the feasibility of a computer system composed of subsystems, each having functions. After having determined the functional architecture of the computer system comprising at least one subsystem and at least one function, the characteristics of the functions implemented are imported from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090193369 - Process for design of semiconductor circuits: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into... Agent: Ditthavong Mori & Steiner, P.C.

20090193372 - Design structure for improvement of matching fet currents using a digital to analog converter: A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of... Agent: Robert R. Williams IBM Corporation, Dept. 917

20090193375 - Manufacturing method, manufacturing program and manufacturing system for semiconductor device: The present of the invention provides a method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based... Agent: Sonnenschein Nath & Rosenthal LLP

20090193374 - Method of designing semiconductor integrated circuit device, designing apparatus, and semiconductor integrated circuit device: As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so... Agent: Mcdermott Will & Emery LLP

20090193373 - Multiple voltage threshold timing analysis for a digital integrated circuit: An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an... Agent: Hoffman Warnick LLC

20090193376 - Clock power minimization with regular physical placement of clock repeater components: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to... Agent: Law Office Of Jack V. Musgrove (ibm)

20090193377 - Regular local clock buffer placement and latch clustering by iterative optimization: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to... Agent: Law Office Of Jack V. Musgrove (ibm)

20090193378 - Modifying layout of ic based on function of interconnect and related circuit and design structure: Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable... Agent: Hoffman Warnick LLC

20090193379 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090193380 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090193381 - Power mesh management method: The invention discloses a power mesh management method utilized in an integrated IC. The integrated circuit includes a macro block including at least a macro block power supplying line growing along a first direction. The management method includes: defining a plurality of first power supplying lines located in a metal... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090193383 - Auto-router performing simultaneous placement of signal and return paths: An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20090193382 - Method of making an integrated circuit including simplifying metal shapes: A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of... Agent: Dicke, Billig & Czaja

20090193384 - Shift-enabled reconfigurable device: A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array contains partially or fully populated matrices of switches, where each such matrix of switches is obtained by merging a standard diagonal switch matrix with an array shift... Agent: Mihai Sima

20090193385 - Method of checking and correcting mask pattern: The present invention provides a method of checking and correcting a mask pattern. The method includes inputting a mask pattern, wherein the mask pattern includes at least a segment; inputting a process rule; selecting an edge, which fits in with an orientation model, as a target edge, wherein two ends... Agent: North America Intellectual Property Corporation

20090193386 - Semiconductor cell for photomask data verification and semiconductor chip: A semiconductor cell for photomask data verification is disclosed that is provided in a semiconductor chip having a semiconductor integrated circuit and used for verifying photomask data of the semiconductor chip obtained by performing arithmetic processing on layout data of the semiconductor integrated circuit. The semiconductor cell for photomask data... Agent: Dickstein Shapiro LLP

20090193387 - Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks: A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality... Agent: International Business Machines Corporation Dept. 18g

20090187866 - Electrical parameter extraction for integrated circuit design: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a... Agent: Haynes And Boone, LLPIPSection

20090187867 - Techniques for verifying error detection of a design rule checking runset: A technique for verifying error detection of a design rule checking runset includes assigning first shapes for a first layer of an integrated circuit design to a first cell and assigning second shapes for a second layer of the integrated circuit design to a second cell. Design rule checking is... Agent: Ibm Corporation

20090187869 - Budgeting electromigration-related reliability among metal paths in the design of a circuit: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal... Agent: Texas Instruments Incorporated

20090187868 - Design of integrated circuits less susceptible to degradations in transistors caused due to operational stress: According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and... Agent: Texas Instruments Incorporated

20090187870 - Placement driven routing: A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090187871 - Hierarchical compression for metal one logic layer: A method of increasing hierarchy compression of a metal 1 standard cell layout during optical proximity correction (OPC) is provided. This method can use a context determination defined from the outermost OPC correctable-edge boundaries of a metal 1 standard cell and not extending past outermost OPC correctable edge boundaries of... Agent: Bever, Hoffman & Harms, LLP

20090187872 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090187873 - Signal delay skew reduction system: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method... Agent: David Smith Lsi Corporation

20090187874 - Circuit and circuit design method: A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090187875 - System and method for creating a logical representation of a functional logic system from a physical representation: A system and method for transforming a physical representation of a functional logic system or sub-system to a logical representation of the same functional logic system or sub-system. One embodiment provides a method comprising loading a physical hardware description language (HDL) representation of the system or creating a physical HDL... Agent: Quarles & Brady LLP

20090187877 - Multi-pass, constrained phase assignment for alternating phase-shift lithography: Generating two-tone phase shift photomasks that satisfy lithography and photomask constraints is accomplished using an iterative algorithm which successively identifies violations of the constraints, relaxes or removes constraints, and alters layout polygons associated with the violations, to produce a phase assignment configuration which meets the lithography and photomask constraints or... Agent: Texas Instruments Incorporated

20090187876 - Steiner tree based approach for polygon fracturing: Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater than 90 degrees), including steps of developing a rectilinear partition... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090187878 - Data generation method for semiconductor device, and electron beam exposure system: A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference in shape between an electron beam exposure pattern formed on a substrate through electron beam exposure on the basis of the electron beam exposure... Agent: Staas & Halsey LLP

20090183126 - Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives... Agent: Steptoe & Johnson LLP

20090183128 - Generating test patterns having enhanced coverage of untargeted defects: Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are... Agent: Klarquist Sparkman, LLP

20090183127 - Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information: A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user... Agent: Mark P. Kahler

20090183129 - Method, system, and program product for automated verification of gating logic using formal verification: Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will... Agent: International Business Machines Corporation Richard Lau

20090183130 - System and method for improved hierarchical analysis of electronic circuits: A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.

20090183132 - Semiconductor-device manufacturing method, semiconductor-device manufacturing program and semiconductor-device manufacturing system: Disclosed herein is a semiconductor-device manufacturing method including the steps of: computing a capacitance, a resistance as well as capacitance and resistance variations as quantities generated as a result of changing the physical layout of a semiconductor integrated circuit in a range determined in advance; dividing the physical layout of... Agent: Sonnenschein Nath & Rosenthal LLP

20090183131 - Structure for semiconductor on-chip repair scheme for negative bias temperature instability: Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090183134 - Design structure for identifying and implementing flexible logic block logic for easy engineering changes: A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.... Agent: Greenblum & Bernstein, P.L.C

20090183133 - Tool and method to graphically correlate process and test data with specific chips on a wafer: A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip... Agent: Greenblum & Bernstein, P.L.C

20090183135 - Method and device for identifying and implementing flexible logic block logic for easy engineering changes: A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).... Agent: Greenblum & Bernstein, P.L.C

20090183136 - Structure for a programmable interpolative voltage controlled oscillator with adjustable range: A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090178014 - Heuristic clustering of circuit elements in a circuit design: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090178012 - Methodology for improving device performance prediction from effects of active area corner rounding: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over... Agent: Scully, Scott, Murphy & Presser, P.C.

20090178013 - System for implementing post-silicon ic design changes: An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare... Agent: Smith-hill And Bedell, P.C.

20090178015 - Method and system for reducing turn around time of complicated engineering change orders and asic design reutilization: Reducing turn around time of engineering change orders in ASIC re-spin design includes finding, on the fly, all corresponding boundary points of storage gate elements indicated by engineering change orders to be either added, deleted or renamed. Boolean equivalence tools are used between an old spin ASIC design and a... Agent: Cantor Colburn LLP-ibm Europe

20090178016 - Method for quantifying the manufactoring complexity of electrical designs: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are... Agent: Scully, Scott, Murphy & Presser, P.C.

20090178017 - System and method for i/o synthesis and for assigning i/o to programmable devices: A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin... Agent: Osha Liang L.L.P.

20090178018 - Pre-bias optical proximity correction: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.... Agent: Klarquist Sparkman, LLP

20090172608 - Techniques for selecting spares to implement a design change in an integrated circuit: A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.... Agent: Dillon & Yudell LLP

20090172609 - Jitter amount estimating method, method for calculating correlation between amount of simultaneously operating signal noise and jitter amount, and recording medium: An SSO noise calculating unit estimates the amount of simultaneously operating signal noise caused by simultaneous operations of input/output pins peripheral to a power supply voltage pin as a center. A PLL jitter calculating unit estimates the amount of jitter occurring at the power supply voltage pin by using as... Agent: Staas & Halsey LLP

20090172611 - Method for manufacturing semiconductor device: Manufacturing a semiconductor device by measuring an electrical characteristic of a plurality of semiconductor elements, defining layout parameters on the basis of layout data and deciding a functional relationship between the layout parameters and the electrical characteristic, extracting values of the layout parameters from design layout data of the semiconductor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090172613 - Mutual inductance extraction using dipole approximations: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a... Agent: Klarquist Sparkman, LLP

20090172612 - Static hazard detection device, static hazard detection method, and recording medium: There is provided a check target extraction unit that receives logic circuit information describing a logic circuit, and extracts at least one set of a start point register and an end point register from registers in the logic circuit, the start point register outputting an exception signal to be supplied... Agent: Nec Corporation Of America

20090172610 - System and method for circuit simulation: In a circuit simulation system, a storage section is configured to store a circuit data, an analysis condition data and an output data. An initial data setting section reads out the circuit data and the analysis condition data from the storage section and sets an initial data and a convergence... Agent: Mcginn Intellectual Property Law Group, PLLC

20090172617 - Advisory system for verifying sensitive circuits in chip-design: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and... Agent: Slater & Matsil, L.L.P.

20090172614 - Avoiding device stressing: A system for protecting a weak device operating in micro-electronic circuit and a design structure including the system embodied in a machine readable medium are disclosed. The system includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a... Agent: Scully, Scott, Murphy & Presser, P.C.

20090172615 - Method and apparatus for on-the-fly minimum power state transition: The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first... Agent: Scully, Scott, Murphy & Presser, P.C.

20090172616 - Method, system, and computer program product for implementing a direct measurement model for an electronic circuit design: Various embodiments of the present invention are generally directed to a method, system, and computer program product for implementing direct measurement model with simulation and calibration of manufacturing process model in the manufacturing of precision devices such as electronic integrated circuits. The method and the system determine the measured measurement... Agent: VistaIPLaw Group LLP

20090172618 - Technique for creating analysis model and technique for creating circuit board model: According to a circuit board creation program presented herein, a simulation assuming a case in which an addition of a bypass capacitor near a another bypass capacitor provided between a pin and via of an LSI part can be performed, simply by adding a bypass capacitor property model and changing... Agent: Staas & Halsey LLP

20090172619 - Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis: Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are... Agent: VistaIPLaw Group LLP

20090172621 - System and method for system-on-chip (soc) performance analysis: A system and method of performing transaction level System on Chip (SoC) performance analysis includes obtaining a SoC description file including all intellectual property (IP) modules interconnected in a SoC via interconnects, calculating clock periods of the IP modules, calculating a greatest common divisor (GCD) of all the clock periods,... Agent: Rahman LLC

20090172620 - Timing analyzing apparatus, timing analyzing method, and computer-readable storage medium on which timing analyzing program is recorded: According to one embodiment, a timing analyzing apparatus comprises an instance list creating module configured to create instance lists for each path reports, an instance list report creating module configured to create an instance list report including the instance lists, a maximally appearing instance determining module configured to determine an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090172622 - Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow: An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includes instructions for use by the custom block composition tool to... Agent: Mhkkg/sun

20090172623 - Method and system for implementing efficient locking to facilitate parallel processing of ic designs: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.... Agent: VistaIPLaw Group LLP

20090172624 - Method and system for implementing stacked vias: The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical... Agent: VistaIPLaw Group LLP

20090172625 - Method and mechanism for performing clearance-based zoning: A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with... Agent: VistaIPLaw Group LLP

20090172627 - Design structure for a clock system for a plurality of functional blocks: A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of design partitions of an integrated circuit system to create a clock system that reduces peak power consumption across the... Agent: Downs Rachlin Martin PLLC

20090172626 - Method and system for visual implementation of layout structures for an integrated circuit: The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation could be employed to display a set of layout choices when correcting errors or rules violations identified in the design. Alternatively, the visual... Agent: VistaIPLaw Group LLP

20090172628 - Method and system for utilizing hard and preferred rules for c-routing of electronic designs: An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing.... Agent: VistaIPLaw Group LLP

20090172629 - Validating continuous signal phase matching in high-speed nets routed as differential pairs: Methods and apparatus to validate continuous signal phase matching in high-speed nets routed as differential pairs are described. In one embodiment, a primary net of a differential pair may be traversed to determine whether a design rule violation has occurred based on comparison of calculated trace lengths of the primary... Agent: Caven & Aghevli LLC C/o Cpa Global

20090172630 - Automated processor generation system and method for designing a configurable processor: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that... Agent: Pillsbury Winthrop Shaw Pittman LLP