Data processing: design and analysis of circuit or semiconductor mask inventions 06/09

20090164954 - Automatic antenna designing apparatus and automatic antenna designing method: An automatic antenna designing apparatus for designing a tag antenna of an IC tag, has a model storage unit configured to store models serving as templates of the tag antenna to be designed; and a design input unit configured to read out a model from the model storage unit on... Agent: Katten Muchin Rosenman LLP

20090164953 - Simultaneous optimization of analog design parameters using a cost function of responses: An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation

20090164955 - Method for verifying safety apparatus and safety apparatus verified by the same: A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090164957 - Design structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks: A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090164958 - Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus: Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component σr about a plurality of nodes of the single path is calculated. Next, an on-chip variation component chip is calculated on the basis of the on-chip random... Agent: Buchanan, Ingersoll & Rooney PC

20090164956 - Redistribution of current demand and reduction of power and dcap: A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a... Agent: Christopher P Maiorana, PC Lsi Corporation

20090164959 - Layout design device and layout design method of semiconductor integrated circuit: A layout design device includes a calculation processing portion that calculates a degree of wire congestion of each layer based on a pre-wiring design data to form a desired wiring structure in each layer, a selection processing portion that selects one area from a plurality of areas as a selection... Agent: Mcginn Intellectual Property Law Group, PLLC

20090164960 - Semiconductor integrated circuit design system, semiconductor integrated circuit design method, and computer readable medium: A semiconductor integrated circuit design method has extracting connection-permitted patterns which are permitted to connect to each other in a layout pattern, disconnection-permitted patterns which exercise no effect on a circuit operation even when disconnected in the layout pattern, and a multicut via which suffices when connection is made to... Agent: SprinkleIPLaw Group

20090164961 - Design structure for a system for controlling access to addressable integrated circuits: A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset... Agent: Downs Rachlin Martin PLLC

20090164962 - Method of reducing crosstalk induced noise in circuitry designs: A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel... Agent: Dillon & Yudell LLP

20090164963 - System and method for routing connections: A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing... Agent: Baker Botts L.L.P.

20090164964 - Design structures including integrated circuits for reducing electromigration effect: A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii)... Agent: Schmeiser, Olsen & Watts

20090164967 - High-level synthesis apparatus, high-level synthesis system and high-level synthesis method: A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090164965 - Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or... Agent: Dillon & Yudell LLP Suite 2110

20090164966 - Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or... Agent: Dillon & Yudell LLP Suite 2110

20090164968 - Method and system for implementing top down design and verification of an electronic design: Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same... Agent: VistaIPLaw Group LLP

20090158223 - Adaptive weighting method for layout optimization with multiple priorities: An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (pi) to be multiple of the weight of a lower priority (pi−1) where W(pi)=mi % W(pi−1. To avoid numerical imprecision, this method keeps the total cost in the objective function within a... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090158224 - Design structure including failing address register and compare logic for multi-pass repair of memory arrays: Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the tri-state address bus. The design structure allows for easy, discrete... Agent: Hoffman Warnick LLC

20090158226 - High-density, trench-based non-volatile random access sonos memory cells for soc applications: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with... Agent: Scully, Scott, Murphy & Presser, P.C.

20090158225 - Method and system for automatically accessing internal signals or ports in a design hierarchy: A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090158227 - Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure: Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C∞ and inductances L∞ of coplanar transmission line structures over silicon substrate utilizes field based expressions derived for a single coplanar T-line structures over silicon, and coupled coplanar T lines over... Agent: Scully, Scott, Murphy & Presser, P.C.

20090158228 - Moment computation algorithms in vlsi system: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced.... Agent: Lsi Corporation

20090158229 - Method of area compaction for integrated circuit layout design: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used... Agent: Freescale Semiconductor, Inc. Law Department

20090158230 - Determining allowable antenna area as function of total gate insulator area for soi technology: A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a... Agent: Hoffman Warnick LLC

20090158231 - Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire... Agent: Downs Rachlin Martin PLLC

20090158233 - Automatic design method and computer program thereof: An automatic design method according to the present invention comprises the steps of: grouping rats and tentatively disposed vias by bonding pad groups to be connected, corresponding to the pads that are grouped by four sides of a substrate surface; setting boundary lines to define regions each of which contains... Agent: Staas & Halsey LLP

20090158232 - Circuit arrangements and associated apparatus and methods: There is provided a method comprising: examining the location of one or more feature(s) of the one or more component(s) of a circuit arrangement to determine the displacement of the location of said one or more associated communication contact(s) with respect to a designed location for the communication contact(s), and... Agent: Foley & Lardner LLP

20090158234 - Vertical soi trench sonos cell: A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that... Agent: Scully, Scott, Murphy & Presser, P.C.

20090158235 - Synthesis of electronic circuits: The invention relates to a method of synthesising an electronic circuit for performing a function. The method comprises programming the function using a programming language by defining one or more terms, each term comprising one or more functional constants. Game semantics are applied to interpret the programmed function. Each term... Agent: Goodwin Procter LLP Patent Administrator

20090158236 - Semiconductor device fabrication method and fabrication apparatus using a stencil mask: A semiconductor device fabrication method includes preparing a substrate having a first circuit pattern of a semiconductor device; providing a mask with at least part of second circuit pattern of the semiconductor device; collimating incident direction of particles; changing at least one of the a substrate angle between a vertical... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090150834 - Method of reusing constraints in pcb designs: A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090150835 - technique for generation of load-slew indices for circuit characterization: A method and system for generation of low-slew indices for circuit characterization are disclosed. In one embodiment, a method for automatically generating a subset of sampling points from a set of load and slew points for circuit characterization includes iteratively obtaining sampling points such that error between an actual value... Agent: GlobalIPServices, PLLC

20090150836 - Intelligent pattern signature based on lithography effects: The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it... Agent: VistaIPLaw Group LLP

20090150837 - Checking a circuit layout for a semiconductor apparatus: (d) carrying out a simulation for the at least one circuit part determined in step (c), in order to obtain a simulation result.... Agent: Dickstein Shapiro, LLP

20090150842 - Identifying parasitic diode(s) in an integrated circuit physical design: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction... Agent: Greenblum & Bernstein, P.L.C

20090150839 - Integrated prototyping system for validating an electronic system design: An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The... Agent: Haynes And Boone, LLPIPSection

20090150840 - Method for acquiring basic characteristic of simultaneous switching noise in method for estimating simultaneous switching noise on semiconductor device: In an initial stage of device design, a circuit analysis control unit of an evaluation board stores SSO noise basic characteristic data actually measured by the evaluation board in an SSO noise basic characteristic data storage unit, and an SSO noise calculation unit calculates a rough amount of SSO noise... Agent: Staas & Halsey LLP

20090150838 - Method of progressively prototyping and validating a customer's electronic system design:

20090150841 - Semiconductor integrated circuit design supporting method, semiconductor integrated circuit design supporting system, and computer readable medium: A semiconductor integrated circuit design supporting system has a memory unit which stores cell information containing the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file defining a drive factor of... Agent: Amin, Turocy & Calvin, LLP

20090150844 - Critical path selection for at-speed test: A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090150846 - Intelligent timing analysis and constraint generation gui: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The... Agent: Christopher P Maiorana, PC Lsi Corporation

20090150843 - Method and apparatus for making a semiconductor device using hardware description having merged functional and test logic blocks: A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to... Agent: Freescale Semiconductor, Inc. Law Department

20090150845 - Method for driving current of cell library: Embodiments relate to a cell library for an application specific integrated circuit (ASIC). Embodiments relate to a method for defining current drive capacity of a cell library, which may define an amount of various kinds of drive current in a single pin and driving current in the cell library. According... Agent: Sherr & Vaughn, PLLC

20090150847 - Logic circuit delay optimization: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is... Agent: Martin D. Moynihan D/b/a Prtsi, Inc.

20090150848 - Topologies and methodologies for ams integrated circuit design: A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return... Agent: Ibm Corporation, T.j. Watson Research Center

20090150850 - Method and apparatus for identifying and correcting phase conflicts: One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout. Next, the system removes a first set of edges from the... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090150849 - Methods for measuring mean-to-target (mtt) based on pattern area measurements and methods of correcting photomasks using the same: Methods of measuring a mean-to-target (MTT) based on pattern area measurements are provided including providing a design pattern. A plurality of design pattern measurements are measured for calculating an area of the design pattern based on a shape of the design pattern. A series of calculation measurements are calculated by... Agent: Myers Bigel Sibley & Sajovec

20090144669 - Method and arrangement for enhancing process variability and lifetime reliability through 3d integration: A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090144670 - Automated optimization of device structure during circuit design stage: A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved... Agent: International Business Machines Corporation Dept. 18g

20090144671 - Designing integrated circuits for yield: Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found.... Agent: Cadence Design Systems Sawyer Law Group LLP

20090144672 - Determination of values of physical parameters of one or several components of an electronic circuit or of a microelectro-mechanical system: A method for determining, for each of at least p physical parameters of one or several components of an electronic circuit or of a microelectromechanical system, a number n of experiment values of the physical parameter includes determining n vectors of dimension p, each component of each of the vectors... Agent: HowardIPLaw Group

20090144673 - Partial good schema for integrated circuits having parallel execution units: Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the... Agent: W. Riyon Harding

20090144674 - Timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy: An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two different models of the same circuit block and performing timing analysis... Agent: Texas Instruments Incorporated

20090144675 - Transaction based verification of a system on chip on system level by translating transactions into machine code: In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a... Agent: Williams, Morgan & Amerson

20090144680 - Automated debugging method and system for over-constrained circuit verification environment: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained... Agent: Mcdermott Will & Emery LLP

20090144681 - Automated debugging method and system for over-constrained circuit verification environment: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained... Agent: Mcdermott Will & Emery LLP

20090144677 - Design structure for a circuit and method to measure threshold voltage distributions in sram devices: A design structure for a circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The design structure for the circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically... Agent: Downs Rachlin Martin PLLC

20090144676 - Design verification technique: A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is an impact checker to determine the impact of portions of the design on the operation of the design.... Agent: Ibm Corporation, T.j. Watson Research Center

20090144678 - Method and on-chip control apparatus for enhancing process reliability and process variability through 3d integration: A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method.... Agent: Scully, Scott, Murphy & Presser, P.C.

20090144679 - Staged scenario generation: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of... Agent: Lsi Corporation

20090144683 - Automated debugging method and system for over-constrained circuit verification environment: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained... Agent: Mcdermott Will & Emery LLP

20090144684 - Clock model for formal verification of a digital circuit description: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in... Agent: Trellis Intellectual Property Law Group, PC

20090144682 - Dual path static timing analysis: A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an... Agent: Christopher P Maiorana, PC Lsi Corporation

20090144685 - Double-layer integral using a static green's function and rectangular basis: The present invention a new closed-form double-layer integral for a rectangular basis. It is valid for both self integrals and non-self integrals. In general, the approach of the present invention contains only six (6) terms and is much simpler than indirect closed-form results, which has 24 terms.... Agent: Hoffman Warnick LLC

20090144687 - Layout design method of semiconductor integrated circuit by using soft macro: A layout design method of a semiconductor integrated circuit to be formed in an integrated circuit (IC) chip is provided. The layout design method includes reading a netlist and a soft macro. The soft macro includes: relative position information describing relative positions of a plurality of relative arrangement position determined... Agent: Foley And Lardner LLP Suite 500

20090144686 - Method and apparatus for monitoring marginal layout design rules: A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology... Agent: Scott F. Diring Williams, Morgan & Amerson, P.C.

20090144688 - Systems and methods for probabilistic interconnect planning: Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability... Agent: Law Offices Of Mark L. Berrier

20090144689 - Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal: A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages.... Agent: Downs Rachlin Martin PLLC

20090144690 - System and method for converting software to a register transfer (rtl) design: A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory... Agent: Ratnerprestia

20090144691 - Enhanced process yield using a hot-spot library: The invention provides apparatus and methods for processing substrates using a hot-spot library.... Agent: Tokyo Electron U.s. Holdings, Inc.

20090144692 - Method and apparatus for monitoring optical proximity correction performance: A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data... Agent: Scott F. Diring Williams, Morgan & Amerson, P.C.

20090144693 - Exposure data generator and method thereof: An exposure data generator for generating exposure data representing graphical information of a pattern to be exposed and a computer-readable recording medium are provided. The generator includes a storage device for storing pre-correction exposure data which include information on positions and sizes of patterns placed within an target region and... Agent: Staas & Halsey LLP