|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor mask May archived by USPTO category 05/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/28/2009 > patent applications in patent subcategories. archived by USPTO category
20090138832 - Implementing enhanced wiring capability for electronic laminate packages: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit... Agent: Ibm Corporation RochesterIPLaw Dept 917
20090138833 - Method, apparatus and computer program for facilitating the improvement of a user interface: There is disclosed a method, apparatus and computer program for facilitating improvement of a user interface. A plurality of critical paths though the user interface are determined. A complexity of each of the critical paths is calculated. The complexity of the critical paths relative to a level of criticality of... Agent: Hoffman Warnick LLC
20090138835 - Identifying layout regions susceptible to fabrication issues by using range patterns: A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside... Agent: Silicon Valley Patent Group LLP Attn: Syn
20090138834 - Structure for a duty cycle measurement circuit: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090138836 - Automatic verification of adequate conductive return-current paths: After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090138838 - Method and apparatus for supporting delay analysis, and computer product: A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that... Agent: Greer, Burns & Crain
20090138839 - Method, apparatus and program for designing circuits: A circuit designing method for a semiconductor integrated circuit, the circuit having a clock control circuit and leaves to which clock signals are propagated through the clock control circuit, has detecting a clock signal producing point where a clock signal is to be produced and an operational mode setting point... Agent: Amin, Turocy & Calvin, LLP
20090138837 - System and method for sequential equivalence checking for asynchronous verification: A system and method for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090138840 - Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which... Agent: Mcdermott Will & Emery LLP
20090138841 - System and apparatus for in-system programming: Embodiments of the present invention relate to machines that perform in-system programming of programmable devices that are attached to assembled printed circuit boards. In accordance with one aspect, multiple nonvolatile devices may be programmed in a single session at their normal maximum programming speeds. Different nonvolatile devices on a board... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20090138842 - Behavioral synthesis system, behavioral synthesis method, and behavioral synthesis program: A behavioral synthesis system has a scheduling unit and a mode control unit. The scheduling unit performs scheduling of a behavioral level description with reference to a resource quantity data indicating resource constraint and a resource delay data indicating delay times of respective resources. A single process described in the... Agent: Sughrue Mion, PLLC05/21/2009 > patent applications in patent subcategories. archived by USPTO category
20090132970 - method for incremental, timing-driven, physical-synthesis optimization under a linear delay model: A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net... Agent: Dillon & Yudell LLP
20090132971 - Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler: A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090132974 - method for semiconductor circuit: Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat... Agent: Miles & Stockbridge PC
20090132973 - Design structure of an integration circuit and test method of the integrated circuit: A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and which is connected to the first... Agent: International Business Machines Corporation Dept. 18g
20090132972 - Method and apparatus for determining electro-migration in integrated circuit designs: A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level... Agent: Texas Instruments Incorporated
20090132975 - Circuit splitting in analysis of circuits at transistor level: Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed.... Agent: Fish & Richardson, PC
20090132979 - Dynamic pointer dereferencing and conversion to static hardware: Disclosed herein are embodiments of methods and apparatus for handling dynamic pointers during algorithmic synthesis. In one disclosed embodiment, a high-level description of a circuit design (e.g., C++ description or a parsed C++ description) is received. In this embodiment, the high-level description comprises one or more dynamic pointer dereferencing operations.... Agent: Klarquist Sparkman, LLP
20090132978 - Method for automatically modifying frame of circuit diagram: A method for automatically modifying a frame of a circuit diagram is applicable for a computer-executable circuit layout software, which determines intersection or discontinuity of line segments generated after a diagram is converted through using a program, and automatically corrects the diagram to output a complete circuit diagram, so as... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090132976 - Method for testing an integrated circuit and analyzing test data: A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of... Agent: Schmeiser, Olsen & Watts
20090132977 - Method of establishing coupon bar: A method of establishing a coupon bar is applied to circuit layout of a multi-layer printed circuit board (PCB). A coupon bar library storing a great number of coupon bars and sets of setting parameters each corresponding to a coupon bar is connected. A set of parameters including a layer... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090132980 - Range pattern definition of susceptibility of layout regions to fabrication issues: A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at... Agent: Silicon Valley Patent Group LLP Attn: Syn
20090132983 - Driving values to dc adjusted/untimed nets to identify timing problems: An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090132981 - Method for incremental, timing-driven, physical-synthesis using discrete optimization: A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one... Agent: Dillon & Yudell LLP
20090132982 - Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes: A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases... Agent: International Business Machines Corporation Dept. 18g
20090132984 - Optimal flow in designing a circuit operable in multiple timing modes: A design approach provided according to an aspect of the present invention consolidates the constraint files of respective modes into consolidated information and performs place-and-route using such consolidated information. The resource requirements may be reduced as result. Another aspect of the present invention provides a programmatic approach to consolidating timing... Agent: Texas Instruments Incorporated
20090132985 - Design structure for on-chip electromigration monitoring system: A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to... Agent: International Business Machines Corporation Dept. 18g
20090132986 - Circuit design assisting apparatus, method, and program: A circuit design assisting apparatus for assisting a layout tool in designing an integrated circuit that includes a circuit module having plural cells achieving a prescribed function. A cell connection information acquiring device is provided to acquire cell connection information that specifies connection counterparts to the plural cells and is... Agent: Dickstein Shapiro LLP
20090132987 - Method and system for the modular design and layout of integrated circuits: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width... Agent: Imperium Patent Works
20090132988 - Power mesh arrangement method utilized in an integrated circuit having multiple power domains: The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second partial local power mesh according to a position of a... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090132989 - Method of determining minimum cost path: A network is represented using a graph. The graph comprises a plurality of vertices and a plurality of edges. The vertices comprise a source vertex, a destination vertex and a vertex u. The edges link corresponding adjacent pairs of the vertices. A minimum cost path in the graph is determined... Agent: At&t Legal Department - Lnap Attn: Patent Docketing
20090132990 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20090132991 - Partial order reduction for scalable testing in system level design: A system and method for program testing includes, using a static analysis, determining dependency relations of enabled running processes in a program. The dependency relations are organized in a matrix to provide an interface for exploring the program. A reduced set of possible executions obtained by removal of redundant interleavings... Agent: Nec Laboratories America, Inc.
20090132992 - Statistical optical proximity correction: An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.... Agent: HorizonIPPte Ltd05/14/2009 > patent applications in patent subcategories. archived by USPTO category
20090125851 - Nonlinear driver model for multi-driver systems: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used... Agent: Bever, Hoffman & Harms, LLP
20090125854 - Automated generation of theoretical performance analysis based upon workload and design configuration: A method of more efficiently, easily and cost-effectively analyzing the performance of a device model is disclosed. Embodiments enable automated generation of theoretical performance analysis for a device model based upon a workload associated with rendering graphical data and a configuration of the device model. The workload may be independent... Agent: Murabito Hao & Barnes LLP
20090125853 - Circuit structure of integrated circuit: A circuit structure of an integrated circuit is provided. The circuit structure is adapted for a circuit layout of a wafer. The circuit structure at least includes a first array cell and a second array cell. The second array cell and the first array cell are connected to each other... Agent: Jianq Chyun Intellectual Property Office
20090125852 - Method and apparatus for net-aware critical area extraction: In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, the net comprising a plurality of interconnected... Agent: Patterson & Sheridan, LLP
20090125855 - Forming separation directives using a printing feasibility analysis: Separation directives for integrated circuit layout design data are formed based upon one or more printing feasibility analyses performed on the layout design data. At least one printing feasibility analysis is performed on layout design data to identify portions of the design that may not be correctly formed or “printed”... Agent: Mentor Graphics Corp. Patent Group
20090125856 - Methods and apparatus for boolean equivalency checking in the presence of voting logic: In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of... Agent: Ibm Corporation, Intellectual Property Law
20090125857 - Design structure for an absolute duty cycle measurement circuit: A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090125858 - Ic design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis: An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which the output of a cell is expected to switch, and performing timing analysis based on the selected values. By using appropriate smaller sub-intervals within the timing window,... Agent: Texas Instruments Incorporated
20090125859 - Methods for optimal timing-driven cloning under linear delay model: A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and... Agent: Ibm Corporation (jvm)
20090125860 - Auto-routing small jog eliminator: In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined.... Agent: Robert R. Williams IBM Corporation, Dept. 917
20090125861 - Wiring design processing method and wiring design processing apparatus: A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical... Agent: Staas & Halsey LLP
20090125862 - Wiring path information creating method and wiring path information creating apparatus: A wiring processing apparatus decides each group formed by sorting signals that flow between component pins. Then, the wiring processing apparatus reads printed circuit board data and identifies a net cluster that belongs to each group. After a net cluster that belongs to each group is identified, the wiring processing... Agent: Staas & Halsey LLP
20090125869 - Calculation system for inverse masks: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20090125867 - Handling of flat data for phase processing including growing shapes within bins to identify clusters: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the... Agent: Bever Hoffman & Harms, LLP
20090125866 - Method for performing pattern decomposition for a full chip design: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for... Agent: Pillsbury Winthrop Shaw Pittman LLP
20090125868 - Multilayer opc for design aware manufacturing: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper... Agent: International Business Machines Corporation Dept. 18g
20090125864 - System and method for making photomasks: The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity... Agent: Texas Instruments Incorporated
20090125865 - System and method for making photomasks: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the... Agent: Texas Instruments Incorporated
20090125863 - Treatment of trim photomask data for alternating phase shift lithography: In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating initial phase photomask data and initial trim photomask data from a first set of data from a first drawn layer and/or layout and a second set of data from a second... Agent: Texas Instruments Incorporated
20090125870 - System and method for making photomasks: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database, the drawn pattern data describing device circuit features and dummy features. The dummy features have first target patterns. Mask pattern data is generated for the dummy features, wherein... Agent: Texas Instruments Incorporated
20090125871 - System and method for making photomasks: The present disclosure is directed a method for, preparing a photomask pattern. The method comprises receiving drawn pattern data from a design database. The drawn pattern data describes two or more adjacent feature ends that are positioned at different locations along a y-axis. A photomask pattern is formed for patterning... Agent: Texas Instruments Incorporated05/07/2009 > patent applications in patent subcategories. archived by USPTO category
20090119621 - Variability-aware asynchronous scheme for optimal-performance delay matching: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing... Agent: Stattler-suh PC
20090119622 - Variability-aware asynchronous scheme based on two-phase protocols: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing... Agent: Stattler-suh PC
20090119623 - Method of labelling swappable pins for integrated circuit pattern matching: The present invention seeks to provide a simple, but novel regime, for re-labelling swappable pins that permits swappability information to be maintained without significantly increasing computational complexity and is conducive to inexact pattern matching for the purposes of developing more complex logical processing blocks from elementary components in design analysis.... Agent: The Nath Law Group
20090119625 - structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit: A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include... Agent: Downs Rachlin Martin PLLC
20090119624 - Apparatus and method for analyzing source code using path analysis and boolean satisfiability: A computer readable storage medium includes executable instructions to identify a path in target source code. Constraints associated with the path are extracted. The constraints are converted to a Boolean expression. The Boolean expression is processed with a Boolean satisfiability engine to identify either a feasible path or an infeasible... Agent: Cooley Godward Kronish LLP Attn: Patent Group
20090119626 - Design structure including transistor having gate and body in direct self-aligned contact: A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a... Agent: Hoffman Warnick LLC
20090119628 - Methods, systems and user interface for evaluating product designs in light of promulgated standards: Systems, methods, and interfaces for evaluating proposed product designs having interconnected devices in light of promulgated industry standards via a graphical interface.... Agent: Armstrong Teasdale LLP (16463)
20090119627 - Pattern data generation method, design layout generating method, and pattern data verifying program: A pattern data generation method according to an example of the present invention includes based on design pattern data of a circuit including a plurality of MIS transistors having the same gate size, identifying types of the plurality of MIS transistors, setting size specs for gate patterns of the plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090119630 - Arrangements for developing integrated circuit designs: In some embodiments, a method is disclosed for converging on an acceptable integrated circuit design for an integrated circuit. The method can include selecting a path, determining if the path has a timing deficiency, segmenting the path into path segments and allocating the timing deficiency across the segments according to... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC
20090119629 - System and method for generating at-speed structural tests to improve process and environmental parameter space coverage: A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so... Agent: Downs Rachlin Martin PLLC
20090119631 - Variability-aware asynchronous scheme for high-performance delay matching: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing... Agent: Stattler-suh PC
20090119632 - Method for supporting determination of design process order: A system and method which support determination of a design process order. The system includes: a storage device that stores constraint data indicating a strength of a constraint that is given to a respective design process from a respective of the other design processes; a detection unit that accesses the... Agent: Ibm Corporation, T.j. Watson Research Center
20090119633 - Cad apparatus and program used in the same: A CAD apparatus is comprised of: input unit 102A for inputting design input information of the component model by a CAD operator; sequence information storage unit 105A for previously storing thereinto sequence information corresponding to information produced by dividing all of designing processes related to the component model and by... Agent: Sughrue-265550
20090119634 - Method and system for implementing controlled breaks between features using sub-resolution assist features: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or... Agent: VistaIPLaw Group LLP
20090119635 - Mask pattern correction method for manufacture of semiconductor integrated circuit device: Mask data is generated from a design layout by executing a mask data process including optical proximity correction. A pattern is formed on the major surface of a test semiconductor substrate by using a mask prepared from the mask data. The dimensional difference between the design layout and the pattern... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLPPrevious industry: Data processing: presentation processing of document
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