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Data processing: design and analysis of circuit or semiconductor mask April category listing, related patent applications 04/09

20090113356 - Optimization of post-layout arrays of cells for accelerated transistor level simulation: A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are... Agent: Silicon Valley Patent Group LLP Attn: Syn

20090113358 - Mechanism for detection and compensation of nbti induced threshold degradation: The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090113360 - Method for computing the sensistivity of a vlsi design to both random and systematic defects using a critical area analysis tool: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090113359 - Model based microdevice design layout correction: Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault.... Agent: Mentor Graphics Corp. Patent Group

20090113357 - Monitoring ionizing radiation in silicon-on insulator integrated circuits: A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon... Agent: Schmeiser, Olsen & Watts

20090113364 - Apparatus and computer program product for semiconductor yield estimation: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.... Agent: Greenblum & Bernstein, P.L.C

20090113361 - Design structure for an automated real-time frequency band selection circuit for use with a voltage controlled oscillator: A design structure for an integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes... Agent: Downs Rachlin Martin PLLC

20090113363 - Method and system for creating a boolean model of multi-path and multi-strength signals for verification: A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL... Agent: VistaIPLaw Group LLP

20090113362 - Method for designing a mask for an integrated circuit having separate testing of design rules for different regions of a mask plane: The invention relates to a method for designing integrated circuits, in particular a description and verification of design rules, wherein in one and the same process layer different design rules (6, 7) should be valid, for instance for a metallization layer for forming conductive lines in a high voltage smart... Agent: Hunton & Williams LLP Intellectual Property Department

20090113365 - Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof: The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic,... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090113366 - Method and mechanism for performing timing aware via insertion: A method and system to insert redundant vias while preserving timing is disclosed. The system and method preserve the timing during redundant via insertion, which utilizes incremental timing and extraction updates. A budgeting based approach and a path based approach to the method are disclosed. The budgeting approach is faster,... Agent: VistaIPLaw Group LLP

20090113367 - Analog ic placement using symmetry-islands: A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) representation of a trial placement wherein each symmetry group and each... Agent: Smith-hill And Bedell, P.C.

20090113368 - Filler cells for design optimization in a place-and-route system: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090113370 - Layout designing method for semiconductor device and layout design supporting apparatus for the same: In a layout designing method of a semiconductor device, a first standard cell with a first well and a second standard cell with a second well are arranged. The first well and the second well are applied with different voltages, respectively. An empty cell is arranged in an area that... Agent: Foley And Lardner LLP Suite 500

20090113369 - Registry for electronic design automation of integrated circuits: A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application;... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20090113372 - Interconnect routing methods of integrated circuit designs: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing... Agent: Cadence Design Systems C/o Alford Law Group, Inc.

20090113371 - Routing interconnect of integrated circuit designs: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing... Agent: Cadence Design Systems C/o Alford Law Group, Inc.

20090113373 - Layout design apparatus, layout design method, and computer product: A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and... Agent: Staas & Halsey LLP

20090113374 - Method for designing semiconductor device layout and layout design supporting apparatus: In a layout design method for a semiconductor device having a hard macro, a netlist data of the semiconductor device and a hard macro data are read out from a storage section. An arrangement position of the hard macro is determined from the netlist data and the hard macro data,... Agent: Mcginn Intellectual Property Law Group, PLLC

20090113375 - Methods, media, and means for forming asynchronous logic networks: Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the... Agent: Wilmerhale/columbia University

20090113376 - Apparatus for opc automation and method for fabricating semiconductor device using the same: An OPC automation apparatus and manufacturing method of a semiconductor device using the same, being capable of improving the fabrication yield of a semiconductor device by establishing a system and an OPC automation apparatus in which an engineer computer and a work station are connected to one database such that... Agent: Marshall, Gerstein & Borun LLP

20090106707 - Multiple source-single drain field effect semiconductor device and circuit: Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090106708 - Structure for reduced area active above-ground and below-supply noise suppression circuits: A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090106710 - Method and apparatus for synthesis: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has... Agent: Adeli & Tollen, LLP

20090106711 - Method for optimizing of pipeline structure placement: Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The... Agent: International Business Machines Corporation

20090106709 - System for improving a logic circuit and associated methods: A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of... Agent: International Business Machines Corporation

20090106713 - Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes active circuitry on a substrate, a bond pad carried by the substrate, and a shielding structure disposed between the substrate and the bond pad. The shielding structure includes a plurality of... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090106712 - Reliability evaluation and system fail warning methods using on chip parametric monitors: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can... Agent: Greenblum & Bernstein, P.L.C

20090106714 - Methods and system for analysis and management of parametric yield: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution... Agent: Scully, Scott, Murphy & Presser, P.C.

20090106715 - Programmable design rule checking: An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For... Agent: Mentor Graphics Corp. Patent Group

20090106716 - Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers: A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated... Agent: Rutan & Tucker, LLP.

20090106718 - Delay adjusting method and lsi that uses air-gap wiring: Provided is a method for manufacturing a semiconductor integrated circuit device which enables a timing optimization without giving additions to a manufacturing process and increasing cost and TAT. Existence of a timing constraint violation is determined, and when a timing constraint violation is detected, to dissolve the violation, a void... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090106722 - Design automation method and system for assessing timing based on gaussian slack: An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090106719 - Method and system for asynchronous chip design: A method of designing an asynchronous integrated circuit is provided. A global clock network of a synchronous circuit is replaced with a plurality of handshaking circuits. Data validity is encoded into a communication path between a first pipeline stage and a second pipeline stage of the synchronous circuit. A control... Agent: Foley & Lardner LLP

20090106721 - Method of designing semiconductor integrated circuit in which fault detection can be effected through scan-in and scan-out: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of... Agent: Mcdermott Will & Emery LLP

20090106717 - Multithreaded static timing analysis: A method and apparatus for executing multithreaded algorithm to provide static timing analysis of a chip design includes analyzing a chip design to identify various components and nodes associated with the components. A node tree is built with a plurality of nodes. The node tree identifies groups of nodes that... Agent: Martine Penilla & Gencarella, LLP

20090106720 - Timing analysis apparatus and method for semiconductor integrated circuit in consideration of power supply and ground noises: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power... Agent: Nixon & Vanderhye P. C.

20090106723 - Semiconductor device metal programmable pooling and dies: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a... Agent: Klein, O'neill & Singh, LLP

20090106724 - Transition balancing for noise reduction/di/dt reduction during design, synthesis, and physical design: An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090106725 - Method and apparatus for computing dummy feature density for chemical-mechanical polishing: One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090106726 - Design structures including means for lateral current carrying capability improvement in semiconductor devices: A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to... Agent: Schmeiser, Olsen & Watts

20090106727 - Methods and systems for layout and routing using alternating aperture phase shift masks: A method of laying out features for alternating aperture phase shift masks. The method includes defining features on a grid of a uniform basic pitch, orienting the features such that those of the features defined, at least in part, by phase shifting shapes are oriented along a primary direction, and... Agent: Greenblum & Bernstein, P.L.C

20090106728 - Routing methods for integrated circuit designs: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing... Agent: Cadence Design Systems C/o Alford Law Group, Inc.

20090100386 - Ic layout optimization to improve yield: Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods... Agent: W. Riyon Harding

20090100385 - Optimal simplification of constraint-based testbenches: Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the... Agent: The Brevetto Law Group, PLLC

20090100387 - Hdl processing method and computer-readable storage medium: A Hardware Description Language (HDL) processing method is implemented in a computer and processes a HDL file which is written in HDL having a hierarchical structure including three or more hierarchical levels in a Computer-Aided Design (CAD) which supports hardware design. The HDL processing method analyzes the hierarchical structure of... Agent: Staas & Halsey LLP

20090100388 - Deep trench capacitor and method of making same: A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of... Agent: Schmeiser, Olsen & Watts

20090100390 - Low depth circuit design: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f′n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.

20090100391 - Overlay measurement on double patterning substrate: A method of measuring overlay between a first structure and a second structure on a substrate is provided. The structures include equidistant elements, such as parallel lines, wherein the equidistant elements of the first and second structure alternate. A design width CD1 of the elements of the first structure is... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090100392 - Securing authenticity of integrated circuit chip: A system and method are provided for securely manufacturing a device at a foundry. For example, an integrated circuit chip may be securely fabricated at an untrusted foundry by later verifying authenticity of the integrated circuit chip based on a valid usage of an original source code file associated with... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090100389 - Shape-based photolithographic model calibration: A method and apparatus for determining how well a photolithographic model simulates a photolithographic printing process. A test pattern of features is printed on a wafer and the shape of the printed features is compared with the shape of simulated features produced by the model. A cost function is calculated... Agent: Klarquist Sparkman, LLP

20090100393 - Method and apparatus for incrementally computing criticality and yield gradient: In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slack for the circuit, determining a slack of at... Agent: Patterson & Sheridan LLP IBM Corporation

20090100394 - Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process: In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a... Agent: International Business Machines Corporation

20090100395 - Method, apparatus, and computer program product for stale ndr detection: Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type... Agent: International Business Machines Corporation

20090100396 - Methods and systems for process compensation technique acceleration: Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout... Agent: Martine Penilla & Gencarella, LLP

20090100397 - Buffer placement with respect to data flow direction and placement area geometry in hierarchical vls designs: A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical... Agent: International Business Machines Corporation

20090100398 - Structure for performing iterative synthesis of an integrated circuit design to attain power closure: A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from... Agent: Hoffman Warnick LLC

20090100399 - Design structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks: A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions... Agent: Greenblum & Bernstein, P.L.C

20090100400 - Phase-shifting masks with sub-wavelength diffractive optical elements: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the... Agent: Intel Corporation C/o Cpa Global

20090094563 - Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms: A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satisfiability solver operations with respect to said initial... Agent: Dillon & Yudell LLP

20090094565 - Method and device for selectively adding timing margin in an integrated circuit: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed”... Agent: Greenblum & Bernstein, P.L.C

20090094564 - Method for rapid return path tracing: A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the structure. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090094566 - Design structure for chip identification system: Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090094567 - Immunity to charging damage in silicon-on-insulator devices: Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090094569 - Test pattern evaluation method and test pattern evaluation device: Provided are an evaluation method and device of a test pattern which enable an appropriate evaluation in a reliability test with a simulation time reduced and high accuracy. It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value... Agent: Nixon & Vanderhye, PC

20090094568 - Validation of an integrated circuit for electro static discharge compliance: An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an... Agent: Texas Instruments Incorporated

20090094570 - Configurable asic-based sensing circuit: A sensing circuit based on an application-specific integrated circuit (ASIC) sensor which includes a sensor portion and a processor portion which are integrated on an ASIC. The sensor portion outputs raw output in response to a stimulus. The output of the sensor portion is processed by the processor portion. The... Agent: Martin D. Moynihan D/b/a Prtsi, Inc.

20090094571 - Method and system for outputting a sequence of commands and data described by a flowchart: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of... Agent: Lsi Corporation

20090089735 - Method and apparatus for routing: In some embodiments, the routing method identifies a route for a net by performing one or more path search operations, where each path search operation identifies one set of path expansions that can be used to define a segment of a route for the net. A path search operation in... Agent: Adeli & Tollen, LLP

20090089736 - Facilitating process model accuracy by modeling mask corner rounding effects: An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP