Data processing: design and analysis of circuit or semiconductor mask inventions 03/09

20090083679 - Efficient second harmonic generation (shg) laser design: A method, a data processing method, and a computer program product for the design of efficient second harmonic generation semiconductor lasers is disclosed. A method for determining an optimum laser configuration includes the determination of a conversion efficiency curve for each SHG configuration using a target conversion efficiency. Each curve,... Agent: Slater & Matsil, L.L.P.

20090083680 - Model-building optimization: A method and system for performing multi-objective optimization of a multi-parameter design having several variables and performance metrics. The optimization objectives include the performance values of surrogate models of the performance metrics and the uncertainty in the surrogate models. The uncertainty is always maximized while the performance metrics can be... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090083681 - Methods and apparatuses for designing integrated circuits using virtual cells: Methods and apparatuses for analyzing and/or designing integrated circuits using virtual transparent cells disclosed. Some embodiments comprise calculating model values for virtual transparent cells or elements of an integrated circuit design varying a transparency variable in modeling equations, and allowing replacement of the cell with a wire based upon the... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC

20090083683 - Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system: Method and apparatus for implementing communication between a software side and a hardware side of a test bench in a transaction-based acceleration verification system are described. In one example, transactors and communication channels are identified in a hierarchy of the test bench. Software side endpoints of the communication channels are... Agent: MoserIPLaw Group/ Cadence Design Systems Inc.

20090083682 - Simulation apparatus and control method of simulation: A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090083685 - Method for generating optimized constraint systems for retimable digital designs: A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits... Agent: Glenn Patent Group

20090083684 - Method for violating the logical function and timing behavior of a digital circuit decision: The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing (10) a VHDL description of the digital circuit design, performing (12) a logic synthesis, wherein the VHDL... Agent: Duke W. Yee Yee & Associates, P.C.

20090083687 - Printed circuit board design support method and apparatus: A method used for supporting designing of a printed circuit board including a plurality of conductive layers having conductive areas to which a constant potential is applied, includes specifying conductive areas having a predetermined wiring from the conductive areas for each of the plurality of conductive layers, extracting areas that... Agent: Canon U.s.a. Inc. Intellectual Property Division

20090083686 - Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential: Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of... Agent: SprinkleIPLaw Group

20090083688 - Method and apparatus for generating a layout for a transistor: A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090083689 - Gridded-router based wiring on a non-gridded library: A computerized method for automatically generating a grid-based derivative of a non-gridded cell library of an integrated circuit design comprises the step of determining at least one valid position of at least one wiring element of a circuit of the first cell library, wherein the at least one valid position... Agent: International Business Machines Corporation Dept. 18g

20090083690 - System for and method of integrating test structures into an integrated circuit: A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into an IC design which... Agent: W. Riyon Harding International Business Machines Corporation

20090083691 - Systems and techniques for developing high-speed standard cell libraries: A method for providing a high-speed cell library is provided. The method can include, for example, selecting a set of commonly-occurring logic functions. The method can then include obtaining a netlist of area distributions for each of the set of functions. The netlist can be used to synthesize a set... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090083692 - Flash-based anti-aliasing techniques for high-accuracy high efficiency mask synthesis: One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF)... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090083693 - Flash-based updating techniques for high-accuracy high efficiency mask synthesis: Another embodiment of the present invention provides a system that computes the effect of perturbations to an input pattern layout during an OPC (Optical Proximity Correction) process. During operation, the system receives a pattern layout. The system further receives a set of lithography model kernels. The system then obtains a... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090077505 - Generalized constraint collection management method: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20090077506 - Simultaneous multi-layer fill generation: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After... Agent: Mentor Graphics Corp. Patent Group

20090077508 - Accelerated life testing of semiconductor chips: Improved techniques for accelerated life testing of a sample of semiconductor chips advantageously enable more effective testing and better estimation of lifetime. Full-chip temperature maps are computed at sets of operating and testing conditions. Evaluating the temperature maps enables operations such as: temperature-aware design changes, including adding and/or configuring heating... Agent: Walstein Bennett Smith Iii

20090077509 - Method for controlling sheet resistance of poly in fabrication of semiconductor device: A method for controlling the sheet resistance of poly in the fabrication of a semiconductor device. In one example embodiment, a method for controlling the sheet resistance of a poly in the fabrication of a semiconductor device includes various steps. First, detection is made whether or not an N-ion implantation... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090077507 - Method of generating technology file for integrated circuit design tools: A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based... Agent: Slater & Matsil, L.L.P.

20090077513 - Generalized constraint collection management method: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20090077511 - Generating constraints in a class model: A method of generating code from a class model for a modeled system. The class model specifies a plurality of elements of a modeling language and dependencies between elements of a plurality of elements. In operations the method analyzes the class model to identify a first possible source of under-specification... Agent: Ibm Corporation (swp)

20090077512 - Matching device: A matching device includes a first storing unit, a second storing unit, and a semiconductor device. The semiconductor device includes a control unit and a circuit unit. In the circuit unit, a first circuit including distance calculating circuits that calculate distances between unknown characters and dictionary characters and a selecting... Agent: Cooper & Dunham, LLP

20090077510 - Rules and directives for validating correct data used in the design of semiconductor products: A method to validate data used in a design of a semiconductor product currently in a partially fabricated state is disclosed. The partially fabricated state having a plurality of layers up to and including a first conductive layer. The method generally includes the steps of (A) adding a second conductive... Agent: Christopher P Maiorana, PC Lsi Corporation

20090077514 - Area and power saving standard cell methodology: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by... Agent: Klein, O'neill & Singh, LLP

20090077515 - Method of constrained aggressor set selection for crosstalk induced noise: A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of... Agent: International Business Machines Corporation Dept. 18g

20090077516 - Semiconductor integrated device and apparatus for designing the same: The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground... Agent: Muirhead And Saturnelli, LLC

20090077517 - Semiconductor intergrated device and apparatus for designing the same: The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground... Agent: Muirhead And Saturnelli, LLC

20090077518 - Derived level recognition in a layout editor: A computer program product stored on machine readable media includes machine executable instructions for displaying a layout of a circuit design, the product including instructions for: over a plurality of layers within a design, identifying at least one of a derived level and a device defined within the plurality; and... Agent: Cantor Colburn LLP - IBM Rochester Division

20090077519 - Displacement aware optical proximity correction for microcircuit layout designs: Techniques for adjusting edge segments within a layout design such that fewer iterations of an optical proximity correction process are required for covergence are provided. With various implementations, multiple iterations of an optical proximity correction process are performed on a portion of a layout design. The final displacement of various... Agent: Mentor Graphics Corp. Patent Group

20090077522 - Method and apparatus for routing with independent goals on different layers: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method... Agent: Adeli & Tollen, LLP

20090077520 - Method and system for representing manufacturing and lithography information for ic routing: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.... Agent: VistaIPLaw Group LLP

20090077521 - Method and system for representing manufacturing and lithography information for ic routing: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.... Agent: VistaIPLaw Group LLP

20090077523 - Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages: Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry... Agent: Martine Penilla & Gencarella, LLP

20090077524 - Method of manufacturing photomask: A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level different for each mask layout, product, and mask layer is relatively recognized with a mask manufacturing load index calculated by a mask manufacturing load prediction... Agent: Miles & Stockbridge PC

20090077529 - Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090077530 - Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090077528 - Pattern correction method, pattern correction system, mask manufacturing method, semiconductor device manufacturing method, recording medium, and designed pattern: A semiconductor device having a physical pattern based on a designed pattern is provided. The designed pattern includes a target pattern and a correction pattern. The target pattern includes a first portion of an edge with a first distance between the first portion and a pattern opposed thereto, a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090077525 - System and method for semiconductor device fabrication using modeling: System and method for using adjustment patterns as well as physical parameters as targets to control mask structure dimensions using optical proximity correction. A method for correcting layer patterns comprises selecting optimum sacrificial patterns, defining virtual targets from the optimum sacrificial patterns, and executing an optical proximity correction process with... Agent: Slater & Matsil LLP

20090077527 - System for determining repetitive work units: During a method for generating a mask pattern for a photo-mask, a target pattern is partitioned into subsets of the target pattern. The subsets of the target pattern may be selected so that at least some of the subsets are approximately identical, thereby dividing the subsets into a degenerate group... Agent: Wilson Sonsini Goodrich & Rosati

20090077526 - Write-pattern determination for maskless lithography: A method for generating a write pattern to be used in a maskless-lithography process is described. During the method, a computer system determines a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in a spatial-light modulator used in the maskless-lithography process. Furthermore, the... Agent: Wilson Sonsini Goodrich & Rosati

20090070714 - Identifying and improving robust designs using statistical timing anaysis: Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a... Agent: Bever, Hoffman & Harms, LLP

20090070715 - Method for eliminating negative slack in a netlist via transformation and slack categorization: A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a... Agent: International Business Machines Corporation Dept. 18g

20090070716 - System and method for optimization and predication of variability and yield in integrated ciruits: A system and method for designing a circuit includes generating physics based equations to describe phenomena of a circuit component, representing physical device geometry by correlating the physical device geometry with features of a circuit component design, and integrating the physical based equations and correlated physical device geometry into a... Agent: Keusey, Tutunjian & Bitetto, P.C.

20090070717 - Method and system for generating coverage data for a switch frequency of hdl or vhdl signals: The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model (10) within a register transfer level, providing a filtering algorithm or filtering rules (12) for signals occurring in... Agent: Duke W. Yee Yee & Associates, P.C.

20090070718 - Methodology for placement based on circuit function and latchup sensitivity: A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes... Agent: Greenblum & Bernstein, P.L.C

20090070719 - Logic block timing estimation using conesize: A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The... Agent: International Business Machines Corporation

20090070720 - System to identify timing differences from logic block changes and associated methods: A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the... Agent: International Business Machines Corporation

20090070721 - Three dimensional memory in a system on a chip: A 3D memory management system is described involving (a) memory hierarchy with adjustable synchronous DRAM, (b) 3D active memory with integrated logic circuitry, cache and router, (c) reconfigurable memory, (d) adaptive queue processing, (e) data compression processing and (f) multiple memory components in hierarchical configurations.... Agent: Neal Solomon

20090070722 - Method for generating device model overrides through the use of on-chip parametric measurement macros: A method generates area dependent design rules during semiconductor technology qualification by identifying the layout parametric variation in a semiconductor technology and establishing layout dependent design rules. This method applies the area dependent design rules to identify design sensitivity to area dependent design rules and to optimize semiconductor libraries and/or... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090070723 - method for generating a scan chain in a custom electronic circuit design: The present invention relates to a method for generating a scan chain in a custom electronic circuit design with a plurality of storage elements. Said method comprises the steps of providing a schematic, propagating all scan inputs and all scan outputs of the storage elements to a top level of... Agent: Ibm Microelectronics Intellectual Property Law

20090070724 - Information processing device, method of creating power supply system tree and program of the same: According to one embodiment, an information processing device includes a registration section for registering terminals of a symbol diagrams to a library by associating a relationship of connections of each of a devices, an extraction section for extracting a hierarchical structure of a power supply system and the symbol diagrams,... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090070725 - Method and system for manufacturing a semiconductor device having plural wiring layers: A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured... Agent: Foley And Lardner LLP Suite 500

20090070726 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20090070728 - Ip cores in reconfigurable three dimensional integrated circuits: The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture... Agent: Neal Solomon

20090070727 - Three dimensional integrated circuits and methods of fabrication: Three dimensional integrated circuitry is described with applications to hybrid multiprocessor and reconfigurable computing. Methods of fabrication of multilayer ICs are shown using multilayer TSVs.... Agent: Neal Solomon

20090070729 - Method and software tool for designing an integrated circuit: A method of designing an integrated circuit for use in an application having standards having a plurality of primitives, wherein each of the primitives has a corresponding response. The method includes generating a macros description of each of the primitives and the response corresponding to each of the primitives, generating... Agent: Philip E. Levy Eckert Seamans Cherin & Mellott, LLC

20090070731 - Distributed mask data preparation: Layout data is divided into segments of data, and each segment of data is distributed to a computing node in a parallel processing fracturing tool. During the fracturing process, the fracturing tool generates one or more global parameter values for each segment of data. After the fracturing process is completed,... Agent: Mentor Graphics Corp. Patent Group

20090070730 - Method and apparatus for modeling a vectorial polarization effect in an optical lithography system: One embodiment of the present invention provides a system that accurately models polarization effects in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a polarization-description grid map for a lens pupil in the optical lithography system. The system then constructs a pupil-polarization model... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090070732 - Fracture shot count reduction: Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for “jogs.” For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that can be aligned with the... Agent: Mentor Graphics Corp. Patent Group

20090064059 - Apparatus and method for analyzing circuit specification description design: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the... Agent: Amin, Turocy & Calvin, LLP

20090064060 - Apparatus and method of extracting equivalent circuit of t-type transmission circuit: A method of extracting an equivalent circuit of a T-type transmission circuit measures signals of the first and second terminals to obtain S parameters, converts the S parameters into Z parameters to generate a T-type circuit by using the Z parameters, obtains first to third lead line resistors and first... Agent: Amin, Turocy & Calvin, LLP

20090064058 - Methods and systems for computer aided design of 3d integrated circuits: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two... Agent: Burns & Levinson, LLP

20090064061 - Layout optimization using parameterized cells: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090064063 - Algorithmic reactive testbench for analog designs: An Algorithmic Reactive Testbench (ART) system is provided. The ART system is a high level verification environment with a user program in which on or more analog testbenches are instantiated and operated as prescribed in the program algorithm, and the properties of the unit testbenches (test objects) can be influenced... Agent: Stallman & Pollock LLP

20090064062 - Modeling silicon-on-insulator stress effects: A method and system for modeling silicon-on-insulator shallow trench isolation stress effect is described. The method includes creating instance parameters that define dimensions of a body-tie enclosure of gate and gate-end. The instance parameters are added to a netlist. The netlist and a lookup table are used to generate a... Agent: Honeywell International Inc.

20090064064 - Device, system and method for formal verification: Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement... Agent: Ibm Corporation, T.j. Watson Research Center

20090064066 - Method and apparatus for designing semiconductor integrated circuit: A method, apparatus, and recording medium including computer instructions for estimating the size of a core section of a semiconductor integrated circuit are provided. The method includes calculating a total net length of wires of nets and usable channel length of the core section by referring to circuit information and... Agent: Staas & Halsey LLP

20090064065 - Method of verifying circuit and computer-readable storage medium for storing computer program: A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous... Agent: Staas & Halsey LLP

20090064068 - Method and apparatus for evaluating the timing effects of logic block location changes in integrated circuit design: An integrated circuit (IC) floorplan system includes an integration design system that executes IC floorplan software on a semiconductor die IC model. The IC floorplan software includes a timing tool database of the IC model. IC integrators utilize the IC floorplan software to evaluate logic block moves within the IC... Agent: Mark P. Kahler

20090064069 - Method and system for generating a layout for an integrated electronic circuit:

20090064071 - Method and system for global coverage analysis: Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.... Agent: VistaIPLaw Group LLP

20090064067 - Method of balancing path delay of clock tree in integrated circuit (ic) layout: A method of balancing the path delay of a clock tree for minimizing clock skew of the clock tree in the IC layouts is described. The method includes the following steps: (a) A design tool calculates a plurality of path delay values from the root cell to each sink via... Agent: Austin Rapp & Hardman

20090064070 - Semiconductor circuit design method: This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method comprises setting the flip-flop based on circuit information on a semiconductor integrated circuit; obtaining a control signal controlling the flip-flop; calculating... Agent: Amin, Turocy & Calvin, LLP

20090064072 - Method and apparatus for placing an integrated circuit device within an integrated circuit layout: A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20090064073 - Method for diffusion based cell placement migration: A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20090064074 - System and computer program product for diffusion based cell placement migration: A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20090064077 - Layout versus schematic error system and method: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the... Agent: Sheppard Mullin Richter & Hampton LLP

20090064078 - Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof: An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality... Agent: Oliff & Berridge, PLC

20090064075 - Systems, methods and computer products for schematic editor mulit-window enhancement of hierarchical integrated circuit design: A method and apparatus for displaying hierarchical navigation and editing a plurality of hierarchical levels of design of an integrated circuit includes opening a main editor screen, displaying a viewable scope of hierarchical levels of design in the main editor screen and using a computer to assign a side window... Agent: Cantor Colburn LLP - IBM Rochester Division

20090064076 - Systems, methods and computer products for traversing schematic hierarchy using a scrolling mechanism: A method and a system for displaying hierarchical navigating, debugging and editing of selected hierarchical levels of design of a plurality of hierarchical levels of design in graphical hierarchical design applications, by assigning, from a schematic of the integrated circuit, a viewable scope of a block element desired for traversing.... Agent: Cantor Colburn LLP - IBM Rochester Division

20090064079 - Apparatus and method for circuit layout: An apparatus, includes a search unit which searches a critical signal path from a plurality of candidate signal paths connecting a first terminal and a second terminal, the critical signal path including the most strict delay limit in the plurality of candidate signal paths, and a display control unit which... Agent: Mcginn Intellectual Property Law Group, PLLC

20090064080 - Buffer insertion to reduce wirelength in vlsi circuits: Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning... Agent: Ibm Corporation (jvm)

20090064081 - Process for managing complex pre-wired net segments in a vlsi design: A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns... Agent: International Business Machines Corporation

20090064082 - Method for custom register circuit design: A computer program product stored on machine readable media is disclosed. The computer program product includes machine executable instructions for implementing a method of automatically creating a custom register circuit with a Computer Aided Design (CAD) application. The method includes obtaining parameters of the custom register circuit via a graphical... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090064083 - Computer automated method for designing an integrated circuit, a computer automated system for designing an integrated circuit, and a method of manufacturing an integrated circuit: A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one... Agent: Dla Piper LLP (us )

20090064085 - Method of creating photo mask layout, computer readable recording medium storing programmed instructions for executing the method, and mask imaging system: A method of generating a photo mask layout includes providing a first photo mask layout including main patterns and sub-resolution assist features (SRAF) patterns, defining a plurality of mesh cells by dividing the first photo mask layout into regions, generating a rule based table including correction information for correcting defects... Agent: F. Chau & Associates, LLC

20090064084 - Prediction model and prediction method for exposure dose: wherein MTTdiff represents the differences between the MTT value of a previous lot and the MTT value of a next lot, CDmask represents the actual critical dimension of the mask, X represents the magnification of the mask, ES represents the actual exposure dose of a previous lot, A′ represents an... Agent: J C Patents, Inc.