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Data processing: design and analysis of circuit or semiconductor mask February patent applications/inventions, industry category 02/09

20090055780 - Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components: A graph-based iterative method is provided for selecting component modifications in an integrated circuit design that reduce the power consumption to a minimum while still meeting timing constraints. Channel-connected components are represented as nodes in a timing graph and edges in the timing graph represent directed paths. From the timing... Agent: George A. Willinghan, Iii August Law Group, LLC

20090055781 - Circuit design device, circuit design program, and circuit design method: A circuit design device according to an embodiment of the present invention includes a processor performing operations of: extracting flip-flops each receiving a first clock and a control signal, from flip-flops represented in a first hardware description representing a circuit; generating a second hardware description by replacing the first clock... Agent: Foley And Lardner LLP Suite 500

20090055783 - Computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects: Various computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects are provided. One computer-implemented method for determining if actual defects are potentially systematic defects or potentially random defects includes comparing a number of actual defects in a group to a number of randomly generated... Agent: Baker & Mckenzie LLP

20090055782 - Secure yield-aware design flow with annotated design libraries: A method for designing and manufacturing integrated circuits is provided. The method includes providing a modeling parameter set for manufacturing an integrated circuit; dividing the modeling parameter set into time-dependent data and time-independent data; saving substantially all time-independent data into a design library; and saving substantially all time-dependent data into... Agent: Slater & Matsil, L.L.P.

20090055784 - Method for verifying safety apparatus and safety apparatus verified by the same: A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090055787 - Generation of engineering change order (eco) constraints for use in selecting eco repair techniques: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect... Agent: Silicon Valley Patent Group LLP

20090055786 - Method for verifying timing of a circuit: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090055788 - Silicon tolerance specification using shapes as design intent markers: Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping... Agent: Silicon Valley Patent Group LLP

20090055785 - Statistical iterative timing analysis of circuits having latches and/or feedback loops: Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and... Agent: Intellectual Property Dept./dewitt Ross & Stevens Wisconsin Alumni Research Foundation

20090055789 - Methods and systems for computer aided design of 3d integrated circuits: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two... Agent: Burns & Levinson, LLP

20090055790 - Design structure for on chip shielding structure for integrated circuits or devices on a substrate: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated... Agent: Greenblum & Bernstein, P.L.C

20090055791 - Process and apparatus for adjusting traces: Traces routed through a computer depiction of a routing area of an electronics system comprise a plurality of connected nodes. Forces are assigned to the nodes, and the nodes are moved in accordance with the forces. The forces may be based on such things as the proximity of the nodes... Agent: N. Kenneth Burraston Kirton & Mcconkie

20090055792 - Method and system for designing semiconductor integrated circuit providing dummy pattern in divided layout region: A method of designing a semiconductor integrated circuit, includes dividing a layout area in which a wiring pattern is disposed, into a plurality of division areas, determining a dummy pattern disposition area provided in each of the plurality of division areas, adding a dummy pattern to the dummy pattern disposition... Agent: Mcginn Intellectual Property Law Group, PLLC

20090055793 - Method of making an integrated circuit having fill structures: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there... Agent: Dicke, Billig & Czaja

20090055794 - Apparatus and method for dummy pattern arrangement: The EB data is separated into an area A and other area. The area A is covered by a recognition layer to which an algorism is linked to form a recognition layer A. For arranging a same dummy pattern for respective areas A, a dummy pattern creation starting point is... Agent: Foley And Lardner LLP Suite 500

20090049414 - Method and system for reducing via stub resonance: Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is... Agent: Ibm Rp-rps Sawyer Law Group LLP

20090049415 - Method and software tool for automatic generation of software for integrated circuit: A method of generating software code for a processor of an IC based on a simple input description of the IC's standards. The method includes generating a macros description of each of the primitives from the standards and the response corresponding to each of the primitives, wherein the macros description... Agent: Eckert Seamans Cherin & Mellott

20090049416 - Computer program product for extending incremental verification of circuit design to encompass verification restraints: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint... Agent: Ibm Austin (anthony England) C/o Law Office Of Anthony England

20090049417 - Method of designing a circuit for optimizing output bit length and integrated circuit therefor: In a circuit designing method for arithmetic elements to be employed in digital signal processing, a program is produced so that a directive is added to a target arithmetic operation which provides an overflow determination about desired digital signal processing. On the basis of this program, behavioral synthesis is performed.... Agent: Studebaker & Brackett PC

20090049418 - Method for radiation tolerance by automated placement: A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial... Agent: Ibm Corporation (jvm)

20090049419 - Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method: An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. When performing a DRC, as for in an FPGA, a DRC unit checks an attribute of a pin and the like by... Agent: Staas & Halsey LLP

20090049420 - Dummy pattern placement apparatus, method and program and semiconductor device: The load of OPC processing (especially, the load of bias processing) has been increasing due to optical effects involved in the placement of a dummy pattern. A pattern placement apparatus places dummy patterns in a layout region where a plurality of wiring patterns is placed. The pattern placement apparatus comprises:... Agent: Mcginn Intellectual Property Law Group, PLLC

20090044154 - Over approximation of integrated circuit based clock gating logic: A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing... Agent: Ibm Corporation, T.j. Watson Research Center

20090044156 - Method and apparatus for normalizing thermal gradients over semiconductor chip designs: A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor... Agent: Moser, Patterson & Sheridan, LLP Suite 100

20090044155 - Method and system for designing an electronic circuit: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090044157 - Acyclic modeling of combinational loops: Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including... Agent: Banner & Witcoff, Ltd.

20090044158 - Method, and extensions, to couple substrate effects and compact model circuit simulation for efficient simulation of semiconductor devices and circuit: This invention comprises a new method to couple simulation of electronics circuits (using compact models) with simulation of physical effects which require a PDE (partial differential equation) based simulation, for semiconductor MOSFET based devices and circuits. In particular the method can be used to capture high injection substrate effects such... Agent: John Nielsen Randick O'dea & Tooliatos, LLP

20090044160 - Dynamic critical path detector for digital logic circuit paths: Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed... Agent: Greenblum & Bernstein, P.L.C

20090044159 - False path handling: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit. The processing stage has inputs and outputs and includes circuit components arranged so as to define multiple logical paths between the inputs and the outputs. A timing constraint... Agent: Abelman, Frayne & Schwab

20090044161 - Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device: A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at the center position of a corresponding one of the crystal-grain-defining areas, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090044162 - Semiconductor integrated circuit device and fabrication method thereof: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor... Agent: Dickstein Shapiro LLP

20090044164 - Method for placing dummy patterns in a semiconductor device layout: Disclosed is a method for placing dummy patterns in a semiconductor device layout. More specifically, the method places the dummy patterns densely between main patterns in accordance with a sequence and configuration. The method includes placing vertical dummies having a greater length than width in a region other than main... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20090044163 - Method of generating a standard cell layout: A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the analysis result, and piecing together the leaf cell layouts to generate the standard cell layout.... Agent: North America Intellectual Property Corporation

20090044166 - Exposing mask and production method therefor and exposing method: An exposure mask forms a three-dimensional shape in simple structure and obtainable sufficient number of gray scales by exposure. In an exposure mask (M) for use in an exposure apparatus (S), the present invention is provided such that a plurality of pattern blocks constituted by a pair of a light... Agent: Sonnenschein Nath & Rosenthal LLP

20090044167 - Process-model generation method, computer program product, and pattern correction method: A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090044165 - Fpga with hybrid interconnect: An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20090037863 - Integration of pre-defined functionality and a graphical program in a circuit: System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in response to user input. At least one pre-defined hardware configuration program (HCP) is selected from a plurality of pre-defined HCPs in... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090037864 - Methods for designing semiconductor device with dynamic array section: A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of parallel lines... Agent: Martine Penilla & Gencarella, LLP

20090037865 - Router: Configuration of reconfigurable multidimensional fields are described. Information is provided for handling feedback, among other things.... Agent: Kenyon & Kenyon LLP

20090037866 - Alternating phase shift mask optimization for improved process window: A method for designing alternating phase shift masks is provided, in which narrow phase shapes located between densely spaced design shapes are colored to allow a maximum amount of light transmission. After assigning and ensuring binary legalization of the phase shapes, the narrow phase shapes are assigned a color, such... Agent: International Business Machines Corporation Dept. 18g

20090037867 - Method for optimization of optical proximity correction: A method of designing and forming a mask used for projecting an image of an integrated circuit design. After providing a mask element corresponding to a portion of a design of an integrated circuit layout, the method includes correcting the mask element using OPC techniques, and fracturing the OPC-corrected mask... Agent: Law Office Of Delio & Peterson, LLC.