Data processing: design and analysis of circuit or semiconductor mask inventions 01/09

20090031261 - Characterization and reduction of variation for integrated circuits: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.... Agent: Vista Ip Law Group LLP

20090031262 - Mask pattern formation method, mask pattern formation apparatus, and lithography mask: A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090031260 - Method, computer program and system providing for semiconductor processes optimization: A method, computer program and system for the optimization of semiconductor process parameters given a pre-specified set of targets and constraints on electrical performance metrics are disclosed. Semiconductor process engineers who are not expert in the art of electrical analysis or mathematical optimization can readily use the method of this... Agent: Harrington & Smith, Pc

20090031259 - Obtaining a feasible integer solution in a hierarchical circuit layout optimization: An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming... Agent: Hoffman Warnick Llc

20090031265 - Ic design modeling allowing dimension-dependent rule checking: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at... Agent: Hoffman Warnick Llc

20090031266 - Ic design modeling allowing dimension-dependent rule checking: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at... Agent: Hoffman Warnick Llc

20090031267 - Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit: A layout correction method, which minimize influence of changing a dummy metal on timings when signal wirings are corrected after completion of arrangement design of wirings including dummy metals, includes the steps of correcting, on a layout of a semiconductor integrated circuit in which at least signal wirings and a... Agent: Foley And Lardner LLP Suite 500

20090031263 - Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, Llc

20090031264 - System and method for finding electromigration, self heat and voltage drop violations of an integrated circuit when its design and electrical characterization are incomplete: A system and method for finding electromigration (EM), self heat (SH) and voltage drop/droop violations of an integrated circuit, when its design and electrical characterization are not complete, are disclosed. The method includes analyzing polygons for average, root-mean-square (RMS) and Ipeak current densities and voltages of a mask layout block... Agent: Danny Rittman

20090031268 - Methods for characterization of electronic circuits under process variability effects: A method for determining an estimate of statistical properties of an electronic system comprising individual components subject to manufacturing process variability is disclosed. In one aspect, the method comprises obtaining statistical properties of the performance of individual components of the electronic system, obtaining information about execution of an application on... Agent: Knobbe Martens Olson & Bear LLP

20090031269 - Analytical global placement for an integrated circuit: A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest... Agent: Smith-hill And Bedell, P.c.

20090031270 - Design method and system for minimizing blind via current loops: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.l.c.

20090031271 - Robust design using manufacturability models: The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate... Agent: Vista Ip Law Group LLP

20090031272 - Circuit board design tool and methods: A design tool for printed circuit boards displays a graphical representation of a printed circuit board layout through a graphical user interface (GUI). Comments for particular components of the printed circuit board layout can be entered through the graphical user interface. The comments are stored in a data file associated... Agent: Larson Newman Abel & Polansky, LLP

20090031273 - Method for stacked pattern design of printed circuit board and system thereof: A method for designing stacked pattern of PCB utilizing genetic algorithm and the system thereof are disclosed. The method comprises the following steps: First of all, information data of stacked pattern is inputted into operational interface of the software; Next, initial solution sets of stacked pattern are generated; Then, duplications... Agent: Stout, Uxa, Buyan & Mullins LLP

20090031274 - Computer readable medium, system and associated method for designing integrated circuits with loop insertions: A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by... Agent: International Business Machines Corporation

20090031275 - Method and system for performing global routing on an integrated circuit design: A method for performing global routing on an integrated circuit design is disclosed. The integrated circuit design is initially divided into multiple G-cells. The G-cells are interconnected by a set of nets. The set of nets is then decomposed into corresponding wires. The wires are prerouted to interconnect the G-cells.... Agent: Dillon & Yudell LLP

20090031277 - Architectural physical synthesis: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090031278 - Architectural physical synthesis: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20090031276 - Design apparatus, design method, and program: A design apparatus, a design method, and a program, which enable the design of a small-scale circuit that is high in serviceability and quality are provided. Plural commands described at a behavior level are separated into control system behaviors that are behaviors concerning control and data system behaviors that are... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090024967 - Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer: Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer are provided. One method includes generating simulated images of the reticle features printed on the wafer using different generated models for a set of different values of exposure conditions. The method... Agent: Baker & Mckenzie LLP

20090024968 - Method of designing semiconductor integrated circuit and mask data generation program: A method of designing a semiconductor integrated circuit includes: generating a layout data indicating a layout; and generating a mask data based on the layout data. The generating the mask data includes: referring to the layout data to extract a parameter that specifies a layout pattern around a target transistor... Agent: Foley And Lardner LLP Suite 500

20090024966 - Method of optimized gradient coil design: The present invention relates to a method of discretization of the continuous current solution of a gradient coil design that allows satisfaction of the target field quality characteristics as well as other characteristics such as minimization of the energy/inductance, minimization of the residual eddy current effect, minimization of the thrust... Agent: Ulmer & Berne, LLP Attn: Diane Bell

20090024971 - Cursor path vector analysis for detecting click fraud: A system and method for detecting click fraud where data is received corresponding to a tracking of movement of a cursor on a web page. The movement of the cursor is associated with at least one vector. The at least one vector represents at least a portion of the cursor... Agent: Moore & Van Allen, Pllc For Ibm

20090024970 - Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device: A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090024969 - Semiconductor chip design having thermal awareness across multiple sub-system domains: A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the... Agent: Walstein Bennett Smith Iii

20090024972 - Structures of powering on integrated circuit: Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a... Agent: Hoffman Warnick Llc

20090024973 - Method and program for designing semiconductor integrated circuit: A method of designing a semiconductor integrated circuit includes: performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around the cell; and generating a delay function expressing a delay value of the cell as a function of the parameter, based on a result... Agent: Foley And Lardner LLP Suite 500

20090024974 - Method and program for designing semiconductor integrated circuit: A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of... Agent: Foley And Lardner LLP Suite 500

20090024975 - Systems, methods and computer products for traversing design hierarchy using a scroll mechanism: A method and an apparatus are disclosed for the display of hierarchical navigation in the automated design of integrated circuits under test. A user, using a computer, assigns a head pointer assignment and a tail pointer assignment, which form a definition of a viewable scope of at least one hierarchical... Agent: Cantor Colburn LLP - Ibm Rochester Division

20090024977 - Local preferred direction architecture, tools, and apparatus: model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred... Agent: Adeli & Tollen, LLP

20090024976 - Method for automatically routing multi-voltage multi-pitch metal lines: A method for program routing a circuit with at least a first and second voltages in a single layer is disclosed, which comprises defining a first and second layer types corresponding to the first and second voltages, respectively, specifying at least one first attribute for the first layer type and... Agent: K & L Gates LLP

20090024978 - Semiconductor device mask, method of forming the same and method of manufacturing semiconductor device using the same: Embodiments relate to a semiconductor device mask in which an optical proximity correction (OPC) process is performed to compensate for varying degrees of planarization of a lower layer and a method of forming a mask pattern. In embodiments, a method of forming a semiconductor device mask includes dividing a semiconductor... Agent: Sherr & Vaughn, Pllc

20090019403 - Circuit wiring interference analysis device, interference analysis program, database used in interference analysis device, and asymmetrically connected line model: An interference analysis device that analyzes interference includes an input unit 2 that inputs design data, a selection unit 3 that selects an analysis region, a division unit 5 that divides a wire into segments, a calculation unit 6 that calculates a circuit matrix regarding a coupled line, and an... Agent: Hamre, Schumann, Mueller & Larson P.C.

20090019404 - Method for calculating difficulty level of routing in netlist: The invention provides a method capable of calculating a difficulty level of routing at a high processing speed with good calculating accuracy. The method involves: performing hierarchical clustering on cells in a netlist so as to successively group the cells to be connected to each other through a larger number... Agent: Mcdermott Will & Emery LLP

20090019407 - Clock supply circuit and method of designing the same: A clock supply circuit according to the present invention has a clock tree structure, supplies a clock signal to operating elements, includes driving elements arranged in levels in the clock tree structure and includes connection lines which connect output terminals of the driving elements either to input terminals of driving... Agent: Greenblum & Bernstein, P.L.C

20090019405 - Integrated circuit device evaluation device, evaluation method, and evaluation program: Time-axis data that include the peak waveform and the clock frequency of the power supply current when the LSI is switched are inputted to the LSI information input unit, and the LSI equivalent circuit creation unit creates an equivalent circuit of the LSI on the basis of the time-axis data.... Agent: Sughrue Mion, PLLC

20090019408 - Production method, design method and design system for semiconductor integrated circuit: A production method for a semiconductor integrated circuit includes: creating a model parameter of an element constituting a cell, wherein the model parameter is defined by a design value and a distribution function of variability from the design value; performing a circuit simulation using the model parameter to create a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090019406 - Verification apparatus and verification method: A variable is allocated to a statement that designates an event associated with a function call in an assertion. Generation of the event at an arbitrary time on a continuous time series is detected, and a value corresponding to a meaning of the statement is assigned to the variable. Whether... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090019409 - Method for reducing timing libraries for intra-die model in statistical static timing analysis: A method for performing statistical static timing analysis on an integrated circuit (IC) is disclosed, which comprises identifying a plurality of turned-on devices in the IC during a predetermined operation of the IC, choosing only the libraries of the plurality of turned-on devices, and calculating a time delay of the... Agent: K & L Gates LLP

20090019412 - Design method and design apparatus for semiconductor integrated circuit: According to the present invention, timing information, connection information and physical information are received, and at the weighting determination step, the degree to which a cell can move is weighted. Then, at the movement range determination step, the movement enabled range of the cell is determined, and whether or not... Agent: Mcdermott Will & Emery LLP

20090019410 - Path planning device: A path generating device 1 has a constraint mid-configuration generator 10. The constraint mid-configuration generator 10 defines a constraint surface in a joint angle space. The path generating device 1 probabilistically generates a mid-configuration in the joint angle space. The constraint mid-configuration generator 10 projects the probabilistically generated mid-configuration onto... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090019413 - System and method for automatic layout of integrated circuit: An automatic layout apparatus is provided with: a storage device storing a cell library containing therein cell library data; and a layout tool obtaining from the cell library the cell library data associated with cells to be placed as described in a netlist to perform automatic placement of the cells... Agent: Mcginn Intellectual Property Law Group, PLLC

20090019411 - Thermally aware design modification: In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations... Agent: Walstein Bennett Smith Iii

20090019414 - High tolerance tcr balanced high current resistor for rf cmos and rf sige bicmos applications and cadenced based hierarchical parameterized cell design kit with tunable tcr and esd resistor ballasting feature: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at... Agent: Scully, Scott, Murphy & Presser, P.C.

20090019415 - Stage mitigation of interconnect variability: The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid... Agent: Hoffman Warnick LLC

20090019416 - Customizable synthesis of tunable parameters for code generation: An apparatus, method and/or computer readable media automatically generate hardware description language (HDL) code. A design environment is configured to receive a hardware design, the hardware design including a plurality of numerical parameters. A user interface (UI) accepts a designation of a first numerical parameter as a tunable numerical parameter.... Agent: Cesari And Mckenna, LLP

20090019417 - Logic synthesis apparatus: According to the present invention, there is provided an apparatus for executing logic synthesis for a module having a plurality of clock domains, having: an input unit which inputs circuit description data about a circuit function and a constraint in logic synthesis; a path selection unit which selects a path... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090019418 - Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090019419 - Method for forming lsi pattern: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to... Agent: Mcdermott Will & Emery LLP

20090013289 - Circuit design optimization of integrated circuit based clock gated memory elements: A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of... Agent: Ibm Corporation, T.j. Watson Research Center

20090013290 - Method and system for electromigration analysis on signal wiring: The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell;... Agent: International Business Machines Corporation Dept. 18g

20090013291 - Generating a base curve database to reduce storage cost: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in... Agent: Bever, Hoffman & Harms, LLP

20090013292 - Context dependent timing analysis and prediction: In one embodiment, a method for providing a context aware timing analysis is provided. A library of cells is pre-computed to take into account contouring that may result based on possible context situations for instances in an integrated circuit design. This results in a library that includes a characterization for... Agent: Trellis Intellectual Property Law Group, PC

20090013293 - Delay calculation method, a data processing program and a computer program product for routing of wires of an electronic circuit: The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin (P0; P30) and a receiving pin (P1-P19; P32-P42) being coupled by at least one loop (40, 50; 60, 70, 80), said loop (40, 50;... Agent: International Business Machines Corporation

20090013294 - System and method for statistical timing analysis of digital circuits: The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the... Agent: Louis J. Percello Intellectual Property Law Dept.

20090013297 - Contact resistance and capacitance for semiconductor devices: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are... Agent: Texas Instruments Incorporated

20090013296 - Layout design method for a semiconductor integrated circuit: A method of designing a layout of a semiconductor integrated circuit having a hard macro includes acquiring a condition for permitting wirings with respect to a given region within the hardmacro, and searching a passing wiring that passes through the given region among the wirings that are arranged 6n the... Agent: Mcginn Intellectual Property Law Group, PLLC

20090013295 - Method for arranging virtual patterns: A method for arranging virtual patterns includes providing a semiconductor layout and a circuit pattern; setting a forbidden area of the circuit pattern according to a restriction condition; defining at least a virtual pattern arrangement area on a portion of the semiconductor layout which does not correspond to the forbidden... Agent: North America Intellectual Property Corporation

20090013298 - Offset fill: Techniques are described for increasing the density of structures in a layout circuit design, while reducing undesired total interconnect capacitance that might otherwise be created by the increase in structure density. Data representing a pattern of fill structures is added to the fill regions of the design for one of... Agent: Mentor Graphics Corp. Patent Group

20090013299 - Buffer insertion to reduce wirelength in vlsi circuits: Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning... Agent: Ibm Corporation (jvm)

20090013300 - Synthesis strategies based on the appropriate use of inductance effects: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the... Agent: Klarquist Sparkman, LLP

20090013301 - Hardware definition language generation for frame-based processing: A method generates hardware description language (HDL) code from a model having a plurality of components, including at least one component that processes frame-based input data. A selected preference is received for implementing the frame-based component. The generated HDL code includes a hardware implementation of the frame-based component that satisfies... Agent: Lahive & Cockfield, LLP/the Mathworks Floor 30, Suite 3000

20090013303 - Method of creating mask layout image and imaging system: Provided are a method of creating a mask layout image from a target image, a computer readable storage medium having stored thereon a computer program for executing the method, and an imaging system. The method includes reading all or a part of a target image to be transcribed on a... Agent: Myers Bigel Sibley & Sajovec

20090013302 - Methods of arranging mask patterns responsive to assist feature contribution to image intensity and associated apparatus: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of an assist feature to image intensity. In some methods of arranging mask patterns, a distribution of functions h(ξ−x) is obtained which represents the contribution of an assist feature to image intensity on a main feature.... Agent: Myers Bigel Sibley & Sajovec

20090013304 - Physical-resist model using fast sweeping: A method for determining a surface in a material is described. During this method, arrival times of a wavefront at a first depth in the material are calculated using an Eikonal equation. Note that the first depth is proximate to an outer surface of the material. Next, arrival times of... Agent: Wilson Sonsini Goodrich & Rosati

20090007029 - Method for designing driver: A method for designing a driver including matching stages having transistors matched to each other is disclosed, including interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage. A size of the transistors may be determined using the... Agent: Sherr & Vaughn, PLLC

20090007027 - Translating a user design in a configurable ic for debugging the user design: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit elements(s). The method... Agent: Adeli & Tollen, LLP

20090007028 - Wafer layout optimization method and system: For determining an optimized wafer layout, at least two wafer layouts are specified for a given wafer, each wafer layout defining the location of a plurality of die with regard to the wafer. An optimization parameter value of at least one optimization parameter is determined for each of the at... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20090007030 - Design-based monitoring: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in a layer of the IC that is susceptible to a process fault. Upon... Agent: Applied Materials, Inc. C/o Sonnenschein Nath & Rosenthal LLP

20090007032 - Method and apparatus for substrate noise analysis using substrate tile model and tile grid: A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20090007031 - Method and system for implementing cached parameterized cells: Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.... Agent: VistaIPLaw Group LLP

20090007033 - Method to transfer failure analysis-specific data between data between design houses and fab's/fa labs: A method and system for an IC design house to transfer design and layout information to a fabrication or failure analysis facility on a need-to-know basis to enable effective failure analysis while not providing unnecessary or extraneous information.... Agent: Deborah W. Wenocur

20090007035 - Accurate parasitic capacitance extraction for ultra large scale integrated circuits: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various... Agent: Slater & Matsil, L.L.P.

20090007034 - Device, system, and method for correction of integrated circuit design: Device, system and method of correcting an integrated circuit design. For example, a method includes receiving a list of one or more root points for an active netlist that requires logic correction, wherein the root points correlate between elements of the active netlist and elements of a re-synthesized netlist that... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090007039 - Hierarchical feature extraction for electrical interaction calculations: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the... Agent: Klarquist Sparkman, LLP

20090007038 - Hybrid counterexample guided abstraction refinement: Systems and methods are disclosed for performing counterexample guided abstraction refinement by transforming a design into a functionally equivalent Control and Data Flow Graph (CDFG); performing a hybrid abstraction of the design; generating a hybrid abstract model; and checking the hybrid abstract model.... Agent: Nec Laboratories America, Inc.

20090007037 - Hybrid fully-silicided (fusi)/partially-silicided (pasi) structures: Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090007036 - Integrated fin-local interconnect structure: Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090007040 - Apparatus for analyzing post-layout timing critical paths: A critical path detecting unit for detecting critical paths for a design in which cells are placed on an integrated circuit and information concerning timing constraints. A representative-critical-path extracting unit extracts a representative critical path by having one critical path represent critical paths which share more intervals than a certain... Agent: Shimokaji & Associates, P.C.

20090007041 - Automatic delay adjusting method for semiconductor integrated circuit by using dummy wiring: An automatic delay adjusting method of a semiconductor integrated circuit includes placing a dummy wiring to a layout data and connecting the dummy wiring to a target wiring between a first cell and a second cell which is a timing violation occurs for the target wiring in the layout data.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090007042 - Virtual data representation through selective bidirectional translation: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects... Agent: Lsi Corporation

20090007043 - Managing integrated circuit stress using dummy diffusion regions: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090007044 - Design support method and apparatus, and computer product: A design support apparatus includes an extracting unit that extracts a first cell from among plural cells in a target circuit; a detecting unit that detects a second cell arranged adjacent to the first cell; and a setting unit that sets a delay value of the first cell according to... Agent: Staas & Halsey LLP

20090007045 - Method of designing a semiconductor device: Aiming at providing a method of designing a semiconductor device capable of producing a semiconductor device which expresses performances adapted to required performances, the present invention sets a plurality of suites of device parameters, containing parameters relevant to transistor characteristics (transistor parameters) and parameters relevant to interconnect characteristics (interconnect parameters)... Agent: Young & Thompson

20090007046 - Layout method for vertical power transistors having a variable channel width: The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters... Agent: Hunton & Williams LLP Intellectual Property Department

20090007048 - Design structure for a computer memory system with a shared memory module junction connector: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090007047 - Design structure for a phase locked loop with stabilized dynamic response: A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090007049 - Automatic trace design method: An automatic trace design method comprises: a tentative passing point setting step of setting, on a virtual plane corresponding to a substrate surface, tentative passing points through which a trace subject to route determination should pass; a triangle setting step of setting triangles, each of which is formed by one... Agent: Paul And Paul

20090007050 - System for designing re-programmable digital hardware platforms: A digital design system and method are provided for re-programmable hardware platforms, such as field programmable gate arrays (FPGAs) and other re-programmable system designs. The design system and method bridge the gap between what has previously been a development and prototyping platform used during the design phase of an electronic... Agent: William C. Milks, Iii Russo & Hale LLP

20090007051 - Selectable device options for characterizing semiconductor devices: A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and... Agent: Hoffman Warnick LLC

20090007052 - Method for verifying pattern of semiconductor device: Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed... Agent: Marshall, Gerstein & Borun LLP

20090007053 - Method of manufacturing mask for semiconductor device: A method of manufacturing a mask for a semiconductor device includes checking layout data for a mask in the semiconductor device and correcting any errors in the layout data that violate the design rule, filling small jogs in the layout data, performing optical proximity correction on the jog-filled layout data,... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.