Data processing: design and analysis of circuit or semiconductor mask inventions 12/08

20080320420 - Efficient cell swapping system for leakage power reduction in a multi-threshold voltage process: A method for designing an integrated circuit, comprising the steps of (A) calculating an efficiency value for each of a plurality of equivalent cells in the design; and (B) selecting a number of the plurality of equivalent cells based on the efficiency values. The equivalent cells (i) decrease an overall... Agent: Christopher P Maiorana, PC Lsi Corporation

20080320421 - Feature extraction that supports progressively refined search and classification of patterns in a semiconductor layout: A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing... Agent: Hoffman Warnick LLC

20080320422 - Design rule checking system: In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a... Agent: Freescale Semiconductor, Inc. Law Department

20080320423 - System and method to protect computing systems: A system and method for protecting computing systems, and more particularly a system and method which a dedicated hardware component configured to communicate with a protection program. A computer hardware subsystem includes a memory comprising content. The content is at least a list of files which have been modified within... Agent: Greenblum & Bernstein, P.L.C

20080320424 - Validation of electrical performance of an electronic package prior to fabrication: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the... Agent: Schmeiser, Olsen & Watts

20080320427 - Apparatus and method for integrated circuit design with improved delay variation calculation based on power supply variations: An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level... Agent: Mcginn Intellectual Property Law Group, PLLC

20080320426 - Method for verifying timing of a circuit with crosstalk victim and aggressor: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080320425 - Method for verifying timing of a circuit with rlc inputs and outputs: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080320428 - Minimizing effects of interconnect variations in integrated circuit designs: Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080320429 - Circuit layout tool dimming feature: A computer program product stored on machine readable media including machine executable instructions for display a layout of a circuit design, includes instructions for: receiving designation of at least one design segment from a user; receiving designation of a degree of intensity for at least one of highlighting and dimming... Agent: Cantor Colburn LLP - IBM Rochester Division

20080320430 - Spare gate array cell distribution analysis: A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups:... Agent: International Business Machines Corporation

20080320431 - Power mesh for multiple frequency operation of semiconductor products: The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be... Agent: Lsi Corporation

20080320432 - Disabling unused io resources in platform-based integrated circuits: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied... Agent: Lsi Corporation

20080320433 - Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit- boar: An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape... Agent: Staas & Halsey LLP

20080320434 - Photomask management method and photomask wash limit generating method: A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080320435 - Optical proximity correction improvement by fracturing after pre-optical proximity correction: A method for fabricating a mask used to make integrated circuits is provided using an improved OPC process whereby a pre-fracturing OPC process is performed on the target design of the integrated circuit. The pre-fractured OPC design is then fractured and a post-fracturing OPC process performed to make the final... Agent: Law Office Of Delio & Peterson, LLC.

20080313576 - System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices: A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more... Agent: Shemwell Mahamedi LLP

20080313577 - Vlsi artwork legalization for hierarchical designs with multiple grid constraints: A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be... Agent: Greenblum & Bernstein, P.L.C

20080313580 - Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent... Agent: Texas Instruments Incorporated

20080313578 - Techniques for use with automated circuit design and simulations: Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080313579 - Techniques for use with automated circuit design and simulations: Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080313582 - Accurate transistor modeling: A method and system for generating transistor models. In one embodiment, the method includes generating a transistor model that characterizes a topology of a circuit, and characterizes at least one coupling or at least one interaction between at least two transistors of the circuit.... Agent: Schwegman, Lundberg & Woessner / Atmel

20080313583 - Apparatus and method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip: An apparatus and method are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080313581 - Independent migration of hierarchical designs with methods of finding and fixing opens during migration: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell... Agent: Hoffman Warnick LLC

20080313587 - Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware... Agent: Nixon & Vanderhye P.C.

20080313584 - Logic verification method: A logic verification method is disclosed to a computer to conduct a logic verification process by using a state machine based on a verification property, including the steps of (a) displaying at lease one waveform generated based on a logic verification result of the logic verification process, (b) displaying the... Agent: Staas & Halsey LLP

20080313585 - Method of verifying semiconductor integrated circuit and design program: A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying... Agent: Mcginn Intellectual Property Law Group, PLLC

20080313586 - Resistance net generating apparatus for circuit simulation: In an aspect of the present invention, a resistance net generating apparatus includes a dividing section configured to acquire a data of a wiring pattern which contains connection position with vias and to divide the wiring pattern into rectangular patterns; a division pattern processing section configured to set nodes and... Agent: Foley And Lardner LLP Suite 500

20080313590 - Method and system for evaluating timing in an integrated circuit: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the... Agent: Greenblum & Bernstein, P.L.C

20080313588 - Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing: A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080313589 - Techniques for use with automated circuit design and simulations: Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080313591 - Semiconductor integrated circuit designing method: An IC designing method includes planning placement of a first isolated-power supplied region operating between common ground and power bus lines during a normal operation, and second/third isolated-power supplied regions each operating between the common ground bus line and first/second isolated power lines and supplied with potentials different from the... Agent: Amin, Turocy & Calvin, LLP

20080313592 - Mask layout editor shape query: A computer program product stored on machine readable media includes machine executable instructions for display a layout of a circuit design, the product including instructions for displaying a layout of a circuit design, the product including instructions for: receiving query input including location information; querying a design layout for object... Agent: Cantor Colburn LLP - IBM Rochester Division

20080313593 - Occupancy based on pattern generation method for maskless lithography: An occupancy based pattern generation method for a maskless lithography system using micromirrors is disclosed. The present invention includes the steps of recognizing a pattern upon the substrate through the extraction of the pattern boundary and the construction of the pattern region and recognizing the pattern upon the micromirror through... Agent: Workman Nydegger

20080307371 - Manufacturing aware design and design aware manufacturing: Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC... Agent: Adeli & Tollen, LLP

20080307372 - Method and system for performing minimization of input count during structural netlist overapproximation: A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of... Agent: Dillon & Yudell LLP

20080307373 - Apparatus, method and computer program for managing circuit optimization information: A circuit optimization information management apparatus provides information to be used when a circuit parameter optimization program is executed to design an integrated circuit. The apparatus includes an accumulator for registering information relating to a candidate of a circuit type used in a design target circuit, a simulation test bench... Agent: Wolf Greenfield & Sacks, P.C.

20080307377 - Method for determining maximum operating frequency of a filtered circuit: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080307375 - Method for performing timing analysis of a circuit: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080307376 - Method for verifying timing of a multi-phase, multi-frequency and multi-cycle circuit: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080307374 - Method, system, and computer program product for mapping a logical design onto an integrated circuit with slack apportionment: A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080307378 - Operational cycle assignment in a configurable ic: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and... Agent: Adeli & Tollen, LLP

20080307379 - System and method for incremental statistical timing analysis of digital circuits: The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080307380 - Operational cycle assignment in a configurable ic: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and... Agent: Adeli & Tollen, LLP

20080307381 - Ic layout parsing for multiple masks: A method for separating features in a target layout into different mask layouts for use in a photolithographic process. Features of a target layer are searched for features having a predefined shape. In one embodiment, portions of the feature having the predefined shape divided into two or more sub-features and... Agent: Klarquist Sparkman, LLP

20080307382 - Combination of ground devices in wiring harness designs: A method can include allowing a user to place a first wiring harness design component within a wiring harness topology in a wiring harness design workspace, allowing the user to place a first plurality of ground devices within the first wiring harness design component placed in the wiring harness topology,... Agent: Klarquist Sparkman, LLP

20080307383 - Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints: An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design... Agent: Hoffman Warnick LLC

20080301593 - Method for automatic clock gating to save power: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized... Agent: Townsend And Townsend And Crew, LLP

20080301594 - Method for optimized automatic clock gating: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared... Agent: Townsend And Townsend And Crew, LLP

20080301592 - Methodology for automated design of vertical parallel plate capacitors: Apparatus and program product for designing vertical parallel plate (VPP) capacitor structures in which the capacitor plates in different conductive layers of the capacitor stack have a different physical spacing. The methodology optimizes the physical spacing of the plates in each conductive layer to achieve a targeted electrostatic discharge protection... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20080301595 - Optimization of laser parameters to achieve desired performance: One example disclosed herein relates to a method of at least partially optimizing one or more output performance parameters of a laser die. The method includes an act of identifying one or more output performance parameters to be at least partially optimized, an act of identifying one or more design... Agent: Workman Nydegger

20080301596 - Method and system for testing bit failures in array elements of an electronic circuit: The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write... Agent: Richard M. Kotulak International Business Machines Corporation

20080301598 - method for checking constraints equivalence of an integrated circuit design: The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.... Agent: Sughrue Mion, PLLC

20080301600 - Cad apparatus and check support apparatus: In a computer aided design (CAD) apparatus, an association-data acquiring unit acquires association data that defines an association between pins of a first connector and those of a second connector to be connected to the first connector, and an assignment of signals to the pins. A part-information acquiring unit acquires... Agent: Staas & Halsey LLP

20080301603 - Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic: Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is... Agent: Ibm Corporation (jvm)

20080301602 - Method and apparatus for performing formal verification using data-flow graphs: An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts.... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080301599 - Method for rapid estimation of layout-dependent threshold voltage variation in a mosfet array: An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080301597 - Method to determine the root causes of failure patterns by using spatial correlation of tester data: A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and... Agent: George A. Willinghan, Iii August Law Group, LLC

20080301601 - Techniques for use with automated circuit design and simulations: Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080301604 - Apparatus for and method of estimating the quality of clock gating solutions for integrated circuit design: A novel apparatus for and method of estimating the quality of candidate clock gating solutions. The quality estimation mechanism of the present invention filters candidate clock gating solutions by estimating a measure of the quality of each candidate solution. The effect of the proposed solution on both timing and leakage... Agent: Ibm Corporation, T.j. Watson Research Center

20080301606 - Design structure for switching digital circuit clock net driver without losing clock pulses: A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080301605 - Method for designing lsi system and design support device for lsi system: A method and a device for automatically calibrating a light intensity measurement device is disclosed. The device includes an optical switch for switching a route of output from an optical intensity modulator, an optical attenuator arranged on a first waveguide, a second waveguide, a light intensity measurement device, a control... Agent: Myers Wolin, LLC

20080301607 - Method, system, and computer program product for hierarchical integrated circuit repartitioning: A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080301608 - Methods and apparatuses for designing multiplexers: Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first multiplexer and partitioning the partition neutral representation to create a plurality of second... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20080301609 - Method for generation, placement, and routing of test structures in test chips: A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad array layout of the... Agent: Freescale Semiconductor, Inc. Law Department

20080301610 - Semiconductor integrated circuit having reduced cross-talk noise: A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.... Agent: Arent Fox LLP

20080301611 - Selective optical proximity layout design data correction: After layout design data has been modified using an OPC process, a repair flow is initiated. This repair flow includes analyzing the modified data to identify any remaining or new potential print errors in the layout data. Regions then are formed around the identified potential print errors, and a subsequent... Agent: Mentor Graphics Corp. Patent Group

20080301612 - Method and system for placement of electric circuit components in integrated circuit design: The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step (112) placing the cells (11) into bins (12, 14, 16A, 16B) on the chip (10), as well as a detailed placement process (116)... Agent: International Business Machines Corporation

20080301613 - Designing wiring harnesses: A method of designing a wiring harness using a wiring harness design tool can include allowing a first user to access and edit a first wiring harness design component in a wiring harness design workspace, allowing a second user to access and edit a second wiring harness design component in... Agent: Klarquist Sparkman, LLP

20080301614 - Method, system, and computer program product for spare circuitry distribution: A method, system, and computer program product for spare circuitry distribution in an integrated circuit design are provided. The method includes receiving design data for the integrated circuit design. The design data includes descriptions of spare circuitry and physical area available for circuitry placement. The method further includes determining target... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080301617 - Computer readable recording medium with a wiring design program stored thereon and wiring design device: An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two lines, is added to the wiring... Agent: Volentine & Whitt PLLC

20080301615 - Focused ion beam defining process enhancement: Embodiments employ a method to define points on selected nets in a netlist for a focused ion beam (FIB) to create open circuits. A selected net is partitioned into a set of sub-segments, and after considering all metal layers at and above that of the selected net, a subset of... Agent: Seth Kalson C/o Intellevate, LLC

20080301616 - Layout generator for routing and designing an lsi: According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined... Agent: International Business Machines Corporation

20080301618 - Method and system for routing of integrated circuit design: The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis (208) for a given routed placement of cells (11) containing said electric circuits on chip (10); defining (210) a critical area... Agent: International Business Machines Corporation

20080301619 - System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit: A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a data driven model for matching the hardware resource requirements for an associated user module and the available hardware resources on an underlying chip. Databases are utilized to describe... Agent: Cypress C/o Murabito, Hao & Barnes LLP

20080301621 - Mask pattern correcting method: In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080301622 - Method of determining defects in photomask: A method of determining defects in photomasks according to the present invention is designed to increase the yield of the manufacture of photomasks and to decrease the cost of inspecting the photomasks. In the method, circuit data 1 representing a circuit to be formed on a semiconductor substrate by photolithography... Agent: Sughrue Mion, PLLC

20080301620 - System and method for model-based sub-resolution assist feature generation: Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window.... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080301623 - Lithography suspect spot location and scoring system: A fast method to detect hot spots using foundry independent models that do not require RET/OPC synthesis is presented. In some embodiments of the present invention, sensitive spots are located. Lithography models are used to simulate the geometry near the sensitive spots to produce a model of the area around... Agent: Silicon Valley Patent Group LLP

20080301624 - System and method for employing patterning process statistics for ground rules waivers and optimization: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules... Agent: Keusey, Tutunjian & Bitetto, P.C.