Data processing: design and analysis of circuit or semiconductor mask inventions 11/08

20080295041 - System and method for power domain optimization: A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on... Agent: Ibm Corporation (pec) C/o Patrick E. Caldwell, Esq.

20080295042 - System for delay reduction during technology mapping in fpga: The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present... Agent: Sadler, Breen, Morasch & Colby, Ps

20080295043 - Automatic error diagnosis and correction for rtl designs: A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and... Agent: Marshall, Gerstein & Borun LLP

20080295044 - Method and apparatus for mapping design memories to integrated circuit layout: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are... Agent: David Smith Lsi Logic Corporation

20080295048 - Inline defect analysis for sampling and spc: In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080295045 - Method for creating hdl description files of digital systems, and systems obtained: The invention relates to a method comprising the following steps: HDL instruction sequences which are to be at the origin of memory elements during the synthesis of the system are automatically localised in the original HDL description files; and so-called SCAN HDL instructions are inserted into at least some of... Agent: Clark & Brody

20080295046 - Predicting ic manufacturing yield based on hotspots: One embodiment of the present invention provides a system that predicts a manufacturing yield of a chip. During operation, the system first receives a chip layout. Next, the system identifies hotspots within the chip layout, wherein a hotspot is a location within the chip layout wherein a yield-indicative variable value... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080295047 - Stage yield prediction: In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080295049 - Pattern designing method, pattern designing program and pattern designing apparatus: An embodiment of the invention provides a pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset... Agent: Sonnenschein Nath & Rosenthal LLP

20080295053 - Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a... Agent: Bever, Hoffman & Harms, LLP

20080295054 - Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through... Agent: Priest & Goldstein, PLLC

20080295052 - Modeling asynchronous behavior from primary inputs and latches: Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value,... Agent: Ibm Corporation (jvm)

20080295050 - Semiconductor integrated circuit and method of designing thereof based on tpi: A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path... Agent: Mcginn Intellectual Property Law Group, PLLC

20080295051 - Slew constrained minimum cost buffering: A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for... Agent: Ibm Corporation (jvm)

20080295055 - Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit: The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining... Agent: Buchanan, Ingersoll & Rooney PC

20080295057 - Method for determining a standard cell for ic design: IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be generated by generating critical... Agent: North America Intellectual Property Corporation

20080295056 - System and method for building configurable designs with hardware description and verification languages: An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in a design. Basically, the configurable design is an all-inclusive design having a large... Agent: Patent Venture Group

20080295058 - Representing binary code as a circuit: A high level intermediate representation of a binary is generated. Circuit nodes from the high level intermediate representation are built, wherein a circuit node represents an operation in the high level intermediate representation. The circuit nodes are connecting using a flow analysis of the binary to build a circuit that... Agent: Microsoft Corporation

20080295059 - Method for correcting optical proximity effect: A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibration using the measured line widths and... Agent: Marshall, Gerstein & Borun LLP

20080295060 - Method for forming a semiconductor device using optical proximity correction for the optical lithography: A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has... Agent: Freescale Semiconductor, Inc. Law Department

20080295061 - Generalization of the photo process window and its application to opc test pattern design: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across... Agent: Duane Morris LLP - PhiladelphiaIPDepartment

20080295063 - Method and apparatus for determining factors for design consideration in yield analysis: Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080295062 - Method of verifying a layout pattern: A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film... Agent: North America Intellectual Property Corporation

20080288897 - Method of enforcing a contract for a cad tool: A method for enforcing a contract for a computer-aided-design (CAD) tool is provided. In this method, a first payment for the CAD tool is made in accordance with the contract. The first payment is associated with user access to the CAD tool. At this point, the CAD tool can be... Agent: Bever, Hoffman & Harms, LLP

20080288898 - Prediction of dynamic current waveform and spectrum in a semiconductor device: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then... Agent: Martine Penilla & Gencarella, LLP

20080288899 - Techniques for use with automated circuit design and simulations: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP

20080288900 - Determination of single-fix rectification function: Some aspects provide determination of a function to rectify functional differences between netlist G1 and netlist G2 having inputs V. The determination may include determination of a signal s of netlist G1 that can be re-synthesized so as to correct the functional differences between netlist G1 and netlist G2, assignment... Agent: Buckley, Maschoff & Talwalkar LLC

20080288902 - Circuit design verification method and apparatus and computer readable medium: There is provided with a circuit design verification method including: accepting input of a circuit description which describes a circuit by using a plurality of conditional statements each including one or more conditional elements; extracting each conditional statement included in the circuit description and each conditional element included in the... Agent: Amin, Turocy & Calvin, LLP

20080288901 - Formally deriving a minimal clock-gating scheme: The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design... Agent: International Business Machines Corporation

20080288903 - Generating testcases based on numbers of testcases previously generated: An apparatus, computer system, and storage medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080288904 - Method for modeling and verifying timing exceptions: A method and system for timing exception verification in integrated circuit (IC) designs included verification of functional false paths as well as multi-cycle paths (MCPs). A false path or a MCP is modeled to a satisfiability formula and the formula is validated using a Boolean satisfiability solver. Time required for... Agent: Sughrue Mion, PLLC

20080288905 - Method and apparatus for congestion based physical synthesis: A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080288906 - Integrated system on module: An electronic product includes a circuit board, an integrated system on module, and an application-specific module. The integrated system on module and the application-specific module are integrated with the circuit board. A method of forming the circuit board is disclosed, as well as a method of forming the electronic product.... Agent: Merchant & Gould PC

20080288907 - Crosslinking of netlists: In one embodiment, a method for determining crosslinking between netlists is provided. The first netlist and second netlist may have nets that have different net names but may be the same net. It is also possible that the content of individual nets in one list may need to be split... Agent: Trellis Intellectual Property Law Group, PC

20080288908 - Simultaneous design of integrated circuit and printed circuit board: A printed circuit board (PCB) circuit assembly is designed utilizing software to create the best performing “total design” by selecting component layout locations, optimizing the circuit routing of the PCB copper (or other metallic) traces, and simultaneously optimizing the interconnections between a “standard” die inside an integrated circuit (IC) package... Agent: Knobbe Martens Olson & Bear LLP

20080288909 - Template-based domain-specific reconfigurable logic: A method is provided which creates an architecture of a reconfigurable logic core. The architecture can be deployed for various purposes and its implementation is costefficient in terms of area, performance and power. The invention relies on the perception that a template can be used to describe such an architecture.... Agent: Philips Intellectual Property & Standards

20080288910 - Structure for estimating power consumption of integrated circuitry: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the... Agent: Ibm Corp. (mad) C/o Davis Law Group, P.C.

20080288911 - Method for localizing faulty hardware components and/or system errors within a production plant: There is described a method for localizing faulty hardware components and/or system errors within a production plant comprising several hardware components, with the production plant and the individual hardware components thereof being managed and/or configured by means of automation software and with the production plant being visualized and/or controlled by... Agent: Siemens Corporation Intellectual Property Department

20080288912 - Method of inspecting mask using aerial image inspection apparatus: A method of precisely inspecting the entire surface of a mask at a high speed in consideration of optical effects of the mask. The method includes designing a target mask layout for a pattern to be formed on a wafer, and extracting an effective mask layout using an inspection image... Agent: Marger Johnson & Mccollom, P.C.

20080282206 - Structure for designing an integrated circuit having anti-counterfeiting measures: A design structure for an anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt... Agent: W. Riyon Harding International Business Machines Corporation

20080282208 - Integrated circuit having anti-counterfeiting measures: An article of manufacture, for example, a product or portion of a product produced by an IP design house which, when manufactured, causes random failures in a counterfeit integrated circuit. The article of manufacture (520) is a “genetic code” that comprises all of the necessary functional information needed to build... Agent: W. Riyon Harding International Business Machines Corporation

20080282207 - Method and system for conjunctive bdd building and variable quantification using case-splitting: A method, apparatus and computer-readable medium for conjunctive binary decision diagram building and variable quantification using case-splitting are presented. A BDD building program builds a BDD for at least one node in a netlist graph representation of a circuit design. One or more variables are selected for case-splitting. The variable... Agent: Dillon & Yudell LLP

20080282210 - System and method for product yield prediction: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at... Agent: Cantor Colburn, LLP

20080282209 - System for and method of verifying ic authenticity: A verification system disclosed herein uses the unique signatures of an IC to perform authentication of the IC after the IC is shipped to a customer. The verification system records the fingerprint and associated IC identifier with the fingerprint into a data structure. The data structure is supplied to the... Agent: Ibm Microelectronics Intellectual Property Law

20080282211 - Methodology to improve turnaround for integrated circuit design: A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations... Agent: International Business Machines Corporation Dept. 18g

20080282212 - System and method enabling circuit topology recognition with auto-interactive constraint application and smart checking: A computer implemented method is provided for interactive application of constraints to sub-circuits in a circuit design stored in a computer readable medium, comprising: receiving from a first designer a selection of a sub-circuit; receiving from the first designer a constraint; producing an information structure in computer readable medium that... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20080282213 - Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors: A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting... Agent: Cantor Colburn LLP - IBM Austin

20080282214 - Reconfigurable integrated circuit: A reconfigurable integrated circuit is provided which includes transistors and comprises a first switch with an input terminal, an output terminal, and a control terminal, a first memory with a memory cell connected to the control terminal of the first switch, a second switch capable of shutting down a power... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080282216 - Method for designing structured asics in silicon processes with three unique masking steps: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition... Agent: Bae Systems

20080282215 - Method of designing a digital integrated circuit for a multi-functional digital protective relay: This invention relates to a method of designing a digital integrated circuit for a multi-functional digital protective relay, emphasizing a digital module part, and input voltage and current signals are processed by a digital signal processor module to calculate the fundamental wave of the input voltage and current of protective... Agent: Charles G. Mersereau Nikolai & Merserau, P.A.

20080282217 - Method for creating mask layout data, apparatus for creating mask layout data, and method for manufacturing semiconductor device: According to mask layout data created for a particular factory facility, transistors constituting a semiconductor device are classified into multiple groups depending on the gate length. Thereafter, the concentration of impurity introduced into a channel layer is set for each group, and thereby the gate length-threshold characteristics of a transistor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080282218 - Method for designing mask: A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offspring... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080276205 - Computer program product for designing memory circuits having single-ended memory cells with improved read stability: A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a... Agent: Ryan, Mason & Lewis, LLP

20080276206 - Method for performing failure mode and effects analysis of an integrated circuit and computer program product therefor: A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information,... Agent: Heslin Rothenberg Farley & Mesiti PC

20080276207 - Modeling the skin effect using efficient conduction mode techniques: Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing... Agent: Klarquist Sparkman, LLP

20080276208 - Optimizing integrated circuit design through use of sequential timing information: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20080276209 - Optimizing integrated circuit design through use of sequential timing information: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20080276210 - Optimizing integrated circuit design through use of sequential timing information: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20080276211 - Method and apparatus for determining a process model using a 2-d-pattern detecting kernel: One embodiment provides a system for determining an improved process model that models one or more semiconductor manufacturing processes. During operation, the system can receive a first process model. Next, the system can receive a 2-D-pattern detecting kernel which can detect 2-D patterns. The system can then receive a second... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080276212 - Optimizing integrated circuit design through balanced combinational slack plus sequential slack: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for... Agent: Cadence Design Systems, Inc. C/o Duane Morris LLP (san Francisco)

20080276213 - Method of shield line placement for semiconductor integrated circuit, design apparatus for semiconductor integrated circuit, and design program for semiconductor integrated circuit: A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line with wiring information of a shield line placed for the signal line; an association information storage unit which stores the thus created association information; and a... Agent: Staas & Halsey LLP

20080276214 - Method and computer program for automated assignment and interconnection of differential pairs within an electronic package: Connection assignments of differential signals within an integrated circuit (IC) package are automatically made in the design and manufacturing process of the IC package, for use in automated computing systems. Either predefined pairs of pins at both ends or pairs of pins automatically paired or a combination of both are... Agent: Cantor Colburn LLP - IBM Rochester Division

20080276215 - Mask pattern designing method using optical proximity correction in optical lithography, designing device, and semiconductor device manufacturing method using the same: A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080276216 - Pattern forming method and system, and method of manufacturing a semiconductor device: A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP