Data processing: design and analysis of circuit or semiconductor mask inventions 10/08

20080263480 - Language and templates for use in the design of semiconductor products: During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character... Agent: Westman Champlin & Kelly, P.A.

20080263481 - Apparatus and methods for power management in integrated circuits: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.... Agent: Law Offices Of Maximilian R. Peterson

20080263484 - Layout verification program, layout data and cell data: A layout verification program recorded on a computer-readable medium causes a computer to perform verification processing of a layout data of a semiconductor integrated circuit in which a plurality of cells are placed. The layout data includes a first identification layer in which predetermined patterns are placed. The predetermined patterns... Agent: Foley And Lardner LLP Suite 500

20080263482 - Method and apparatus for small die low power system-on-chip design with intelligent power supply chip: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This... Agent: Fernandez & Associates LLP

20080263487 - Multi-format consistency checking tool: A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule... Agent: Silicon Edge Law Group, LLP

20080263483 - Optical proximity correction method, optical proximity correction apparatus, and optical proximity correction program, method of manufacturing semiconductor device, design rule formulating method, and optical proximity correction condition calculating met: In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of... Agent: Sonnenschein Nath & Rosenthal LLP

20080263486 - Various methods and apparatuses for cycle accurate c-models of components: Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of... Agent: Rutan & Tucker, LLP.

20080263485 - Verification support method and apparatus, and computer product: A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and... Agent: Staas & Halsey LLP

20080263490 - Apparatus and methods for optimizing the performance of programmable logic devices: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least... Agent: Law Offices Of Maximilian R. Peterson

20080263488 - Method for generating a skew schedule for a clock distribution network containing gating elements: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control... Agent: International Business Machines Corporation Dept. 18g

20080263489 - Method to identify and generate critical timing path test vectors: A method of testing critical paths in integrated circuits begins by simulating at least one operation of an integrated circuit chip design to produce chip timing data. Next, critical paths of the integrated circuit chip design are identified based on the chip timing data. The method applies functional test signals... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080263491 - Method for optimizing organizational floor layout and operations: A computer-automated method for analyzing an organizational floorplan layout, and making recommendations for modifying the layout to optimize productivity, and efficiency of operations conducted within the modified layout includes the following method steps. Gathering raw performance measure date comprising performance measures known to quantify the floorplan layout productivity and efficiency... Agent: Scully, Scott, Murphy & Presser, P.C.

20080263492 - 3-dimensional device design layout: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to... Agent: Slater & Matsil, L.L.P.

20080263493 - Method and apparatus for tie net routing: A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known... Agent: International Business Machines Corporation

20080263494 - Power supply wiring structure: Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings... Agent: Mcdermott Will & Emery LLP

20080263495 - Software product for semiconductor device design: A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured... Agent: Foley And Lardner LLP Suite 500

20080263496 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080263497 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080263498 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080263500 - Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method: An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from... Agent: Staas & Halsey LLP

20080263499 - Datapipe interpolation device: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for... Agent: Hovey Williams LLP

20080263501 - System, method, and computer-readable medium for performing data preparation for a mask design: A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response... Agent: Haynes And Boone, LLP

20080263502 - Mask pattern data generating method, information processing apparatus, photomask fabrication system, and image sensing apparatus: A method for generating mask pattern data of a photomask used to form microlenses divides a pattern formation surface of a mask pattern to be used for the photomask into a plurality of grid cells, acquires data which represents transmitted light distribution of the mask pattern to be used for... Agent: Fitzpatrick Cella Harper & Scinto

20080263480 - Language and templates for use in the design of semiconductor products: During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character... Agent: Westman Champlin & Kelly, P.A.

20080263481 - Apparatus and methods for power management in integrated circuits: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.... Agent: Law Offices Of Maximilian R. Peterson

20080263484 - Layout verification program, layout data and cell data: A layout verification program recorded on a computer-readable medium causes a computer to perform verification processing of a layout data of a semiconductor integrated circuit in which a plurality of cells are placed. The layout data includes a first identification layer in which predetermined patterns are placed. The predetermined patterns... Agent: Foley And Lardner LLP Suite 500

20080263482 - Method and apparatus for small die low power system-on-chip design with intelligent power supply chip: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This... Agent: Fernandez & Associates LLP

20080263487 - Multi-format consistency checking tool: A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule... Agent: Silicon Edge Law Group, LLP

20080263483 - Optical proximity correction method, optical proximity correction apparatus, and optical proximity correction program, method of manufacturing semiconductor device, design rule formulating method, and optical proximity correction condition calculating met: In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of... Agent: Sonnenschein Nath & Rosenthal LLP

20080263486 - Various methods and apparatuses for cycle accurate c-models of components: Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of... Agent: Rutan & Tucker, LLP.

20080263485 - Verification support method and apparatus, and computer product: A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and... Agent: Staas & Halsey LLP

20080263490 - Apparatus and methods for optimizing the performance of programmable logic devices: A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least... Agent: Law Offices Of Maximilian R. Peterson

20080263488 - Method for generating a skew schedule for a clock distribution network containing gating elements: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control... Agent: International Business Machines Corporation Dept. 18g

20080263489 - Method to identify and generate critical timing path test vectors: A method of testing critical paths in integrated circuits begins by simulating at least one operation of an integrated circuit chip design to produce chip timing data. Next, critical paths of the integrated circuit chip design are identified based on the chip timing data. The method applies functional test signals... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080263491 - Method for optimizing organizational floor layout and operations: A computer-automated method for analyzing an organizational floorplan layout, and making recommendations for modifying the layout to optimize productivity, and efficiency of operations conducted within the modified layout includes the following method steps. Gathering raw performance measure date comprising performance measures known to quantify the floorplan layout productivity and efficiency... Agent: Scully, Scott, Murphy & Presser, P.C.

20080263492 - 3-dimensional device design layout: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to... Agent: Slater & Matsil, L.L.P.

20080263493 - Method and apparatus for tie net routing: A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known... Agent: International Business Machines Corporation

20080263494 - Power supply wiring structure: Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings... Agent: Mcdermott Will & Emery LLP

20080263495 - Software product for semiconductor device design: A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured... Agent: Foley And Lardner LLP Suite 500

20080263496 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080263497 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080263498 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080263500 - Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method: An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from... Agent: Staas & Halsey LLP

20080263499 - Datapipe interpolation device: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for... Agent: Hovey Williams LLP

20080263501 - System, method, and computer-readable medium for performing data preparation for a mask design: A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response... Agent: Haynes And Boone, LLP

20080263502 - Mask pattern data generating method, information processing apparatus, photomask fabrication system, and image sensing apparatus: A method for generating mask pattern data of a photomask used to form microlenses divides a pattern formation surface of a mask pattern to be used for the photomask into a plurality of grid cells, acquires data which represents transmitted light distribution of the mask pattern to be used for... Agent: Fitzpatrick Cella Harper & Scinto

20080256498 - Method and apparatus for logic equivalence verification, and computer product: A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The... Agent: Staas & Halsey LLP

20080256497 - Scan compression circuit and method of design therefor: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines... Agent: Silicon Valley Patent Group LLP

20080256499 - Using constraints in design verification: A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states... Agent: Dillon & Yudell LLP

20080256500 - Integrated opc verification tool: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction,... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20080250362 - Method and system product for implementing uncertainty in integrated circuit designs with programmable logic: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic... Agent: Harrington & Smith, PC

20080250360 - Method for generating compiler, simulation, synthesis and test suite from a common processor specification: A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions... Agent: Oppenheimer Wolff & Donnelly LLP

20080250361 - Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same: In an apparatus and method for automatically correcting a design pattern in view of different process defects, defect characteristic functions that indicate frequencies of each process defect independent from one another are generated, and a normalization factor that indicates relationships between the defect characteristic functions is determined. A general defect... Agent: Mills & Onello LLP

20080250365 - Circuit state scan-chain, data collection system and emulation and verification method: The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and the corresponding input terminal combinational logics and output terminal combinational logics. The... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080250363 - Design support apparatus for semiconductor devices: A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation... Agent: Buchanan, Ingersoll & Rooney PC

20080250364 - Method and system for verification of multi-voltage circuit design: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080250366 - Noise checking method and apparatus, and computer-readable recording medium in which noise checking program is stored: There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the large cell and are added to chip... Agent: Staas & Halsey LLP

20080250371 - Delay budget allocation with path trimming: Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of the edges based on required arrival time and design slack (S,T) pairs associated... Agent: Law Offices Of Mark L. Berrier

20080250368 - Inductance mitigation through switching density analysis: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock... Agent: Courtney Staniford & Gregory LLP

20080250372 - Method and a computer readable medium for analyzing a design of an integrated circuit: A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events,... Agent: Freescale Semiconductor, Inc. Law Department

20080250369 - Method of estimating the signal delay in a vlsi circuit: This invention relates to a method of estimating the signal delay in a VLSI circuit and accurately estimating the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.... Agent: Alan Kamrath Kamrath & Associates, P.A.

20080250367 - Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry: Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive... Agent: Ibm Burlington (anthony England) C/o Law Office Of Anthony England

20080250370 - Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits: An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is... Agent: Hoffman Warnick LLC

20080250373 - Optimizing asic pinouts for hdi: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer... Agent: Patterson & Sheridan, LLP/cisc

20080250374 - Method of making an integrated circuit: A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell... Agent: Freescale Semiconductor, Inc. Law Department

20080250375 - Detailed placer for optimizing high density cell placement in a linear runtime: A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two... Agent: Bever, Hoffman & Harms, LLP

20080250376 - Integrating a boolean sat solver into a router: One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080250377 - Conductive dome probes for measuring system level multi-ghz signals: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer... Agent: Patterson & Sheridan, LLP/cisc

20080250378 - Circuit emulation and debugging method: A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals... Agent: Smith-hill And Bedell, P.C.

20080250379 - Logic circuit synthesis device: In a logic circuit synthesis device, a library of cell preliminarily stores a condition concerning a property that should be satisfied by the net having the property. The logic circuit synthesis device selects, from a list of nets, a net that has a predetermined property. the logic circuit synthesis device... Agent: Mcdermott Will & Emery LLP

20080250380 - Method of opc model building, information-processing apparatus, and method of determining process conditions of semiconductor device: A method capable of quantitatively evaluating two-dimensional patterns and a system to which the method is applied are provided. In the present invention, a reference coordinate system is set in order to convert pattern edge information (one-dimensional data) acquired by measurement using an existing critical dimension machine into coordinate data.... Agent: Crowell & Moring LLP Intellectual Property Group

20080250381 - Parameter adjustment method, semiconductor device manufacturing method, and recording medium: A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080250382 - Semiconductor device manufacturing method: A yielding percentage is calculated based on a first relationship, a probability distribution and a second relationship. The first relationship is a relationship between measurement values of a transfer pattern formed on a semiconductor substrate provided in the semiconductor device in the semiconductor lithographic process and number of sections on... Agent: Mcdermott Will & Emery LLP

20080250383 - Method for designing mask pattern and method for manufacturing semiconductor device: A mask pattern designing method capable of achieving the reduction in the increasing OPC processing time, shortening the manufacture TAT of a semiconductor device, and achieving the cost reduction is provided. An OPC (optical proximity correction) process at the time when a cell is singularly arranged is performed to a... Agent: Reed Smith LLP

20080250384 - Systems and methods for creating inspection recipes: Systems and methods for creating inspection recipes are provided. One computer-implemented method for creating an inspection recipe includes acquiring a first design and one or more characteristics of output of an inspection system for a wafer on which the first design is printed using a manufacturing process. The method also... Agent: Baker & Mckenzie LLP

20080244471 - System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger... Agent: Abelman, Frayne & Schwab

20080244474 - Cell library management for power optimization: A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of... Agent: Christopher P Maiorana, PC Lsi Corporation

20080244472 - Method for accelerating the generation of an optimized gate-level representation from a rtl representation: A method for accelerating the generation of an optimized netlist from a RTL representation is provided. The method optimizes a given RTL description of an integrated circuit (IC) design by: generating a static single assignment (SSA) graph; creating value range propagation for each variable in the SSA graph; and, applying... Agent: Sughrue Mion, PLLC

20080244473 - Modifying integrated circuit designs to achieve multiple operating frequency targets: A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit... Agent: Ryan, Mason & Lewis, LLP

20080244478 - Model generation method and model generation apparatus of semiconductor device: A model generation method for generating a semiconductor device model used for power supply noise analysis, is performed by, calculating noise values for various circuit elements based on current source noise waveforms calculated in accordance with a current flowing from a power supply when a state of the elements changes,... Agent: Greer, Burns & Crain

20080244475 - Network based integrated circuit testline generator: A network based integrated circuit testline generating system and method of using the same is described. The system includes a user interface for generating and submitting requests which specify types and configurations of needed testlines for device parametric test. A testline generator receives the requests and creates a layout data... Agent: Slater & Matsil, L.L.P.

20080244477 - Simulation model for a semiconductor device describing a quasi-static density of a carrier as a non-quasi-static model: There is disclosed a simulation model and method for designing a semiconductor device being used for a simulation apparatus for designing a semiconductor device that includes using assuming units as to carrier transient density and current flow of electrodes along with a non-quasi-static model describing unit of the simulation apparatus.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080244479 - Structure for intrinsic rc power distribution for noise filtering of analog supplies: A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance... Agent: Greenblum & Bernstein, P.L.C

20080244476 - System and method for simultaneous optimization of multiple scenarios in an integrated circuit design: The present invention provides a system and method for concurrently performing analysis and optimization of an integrated circuit (IC) design in multiple scenarios. The system is based on a distributed computing model, where any optimization change introduced in one scenario is immediately tested in all other scenarios. This ensures that... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080244485 - Capacitance modeling: A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-clip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a... Agent: Scully, Scott, Murphy & Presser, P.C.

20080244484 - Circuit design verification system, method and medium: A common-signal-terminal extracting section extracts common signal terminals from a netlist of the semiconductor device. An information converting section replaces the information of circuit components connected to the extracted common signal terminals by electric property information with reference a circuit-component library. A conformity detecting section determines whether or not the... Agent: Jackson Chen Nec Corporation Of America

20080244482 - Integrated circuit design usage and sanity verification: An automated system and method for sanity checking an integrated circuit cell layout. The method generally includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference... Agent: Haynes And Boone, LLP

20080244483 - Integrated circuit design usage and sanity verification: A method and system for verifying an integrated circuit design are provided. The method includes identifying cell tags embedded in a proposed integrated circuit design file, comparing cells identified as having a tag embedded therein to a cell library containing verified cell data to determine differences between the identified tagged... Agent: Haynes And Boone, LLP

20080244481 - Method for designing and manufacturing semiconductor device and software therefor: A method for designing a semiconductor device including a semiconductor substrate and an interconnect on the semiconductor substrate, with X-direction being one direction parallel to the semiconductor substrate, Y-direction being a direction parallel to the semiconductor substrate and perpendicular to the X-direction, and Z-direction being perpendicular to the semiconductor substrate,... Agent: Pearne & Gordon LLP

20080244487 - Delay analysis support apparatus, delay analysis support method and computer product: A delay analysis support apparatus that supports analysis of delay in a target circuit includes an acquiring unit that acquires error information concerning a cell-delay estimation error that is dependent on a characterizing tool; an error calculating unit that calculates, based on the error information and a first probability density... Agent: Staas & Halsey LLP

20080244486 - Integrated circuit generating device, method therefor, and program: An integrated-circuit generating device for generating an integrated circuit including an adjusting mechanism for adjusting timings of values sequentially outputted from circuits operating in parallel. The device includes a test-circuit storing section for storing test circuit information for validating the integrated circuit, a circuit-information storing section for storing circuit information,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080244488 - Method for laying out decoupling cells and apparatus for laying out decoupling cells: A method for laying out decoupling cells in a semiconductor integrated circuit including a plurality of paths. The method includes extracting from a timing analysis result a timing slack amount as a timing margin for power supply noise in one of the paths serving as a target path, converting the... Agent: Staas & Halsey LLP

20080244489 - Method and apparatus for designing a three-dimensional integrated circuit: A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080244490 - Sequence-pair creating apparatus and sequence-pair creating method: A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block bi in a block set B and information of block placement, creates a sequence-pair (P, M), serving as a pair of a sequence P and a sequence M of the block bi,... Agent: Edwards Angell Palmer & Dodge LLP

20080244492 - Apparatus and method for designing system, and computer readable medium: There is provided with a designing apparatus, including: an input accepting unit configured to accept an input of design description which describes a design of a system that includes components and a plurality of channels each of which connects between components communicating with each other; component constraint description which describes... Agent: Amin, Turocy & Calvin, LLP

20080244491 - Generic methodology to support chip level integration of ip core instance constraints in integrated circuits: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes... Agent: Lsi Logic Corporation Henry Groth

20080244493 - Pattern based elaboration of hierarchical l3go designs: A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical... Agent: Hoffman Warnick LLC

20080244495 - Method of determining wire pattern on board and board designed by the method: A method of determining a wire pattern 11 formed by a plurality of wires W1, W3-W6, W9, and W10 on a board, the method including: an area-graph constructing step of forming an area-graph 12 in the routing area 10, the area-graph 12 having pins P1-P10 and edges B1-B16 connecting the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080244494 - Migration of integrated circuit layout for alternating phase shift masks: Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to phase compliance, jogs are identified on a first (AltPSM) layer and shifted to another second layer. Isolated or clustered jogs... Agent: Hoffman Warnick LLC

20080244496 - Layout design device and layout method: A layout design device according to an exemplary aspect of the present invention is a layout design device for designing layout of an integrated circuit, including a routing section for adjacently wiring a signal line having a high activity rate and a signal line having a low activity rate based... Agent: Nec Corporation Of America

20080244497 - On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise: A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and... Agent: Dillon & Yudell LLP

20080244499 - Apparatus and design method for circuit of semiconductor device etc: A design apparatus comprises a unit generating a new-via-formable overlapped area between a first wiring pattern and a second wiring pattern by extending, in a predetermined direction, at least one of the first wiring pattern included in a first wiring layer and the second wiring pattern connected by a via... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080244498 - Netlist synthesis and automatic generation of pc board schematics: A computer implemented method and system for automatically generating a net list for a printed circuit board are described. Selection of one or more pins on a first and second component to be connected is based on one or more of a logical definition, an electrical definition, a distance property,... Agent: Osha Liang L.L.P.

20080244500 - System, methods and apparatuses for integrated circuits for nanorobotics: The invention describes apparatuses for nano-scale integrated circuits applied to nanorobotics. Using EDA techniques, the system develops fully functional nano ICs, including ASICs and microprocessors. Three dimensional nano ICs are disclosed for increased efficiency in nanorobotic apparatuses. Nano-scale FPGAs are disclosed. The nano-scale semiconductors have applications to nano-scale and micro-scale... Agent: Neal Solomon

20080244501 - Method for reading information from a hierarchical design: The present invention relates to a method for obtaining physical component information that is associated with hierarchical and non-hierarchical symbols as represented within a logical schematic diagram. The method comprises extracting logical design data of a hierarchical schematic from a primary software application, identifying a hierarchical symbol for analysis, and... Agent: Cantor Colburn LLP - IBM Rochester Division

20080244502 - System for and method of supporting logic design: A logic design support system which supports logic design using an HDL includes: RTL analysis means for receiving, as input, an RTL including a dedicated comment as a comment statement specifying expansion of a generate statement, detecting the dedicated comment from the input RTL, and retrieving a generate statement to... Agent: Nec Corporation Of America

20080244503 - System for coloring a partially colored design in an alternating phase shift mask: A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases... Agent: Law Office Of Delio & Peterson, LLC.

20080244504 - Method and apparatus for determining mask layouts for a multiple patterning process: One embodiment provides a method for determining mask layouts. During operation, the system can receive a design intent. Next, the system can determine a set of critical edges in the design layout, and select a first edge and a second edge. The system can then determine a first trench and... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080244480 - System and method to generate an ic layout using simplified manufacturing rule: Some embodiments of the invention provide a system and method where a physical design (“PD”) process can use simplified manufacturing rules to generate an integrated circuit (“IC”) layout. A layout optimization process transforms the PD generated layout to become more manufacturing rule compliant layout using a full set of manufacturing... Agent: Marko Chew