Data processing: design and analysis of circuit or semiconductor mask inventions 09/08

20080235635 - System on chip development with reconfigurable multi-project wafer technology: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is... Agent: K & L Gates LLP

20080235638 - Design structure for radiation hardened programmable phase frequency divider circuit: A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback... Agent: Ibm Corporation

20080235636 - Identifying radiation-induced inversions: A semiconductor layout design analyzer alerts a user of areas in a semiconductor layout design that may be candidates for radiation induced inversion. The analyzer includes means for gathering information, means for identifying, and means for alerting the user. The means for gathering gathers, from the layout design, placement information... Agent: Hanes & Schutz, LLC

20080235637 - Method for heuristic preservation of critical inputs during sequential reparameterization: A method, system, and computer program product for preserving critical inputs. According to an embodiments of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state... Agent: Dillon & Yudell LLP

20080235639 - Method of generating a functional design structure: A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor.... Agent: W. Riyon Harding International Business Machines Corporation

20080235641 - Critical area computation of composite fault mechanisms using voronoi diagrams: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080235640 - Method and apparatus for performing static analysis optimization in a design verification system: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively... Agent: Raymond R. Moser Jr., Esq. MoserIPLaw Group

20080235642 - Method and apparatus for localized planning in an integrated circuit: A method for an improved circuit design is provided. The method comprises the steps of: provide a core ring around a circumference of a circuit design; determining at least two stages of the circuit design; identifying a set of macros for at least one stage; and placing the set of... Agent: Franklin (lin) Yang

20080235643 - Method and system for reducing inter-layer capacitance in integrated circuits: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer.... Agent: Lsi Corporation

20080235644 - Semiconductor integrated circuit with multi-cut via and automated layout method for the same: A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080235645 - Method and apparatus for detecting lithographic hotspots: Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration... Agent: Greer, Burns & Crain

20080235646 - Spacers for reducing crosstalk and maintaining clearances: In one aspect of the invention is a method for reducing crosstalk and maintaining clearances between traces on a printed circuit board design. Crosstalk caused by placing traces a virtual printed circuit board are reduced by placing artificial obstructs, called spacers, between traces and/or between traces and nets to create... Agent: Banner & Witcoff, Ltd.

20080235647 - Modular design method and apparatus: Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further... Agent: Ibm Corporation (cs) C/o Carr LLP

20080235648 - Program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs: A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of... Agent: Dillon & Yudell LLP

20080235649 - Method of designing semiconductor integrated circuit, apparatus for designing semiconductor integrated circuit, recording medium, and mask manuacturing method: A method of designing a semiconductor integrated circuit includes a cell arranging and wiring step of arranging and wiring cells for creating a physical layout, a design-rule checking step of verifying a shape of a second physical layout including the cells of the physical layout with reference to a rule... Agent: Sonnenschein Nath & Rosenthal LLP

20080235650 - Pattern creation method, mask manufacturing method and semiconductor device manufacturing method: A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080235652 - Lithography method for forming a circuit pattern: A lithography method for suppressing resist scum includes the steps of designing an original layout with line patterns and pad patterns, extracting a pad patternlayout from the original, layout, obtaining a first reduction layout which is reduced by a first reduction width relative to the pad pattern layout, obtaining a... Agent: Marshall, Gerstein & Borun LLP

20080235651 - Method and apparatus for determining an optical model that models the effects of optical proximity correction: One embodiment provides a system that can enable a designer to determine the effects of subsequent processes at design time. During operation, the system may receive a test layout and an optical model that models an optical system, but which does not model the effects of subsequent processes, such as... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080229259 - Design flow for shrinking circuits having non-shrinkable ip layout: A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second... Agent: Slater & Matsil, L.L.P.

20080229260 - Structure for automated transistor tuning in an integrated circuit design: A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled... Agent: Dillon & Yudell LLP

20080229262 - Design rule management method, design rule management program, rule management apparatus and rule verification apparatus: Disclosed is a rule management apparatus which acquires a design rule for regulating a part shape from systems such as a CAD system 401, converts the acquired deign rule into data having a hierarchical node format, calculates relationship strength which indicates strength of a relationship between the design rule converted... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080229261 - Design rule system for verifying and enforcing design rules in software: A software design rule system is provided. The software design rule system can employ a rule language that enables software developers to model valid interactions between multiple, inter-related objects; provide a rule verifier component that determines whether design rules achieve their intended purpose; and provide a rule enforcer component that... Agent: Perkins Coie LLP/msft

20080229263 - Performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver: A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable depth. A composite target is verified, using a... Agent: Dillon & Yudell LLP

20080229265 - Design structure for a clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees: Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and... Agent: Downs Rachlin Martin PLLC

20080229266 - Design structure for a clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees: Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have... Agent: Downs Rachlin Martin PLLC

20080229264 - Semiconductor evaluation apparatus, semiconductor evaluation method and semiconductor evaluation program: The present invention provides a semiconductor evaluation apparatus. The semiconductor evaluation apparatus includes: a first integrated circuit; a second integrated circuit; a test section; a measurement section; and a computation section for determining whether a device is good or defective based on sets of power supply voltage and clock period.... Agent: Rader Fishman & Grauer PLLC

20080229267 - Method and system for developing post-layout electronic data automation (eda) applications: A method and system for processing geometrical layout design data to manufacture an electronic circuit is provided. The method includes extracting the geometrical layout design data from one or more data-format files. The method further includes segregating the geometrical layout design data extracted from one or more data-format files into... Agent: GlobalIPServices, PLLC

20080229270 - Design structure for a duty cycle correction circuit: A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080229269 - Design structure for integrating nonvolatile memory capability within sram devices: A design structure embodied in a machine readable medium used in a design process includes a nonvolatile static random access memory (SRAM) device, including a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; and a pair of magnetic spin... Agent: Cantor Colburn LLP-ibm Burlington

20080229268 - Trace optimization in flattened netlist by storing and retrieving intermediate results: A method of trace optimization in a flattened netlist of a circuit is disclosed. The method generally includes the steps of (A) generating a first total result by tracing a first path through the flattened netlist, (B) writing an intermediate result in a memory, the intermediate result characterizing a module... Agent: Christopher P Maiorana, PC Lsi Corporation

20080229271 - Data aligner in reconfigurable computing environment: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC

20080229272 - Data aligner in reconfigurable computing environment: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC

20080229273 - Systems and methods for uv lithography: A method of designing a lithographic mask for use in lithographic processing of a substrate is disclosed. The lithographic processing comprises irradiating mask features of a lithographic mask using a predetermined irradiation configuration. In one aspect, the method comprises obtaining an initial design for the lithographic mask comprising a plurality... Agent: Knobbe Martens Olson & Bear LLP

20080222576 - Design support apparatus, method for supporting design, and medium recording design support program: A design support apparatus and method generating design data of a circuit and updating the design data, storing the design data and update history data representing an update content in association with an updated circuit component when the design data is updated. The disclosed apparatus and method include receiving an... Agent: Staas & Halsey LLP

20080222577 - Method for designing array antennas: A method for designing low signature array antennas using a calculation method. The method proposes a way of improving antenna and signature performance of array antennas. According to the method electromagnetic antenna and signature characteristics are specified, an iterative optimizing method is performed to design the antenna to fulfil the... Agent: Venable LLP

20080222578 - System and method for circuit design scaling: A system and method for scaling a circuit design to a new technology includes designating a first set of components including design scaled elements having a designed scaling in two dimensions to render the first set of components inactive for scaling of a second set of components. The second set... Agent: Keusey, Tutunjian & Bitetto, P.c.

20080222579 - Moment-based method and system for evaluation of metal layer transient currents in an integrated circuit: A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes include peak, rms and average current, which can be used in subsequent reliability analyses. Interconnect... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.l.c.

20080222580 - Moment-based method and system for evaluation of metal layer transient currents in an integrated circuit: A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and... Agent: Legal Department Mips Technologies, Inc.

20080222581 - Remote interface for managing the design and configuration of an integrated circuit semiconductor design: A software system for facilitating the design process and minimizing the time and effort required to complete the design and fabrication of an integrated circuits (IC) is described. The software system utilizes a data center having a plurality of repositories, rules engines and design and verification tools to automatically produce... Agent: Legal Department Mips Technologies, Inc.

20080222582 - System and method for automated electronic device design: A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher quality of results. Such a system as analysis methods, techniques, and tools, a knowledge database, a design database a controller and... Agent: Sprinkle Ip Law Group

20080222585 - Interleaved voltage controlled oscillator: A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element... Agent: Cantor Colburn LLP - Ibm Austin

20080222583 - Method and system for logic verification using mirror interface: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost... Agent: Connolly Bove Lodge & Hutz LLP (for Ibm Yorktown)

20080222584 - Method in a computer-aided design system for generating a functional design model of a test structure: A method in a computer-aided design system for generating a functional design model of a test structure. The test structure is used for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip generated from the functional design model is tested individually without excessive test time... Agent: W. Riyon Harding International Business Machines Corporation

20080222586 - Delay analysis apparatus, delay analysis method and computer product: Within-die delay distributions and die-to-die delay distributions of two arbitrary paths in an analysis target circuit are extracted from a delay distribution library, and an effect index indicative of a relative error of an overall path delay distribution of one path and an overall path delay distribution when the two... Agent: Staas & Halsey LLP

20080222587 - Integrated circuit cell library for multiple patterning: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are... Agent: Martine Penilla & Gencarella, LLP

20080222588 - Method and program for designing semiconductor device: A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver... Agent: Mcginn Intellectual Property Law Group, Pllc

20080222589 - Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design: A system and method for facilitating the design process of an integrated circuits (IC) is described. The system and method utilizes a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the IC. Synthesizable... Agent: Legal Department Mips Technologies, Inc.

20080222590 - Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caring: An improved method, system and computer-readable medium for constructing binary decision diagrams for a netlist graph is disclosed. The method comprises traversing a netlist graph in a depth-first manner. At least one binary decision diagram is built for one input of a node of the netlist graph using a binary... Agent: Dillon & Yudell LLP

20080222591 - Signal connection program, method, and device of hierarchical logic circuit: Information of a logic circuit including a hierarchical structure and connection target information up to a connection target including a pin or a net via hierarchies of the logic circuit are read, and a tree structure in which a hierarchy is taken as a node and a connection target is... Agent: Staas & Halsey LLP

20080222592 - Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method: A semiconductor integrated circuit including a user logic circuit is disclosed in which circuit parts for shifting data are composed of registers other than scan cells except for the circuit part right after a combinational circuit, and the parts configured of the registers other than the scan cells are used... Agent: Dickstein Shapiro LLP

20080222593 - Design method, recording medium, and design support system: A design method includes creating power supply planes in each layer of a circuit board, from CAD data of the circuit boards whereby the power supply planes form one power supply conductor interconnect and supply power or connect to ground, expanding the shape of the power supply planes by a... Agent: Staas & Halsey LLP

20080222594 - Method and apparatus for aligning multiple outputs of an fpga: Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being... Agent: Anderson Gorecki & Manaras, LLP Attn: John C. Gorecki

20080222595 - Method of engineering change to semiconductor circuit executable in computer system: A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second... Agent: Kirton And Mcconkie

20080222596 - Method of shrinking semiconductor mask features for process improvement: Provided is a method to design an integrated circuit. The method reduces a time delay between introduction of a new lithography process and a start of production. A first semiconductor mask is designed at a first process feature size. The first process feature size can be based on an anticipated... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080222597 - Photo mask, exposure method using the same, and method of generating data: A photo mask formed with patterns to be transferred to a substrate using an exposure apparatus, the photo mask comprising a pattern row having three or more hole patterns surrounded by a shielding portion or a semitransparent film and arranged along one direction, and an assist pattern surrounded by the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080216024 - Method and apparatus for allocating data paths: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used,... Agent: Baker Botts L.L.P.

20080216026 - Integrated circuit layout design supporting device: Provided is an integrated circuit layout design supporting device which can reduce the wiring length by avoiding bypass wirings when a plurality of same-type macro blocks are used. The integrated circuit layout design supporting device includes a terminal coordinate calculation control unit and a layout processing control unit. The terminal... Agent: Sughrue Mion, PLLC

20080216025 - Tunneling as a boundary congestion relief mechanism: Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through... Agent: Walstein Bennett Smith Iii

20080216027 - Electronic design for integrated circuits based on process related variations: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature... Agent: VistaIPLaw Group LLP

20080216031 - Design structures for semiconductor structures with error detection and correction: A design structure including design data describing a semiconductor structure. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second... Agent: Schmeiser, Olsen & Watts

20080216028 - Fast evaluation of average critical area for ic: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080216029 - Method and system for performing target enlargement in the presence of constraints: A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers... Agent: Dillon & Yudell LLP

20080216032 - Methods and apparatuses for automated circuit optimization and verification: Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080216030 - System for performing verification of logic circuits: t

20080216033 - Design structure for time based driver output transition (slew) rate compensation: A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal,... Agent: Greenblum & Bernstein, P.L.C

20080216035 - Method and computer program for configuring an integrated circuit design for static timing analysis: A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The... Agent: Lsi Corporation Corporate Legal Department

20080216034 - Performance visualization of delay in circuit design: Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of... Agent: Martine Penilla & Gencarella, LLP

20080216036 - Slack sensitivity to parameter variation based timing analysis: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing,... Agent: Hoffman Warnick LLC

20080216037 - System for using partitioned masks to build a chip: A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a... Agent: Hoffman Warnick LLC

20080216038 - Timing driven force directed placement flow: Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces.... Agent: Walstein Bennett Smith Iii

20080216039 - Node spreading via artificial density enhancement to reduce routing congestion: Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through... Agent: Walstein Bennett Smith Iii

20080216040 - Incremental relative slack timing force model: Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through... Agent: Walstein Bennett Smith Iii

20080216041 - Integrated circuit simulation method considering stress effects: Provided is an integrated circuit (IC) simulation method which can predict the operation and performance of an IC considering stress effects that affect the characteristics of unit devices included in the IC. The method includes drawing out a first net list of unit devices included in a designed IC; preparing... Agent: Myers Bigel Sibley & Sajovec

20080216042 - Method and computer system for otimizing the signal time behavior of an electronic circuit design: A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which... Agent: W. Riyon Harding International Business Machines Corporation

20080216044 - Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights: In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different... Agent: Dillon & Yudell LLP

20080216043 - Structure for optimizing the signal time behavior of an electronic circuit design: A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree... Agent: W. Riyon Harding International Business Machines Corporation

20080216047 - Intermediate layout for resolution enhancement in semiconductor fabrication: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments... Agent: Fenwick & West LLP

20080216045 - Mask data processing method for optimizing hierarchical structure: Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080216046 - Pattern management method and pattern management program: A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080216048 - Yield profile manipulator: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.