|Data processing: design and analysis of circuit or semiconductor mask patents - Monitor Patents|
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Data processing: design and analysis of circuit or semiconductor mask August list of inventions 08/08Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/28/2008 > patent applications in patent subcategories. list of inventions
20080209364 - Method for storing multiple levels of design data in a common database: An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The... Agent: Pillsbury Winthrop Shaw Pittman LLP
20080209366 - Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model: Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent... Agent: Perman & Green
20080209367 - Reliability design method: The reliability design method of this invention includes an aged deterioration target extracting step of obtaining a deterioration part where a characteristic is deteriorated through aging in a semiconductor integrated circuit device having a structure corresponding to an initial mask layout pattern; an aged deterioration executing step of creating a... Agent: Mcdermott Will & Emery LLP
20080209365 - Yield analysis and improvement using electrical sensitivity extraction: A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks... Agent: Hamilton & Terrile, LLP
20080209369 - Device, method, and storage for verification scenario generation, and verification device: A verification scenario generation device including a first input unit which accepts input of a device list showing devices connected with a circuit to be verified, parameter setting information for the devices, and a test bench combination list corresponding to the devices, a test bench library which holds the test... Agent: Staas & Halsey LLP
20080209370 - Formally proving the functional equivalence of pipelined designs containing memories: One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next,... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP
20080209368 - Layout design method, layout design apparatus, and computer product: An apparatus for designing the layout of a circuit includes an acquiring unit, a determining unit, a specifying unit, an arranging unit, a modifying unit, and a routing unit. Based on net information acquired by the acquiring unit, the determining unit determines a wiring block of signal paths connecting cells... Agent: Staas & Halsey LLP
20080209371 - Logic cell configuration processing method and program: A logic cell configuration processing method for a CMOS semiconductor is configured in which leak current per unit width equal for P-channel and N-channel MOS transistors, by calculating a probable average leak current, which is an expected value of leak current of the P-channel MOS transistor and the N-channel MOS... Agent: Staas & Halsey LLP
20080209372 - Estimation of process variation impact of slack in multi-corner path-based static timing analysis: A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing... Agent: Downs Rachlin Martin Pllc
20080209373 - Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect... Agent: Hoffman Warnick Llc
20080209374 - Parameter ordering for multi-corner static timing analysis: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across... Agent: Downs Rachlin Martin Pllc
20080209376 - System and method for sign-off timing closure of a vlsi chip: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design... Agent: International Business Machines Corporation Dept. 18g
20080209375 - Variable threshold system and method for multi-corner static timing analysis: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a... Agent: Downs Rachlin Martin Pllc
20080209377 - Verification method, verification apparatus, and program: A verification method for verifying an asynchronous circuit includes producing a netlist based on circuit information at a register transfer level, extracting delay information and an asynchronous circuit section in which circuits operating with different clock signals are coupled to each other from the netlist, processing the delay information to... Agent: Staas & Halsey LLP
20080209380 - Device and method for high-level synthesis: A high-level synthesis unit creates a first register transfer level circuit from an operation level description. A circuit creating unit creates a second register transfer level circuit based on circuit information for creating an additional circuit to be added to the first register transfer level circuit. A circuit connecting unit... Agent: Mcdermott Will & Emery LLP
20080209378 - Method and system for prototyping electronic devices with multi-configuration chip carriers: A solution for prototyping electronic devices is proposed. The solution uses a carrier which allows mounting the desired components with different configurations. In order to achieve this result, for some of these components, such as discrete capacitors, the carrier includes more contacts than the corresponding terminals. In this way, each... Agent: International Business Machines Corporation Dept. 18g
20080209379 - Method of designing semiconductor integrated circuit, design device, and cad program: A semiconductor integrated circuit design device capable of carrying out design by evaluating a crosstalk between blocks has been disclosed. The integrated circuit design device is adapted to design a semiconductor integrated circuit having a plurality of blocks and comprises a virtual noise source setting PORTION that sets a virtual... Agent: Staas & Halsey LLP
20080209381 - Shallow trench isolation dummy pattern and layout method using the same: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the... Agent: Thomas, Kayden, Horstemeyer & Risley LLP
20080209382 - Stitched ic chip layout design structure: Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched... Agent: Hoffman Warnick Llc
20080209384 - Method of searching for wiring route in integrated circuit, automatic wiring device for integrated circuit, and program therefor: A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been found to be changed after the design has advanced and of easily obtaining an... Agent: Staas & Halsey LLP
20080209383 - Reverse routing methods for integrated circuits having a hierarchical interconnect architecture: The present invention relates to methods for the global and detail routing of integrated circuits with hierarchical interconnect routing architecture. The methods includes the steps of: mapping routing resources of said integrated circuit to the nodes and edges of a graph theoretic tree, mapping each target to a target node;... Agent: Emil Chang Law Offices Of Emil Chang
20080209385 - Mapping programmable logic devices: Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path... Agent: Sadler, Breen, Morasch & Colby, Ps
20080209386 - Method for predicting resist pattern shape, computer readable medium storing program for predicting resist pattern shape, and computer for predicting resist pattern shape: The contour shape of an aerial image formed on a resist by projecting a test pattern onto the resist via a projection optical system is computed. The shape of a resist pattern formed by the exposure using the test pattern and the development process is measured. A correction model indicating... Agent: Morgan & Finnegan, L.l.p.08/21/2008 > patent applications in patent subcategories. list of inventions
20080201669 - Method and apparatus for identifying redundant scan elements: An approach for producing optimized integrated circuit designs that support sequential flow partial scan testing may be embedded within an integrated circuit electronic design device. Using the approach, an integrated circuit design may be analyzed to identify and remove scan-enabled memory elements, or scan elements, that are redundant. The redundant... Agent: Oliff & Berridge, PLC
20080201670 - Using constrained scan cells to test integrated circuits: Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to... Agent: Klarquist Sparkman, LLP
20080201672 - Cascaded pass-gate test circuit with interposed split-output drive devices: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.
20080201674 - Clock-gating circuit insertion method, clock-gating circuit insertion program and designing apparatus: A clock-gating circuit insertion method includes inserting a clock-gating circuit into a position detected on the basis of a circuit data. Timing analysis of an enable signal is performed for the clock-gating circuit. An upper limit of delay variations for the enable signal is calculated to satisfy setup conditions on... Agent: Staas & Halsey LLP
20080201671 - Method for generating timing exceptions: A method for generating timing exceptions for integrated circuit (IC) designs is disclosed. The method includes synthesizing an input RTL description into a gate-level netlist mapped to a technology library; detecting timing critical paths in the netlist; and determining for each detected timing critical path whether it induces timing exceptions.... Agent: Sughrue Mion, PLLC
20080201673 - Semiconductor design support device, semiconductor design support method, and manufacturing method for semiconductor integrated circuit: A semiconductor design support device for designing a semiconductor integrated circuit includes a behavioral description, an RTL description, and a latency analyzer. The behavioral description describes an algorithm of processing performed by hardware in a motion level. The RTL description is generated by reading the behavioral description and recognizes a... Agent: Dickstein Shapiro LLP
20080201675 - Structure for integrated circuit for measuring set-up and hold times for a latch element: A design structure for an integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven... Agent: Scully, Scott, Murphy & Presser, P.C.
20080201676 - System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving... Agent: Keusey, Tutunjian & Bitetto, P.C.
20080201677 - Integrated circuit (ic) chip input/output (i/o) cell design optimization method and ic chip with optimized i/o cells: A method of fabricating an integrated circuit (IC) chip. A standard cell macro (e.g., an Off Chip Interface (OCI) cell) is defined with circuit elements identified as in a macro domain. A variable macro boundary is defined for the standard cell macro. Shapes are selectively added to design layers in... Agent: Law Office Of Charles W. Peterson, Jr. Burlington
20080201678 - Method and apparatus for placement and routing cells on integrated circuit chips: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to... Agent: Blakely Sokoloff Taylor & Zafman LLP
20080201679 - Design aid apparatus, computer-readable recording medium in which design aid program is stored, and interactive design aid apparatus: Logical design of a circuit or a printed board including a number of components is carried out with improved flexibility in determination of the positions and the number of logical terminals of a symbol in order to easily create a logical circuit diagram high invisibility due to absence of deficiency... Agent: Staas & Halsey LLP
20080201681 - Computer program products for determining stopping powers of design structures with respect to a traveling particle: A computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code including an algorithm adapted to implement a method including the following steps. First, design information of the design structure is provided including a back-end-of-line layer of the integrated... Agent: Schmeiser, Olsen & Watts
20080201680 - Designing apparatus, designing method, and program: An apparatus, method, and program for designing a semiconductor device having a storage unit configured to a differential signal library for use in generation of a design data of a differential signal cell that receives or outputs differential signals. The apparatus includes a logic synthesis unit performing logic synthesis based... Agent: Staas & Halsey LLP
20080201683 - Method of generating wiring routes with matching delay in the presence of process variation: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC
20080201686 - Method and apparatus for performing target-image-based optical proximity correction: A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP
20080201685 - Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit: A method and apparatus for fabricating integrated circuits providing a desired operation using a plurality of masks, wherein each of said plurality of masks is used to control a corresponding one of a plurality of layers to form said integrated circuits. Said method includes incorporating a plurality of dummy stacks... Agent: Texas Instruments Incorporated
20080201684 - Simulation site placement for lithographic process models: A method and system for performing the method are provided for designing a mask layout that includes selecting simulation sites for optical proximity correction (OPC) or mask verification, prior to fragmentation of shape edges. The primary simulation sites are selected based upon the influence of adjacent shapes, and then fragmentation... Agent: International Business Machines Corporation Dept. 18g08/14/2008 > patent applications in patent subcategories. list of inventions
20080195984 - Method for optimization of logic circuits for routability improvement: Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis... Agent: F. Chau & Associates, Llc
20080195982 - Random test generation using an optimization solver: An optimization process is repeatedly invoked over an input, which includes the set of constraints and the objective function. The input of each invocation is randomly modified, so as to cause the optimization process to produce multiple different solutions that satisfy the set of constraints. Multiple random test cases for... Agent: Stephen C. Kaufman Ibm Corporation
20080195983 - Semiconductor device stress modeling methodology: A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model. The re-fitting algorithm removes any discrepancy between the base... Agent: Scully, Scott, Murphy & Presser, P.c.
20080195985 - Apparatus, method, and computer product for estimating power consumption of lsi: Design data of a cell group is copied to obtain design data of an antecedent cell group and of a subsequent cell group. Design data of a combinational circuit is copied to generate the combinational circuits in plural corresponding to a given number of cycles n (n=2, 3, 4 .... Agent: Greer, Burns & Crain
20080195988 - Integrated circuit transformer devices for on-chip millimeter-wave applications: Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.... Agent: Frank Chau, Esq. F. Chau & Associates, Llc
20080195986 - Power grid tuning for dc voltage equalization: A method for tuning a plurality of supply voltages across and integrated circuit (IC) package that supplies a number of voltage supply regions within an IC chip. The inventive method includes extracting a power draw for each voltage supply region and the region's functional circuit blocks to generate a current... Agent: Scully, Scott, Murphy & Presser, P.c.
20080195987 - System and method for designing a low leakage monotonic cmos logic circuit: A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a... Agent: Schmeiser, Olsen & Watts
20080195989 - Content based yield prediction of vlsi designs: An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each... Agent: Hoffman Warnick Llc
20080195990 - Structure and method of high performance two layer ball grid array substrate: A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to... Agent: Gary C. Honeycutt Texas Instruments Incorporated
20080195991 - Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same: A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to... Agent: Thompson & Knight, L.l.p. Patent Prosecution Group
20080195993 - Method of generating wiring routes with matching delay in the presence of process variation: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc
20080195992 - System and method for generating constraint preserving testcases in the presence of dead-end constraints: A system and method for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is achieved by establishing a sliding window of constraint solving for a selected number of K time-steps in the future from a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.
20080195995 - Formation of masks/reticles having dummy features: Structures and methods for forming the same. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than... Agent: Schmeiser, Olsen & Watts
20080195994 - Methods and systems for performing design checking using a template: A design application improves design checking by utilizing a template. During the checking process, the design application divides the design layout into regions. To further improve processing speed, the design application utilizes the template. The template maps the location of the regions of a design layout during a checking process.... Agent: Texas Instruments Incorporated
20080195996 - Pre-bias optical proximity correction: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.... Agent: Klarquist Sparkman, LLP08/07/2008 > patent applications in patent subcategories. list of inventions
20080189662 - Selection of cells from a multiple threshold voltage cell library for optimized mapping to a multi-vt circuit: A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and... Agent: Cadence Design Systems, Inc. C/o Novak Druce And Quigg LLP
20080189663 - Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells: A method utilizes an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20080189665 - Surface-acoustic-wave device: A surface-acoustic-wave device comprises a piezoelectric substrate and first and second comb-shaped electrodes each having a bus-bar portion parallel to a propagation direction of a surface acoustic wave in the substrate. Respective electrode fingers are periodically formed on the piezoelectric substrate and extend in directions perpendicular to the propagation direction,... Agent: Staas & Halsey LLP
20080189664 - Test yield estimate for semiconductor products created from a library: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC
20080189667 - Model-based design verification: An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For... Agent: Mentor Graphics Corp. Patent Group
20080189666 - Verification method with the implementation of well voltage pseudo diodes: A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the... Agent: Texas Instruments Incorporated
20080189668 - System for placing elements of semiconductor integrated circuit, method of placing elements thereon, and program for placing elements: An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of regions in which logical elements can be placed, and routing information necessary to execute routing, a placement improvement library that stores specified element information... Agent: Sughrue Mion, PLLC
20080189669 - System and method for checking a length of a wire path between a capacitor and a via of a pcb design: A method for checking a length of a wire path between a capacitor and a via of the PCB design is disclosed. The method includes: obtaining length criteria and information on capacitors from a database; selecting one or more capacitors and pins of selected capacitors from the obtained information on... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang
20080189671 - Hdl design structure for integrating test structures into an integrated circuit design: A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device... Agent: W. Riyon Harding International Business Machines Corporation
20080189670 - Method of logic circuit synthesis and design using a dynamic circuit library: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the... Agent: Ibm Corporation (shc) C/o The Culbertson Group, P.C.
20080189672 - Method and system for a pattern layout split: A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring... Agent: Haynes And Boone, LLP
20080189674 - Data generating method, data generating device, and program: The data generating method is a method for generating, in an exposure system having a function of irradiating multigradation-controllable spotlights in a two-dimensional array onto a photosensitive film on a substrate, gradation values of the spotlights based on design graphic data. Using reference data classified by features of a graphic... Agent: Foley And Lardner LLP Suite 500
20080189673 - Pattern match based optical proximity correction and verification of integrated circuit layout: A method for applying optical proximity correction (OPC) to a circuit layout, includes storing distinct defect patterns in a defect pattern library and modifying the circuit layout to fix defect pattern. The method also includes storing a distinct patterns in an OPC pattern library storing one or more post-OPC targets... Agent: Xin WenPrevious industry: Data processing: presentation processing of document
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