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Data processing: design and analysis of circuit or semiconductor mask July cataloged by category listing 07/08

20080184175 - Calibration method of insulating washer in circuit board: A calibration method of insulating washer in a circuit board is provided, which includes steps of (a) establishing an equivalent circuit model corresponding to a metal via; (b) depicting an electric characteristic curve corresponding to the model; (c) calculating a capacitance and an inductance equation corresponding to the curve; (d)... Agent: Rabin & Berdo, PC

20080184174 - System and method for implementing an online design platform for integrated circuits: One embodiment is a method of designing an integrated circuit (“IC”) using an online design platform system comprising a design platform provider, at least one electronic design automation (“EDA”) tool and at least one intellectual property (“IP”) library. The method comprises accessing the design platform provider using a computer remote... Agent: Haynes And Boone, LLP

20080184176 - Systems and methods for determining electrical characteristics of a power distribution network using a one-dimensional model: Systems and methods for determining electrical characteristics of systems such as power distribution networks using one-dimensional stimulation of the systems in place of conventional three-dimensional simulation. One embodiment comprises a method for determining the resistance of a power distribution network for an integrated circuit, and includes defining a one-dimensional model... Agent: Law Offices Of Mark L. Berrier

20080184177 - Method and apparatus for checking current density limitation: A method of checking a current density limitation includes checking the current density limitation of a power supply wiring based on an allowable current value, the allowable current value depending on the number of vias connected to the power supply wiring.... Agent: Staas & Halsey LLP

20080184179 - Integrated circuit designing device, integrated circuit designing method, and integrated circuit designing program: Shielded clock wiring used in an integrated circuit is designed by storing a table of identifiers of shielded clock wiring usable in the integrated circuit, storing dividing rule information in correspondence with each identifier, describing a way of dividing the shielded clock wiring indicated by the each identifier; inputting a... Agent: Staas & Halsey LLP

20080184178 - Method for checking design rule of layout and computer readable recording medium for storing program thereof: A method for checking a design rule of layout and a computer readable recording medium for storing program thereof are provided. A layout comprising a plurality of layers is united so as to generate a flag layer to check the layout, through which any information about characters in the layout... Agent: J C Patents, Inc.

20080184180 - Behavioral synthesis apparatus, method, and program having test bench generation function: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing... Agent: Scully Scott Murphy & Presser, PC

20080184181 - Analog/digital partitioning of circuit designs for simulation: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as... Agent: Cadence Design Systems, Inc. C/o Novak Druce And Quigg LLP

20080184182 - Method and system for design and modeling of transmission lines: A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures (211) of transmission line cells and expanding each of the models of core structures (211) to include different neighboring elements. The parameter characteristics of the expanded... Agent: Stephen C. Kaufman IBM Corporation

20080184183 - Pattern forming method and pattern verifying method: A pattern forming method including modifying design data subjected to a first design rule check in design data of a pattern to be formed in a semiconductor substrate, performing the first design rule check to the modified design data again, outputting the modified design data which does not violate the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080184184 - Method and system for conducting design explorations of an integrated circuit: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or... Agent: Bingham Mccutchen LLP

20080184185 - Method for searching for a similar design model: In a method, device and computer-readable medium for searching automatically for a similar or equal computer-accessible design model of an electronic library, multiple design models of components are provided. In a first phase, for each of these design models, a substitute design model is calculated, and then, using this substitute... Agent: Crowell & Moring LLP Intellectual Property Group

20080184187 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080184186 - Integrated circuit design for reducing coupling between wires of an electronic circuit: A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.... Agent: Ibm Microelectronics Intellectual Property Law

20080184188 - Integrated circuit design method for efficiently generating mask data: A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the... Agent: Kathy Manke Avago Technologies Limited

20080184190 - Method for resizing pattern to be written by lithography technique, and charged particle beam writing method: A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080184191 - Method, program product and apparatus for performing decomposition of a pattern for use in a dpt process: A method of decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of: (a) defining a region of influence which indicates the minimum necessary space between features to be imaged; (b) selecting a vertex associated with a feature of... Agent: Mcdermott Will & Emery LLP

20080184189 - Step-walk relaxation method for global optimization of masks: A set of candidate global optima is identified, one of which is a global solution for making a mask for printing a lithographic pattern. A solution space is formed from dominant joint eigenvectors that is constrained for bright and dark areas of the printed pattern. The solution space is mapped... Agent: Harrington & Smith, PC

20080184192 - Method and apparatus for modeling an apodization effect in an optical lithography system: One embodiment of the present invention provides a system that accurately predicts an apodization effect in an optical lithography system for manufacturing an integrated circuit. During operation, the system starts by collecting an apodization-effect-induced spatial transmission profile from the optical lithography system. The system then constructs an apodization model based... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080178128 - Parallel optimization using independent cell instances: The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are... Agent: O''melveny & Myers LLP Ip&t Calendar Department La-1118

20080178127 - Silicon multiple core or redundant unit optimization tool: A tool is provided that determines an optimal number of processor cores or other redundant units in a multiple core processor or system on a chip, along with selecting an associated semiconductor technology and integrated circuit package. The tool integrates design elements, performance and power metrics, manufacturing yields, redundancy, and... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.

20080178129 - Comparator circuit and method for operating a comparator circuit: A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure is described. The design structure includes a comparator circuit for comparing a first voltage signal to a second voltage signal comprising a first comparator and a second comparator and a selection... Agent: International Business Machines Corporation Dept. 18g

20080178130 - Fpga circuits and methods considering process variations: Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution times are significantly reduced using these methods in comparison to performing detailed evaluation. The... Agent: John P. O'banion O'banion & Ritchey LLP

20080178132 - Computer program product for design verification using sequential and combinational transformations: System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded... Agent: Ibm Austin (anthony England) C/o Law Office Of Anthony England

20080178131 - Testing method and method for manufacturing an electronic device: A testing method includes: storing QC data for each of electronic device manufacturing processes in a storage unit; changing the QC data for each of the processes to a common fixed form of data; providing a contour for the QC data for each of the processes using the common fixed... Agent: Pearne & Gordon LLP

20080178133 - Method and apparatus for implementing enhanced timing performance through bus signal wire permutation with repowering buffers: A method and apparatus implement improved timing performance of a signal bus through wire permutation with repowering buffers. A repowering buffer includes a prebuffer and a postbuffer. A plurality of prebuffers and postbuffers are stored in a design library, each having a set wiring ordered arrangement for selectively providing wire... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080178134 - Timing verification method and apparatus: A computer-implemented timing verification method for obtaining delay time for a signal propagated through a signal path and performing timing verification. The method stores a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from... Agent: Staas & Halsey LLP

20080178135 - Cells of integrated circuit and related technology and method: Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights equal to a non-integer multiplication of the routing track to establish a cell library, so a layout area of each cell is reduced. Further, higher... Agent: Wpat, Pc

20080178138 - Integrated circuit (ic) having ic floorplan silhouette-like power supply net, and sea of supply (sos) electronic design automation (eda) tool for designing same: An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080178137 - Method and apparatus for net-aware critical area extraction: In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of... Agent: Patterson & Sheridan LLP Ibm Corporation

20080178136 - Method, apparatus, and computer program product for implementing balanced wiring delay within an electronic package: Balanced wiring delay within an electronic package is implemented. A plurality of nets in a net group is identified in the electronic package. A predefined structure is added to each net within the group. A balanced wiring delay customizing program systematically processes and reduces length of the nets until a... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080178139 - Use of breakouts in printed circuit board designs: An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routines that operate on the escapes. Still further, an escape outline... Agent: Mentor Graphics Corp. Patent Group

20080178140 - Method for correcting photomask pattern: A method for correcting a photomask pattern is disclosed. The correction method determines a layout condition according to the space and line width of a layout pattern. The layout condition is used to determine the type of optical proximity correction to be used for a layout pattern in order to... Agent: J C Patents, Inc.

20080178141 - Pattern correction apparatus, pattern correction program, pattern correction method and fabrication method for semiconductor device: A pattern correction apparatus for performing both of optical proximity effect correction and process proximity effect correction with regard to a design pattern includes: a correction calculation means configured to perform correction calculation by two-dimensional model-based optical proximity effect correction for each of sampling points set on pattern edges which... Agent: Sonnenschein Nath & Rosenthal LLP

20080178142 - Hotspot detection method for design and validation of layout for semiconductor device: A hotspot detection method for detecting a hotspot in a layout for a semiconductor device, includes: dividing a target analysis area into a grid based on layout data about the semiconductor device; and determining whether the grid falls into a hotspot or not, based on the results from simulation, using... Agent: Mcginn Intellectual Property Law Group, Pllc

20080172638 - Method of optimizing hierarchical very large scale integration (vlsi) design by use of cluster-based logic cell cloning: A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method... Agent: Downs Rachlin Martin PLLC

20080172641 - Design structure for switching system for signal monitoring and switch-back control: A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal... Agent: Hoffman Warnick LLC

20080172640 - Method for comparing two designs of electronic circuits: d

20080172639 - Methods and apparatus for validating design changes: Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design. Local sensitivity functions at design nodes are aggregated and merged at interconnecting nodes in a recursive process.... Agent: Blakely Sokoloff Taylor & Zafman

20080172643 - High-speed leaf clock frequency-divider/splitter: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses... Agent: Ibm Corporation

20080172642 - Method and apparatus for static timing analysis in the presence of a coupling event and process variation: In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated... Agent: Patterson & Sheridan LLP IBM Corporation

20080172644 - Semiconductor device and yield calculation method: A semiconductor device yield calculation method and a computer program that include selecting from a designed device pattern a specified first pattern and a second pattern that differs from the first pattern, finding a probability that the second pattern passes a test when the first pattern passes the test for... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080172645 - Graph-based pattern matching in l3go designs: A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout; and a graph-based pattern matching system that can identify potential... Agent: Hoffman Warnick LLC

20080172646 - Array transformation in a behavioral synthesis tool: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and... Agent: Klarquist Sparkman, LLP

20080168406 - Methods and apparatuses for thermal analysis based circuit design: Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit... Agent: Blakely Sokoloff Taylor & Zafman

20080168407 - Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric: Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous... Agent: Schwegman, Lundberg & Woessner, P.A.

20080168408 - Performance control of an integrated circuit: An integrated circuit is provided with a test circuit element and one or more further circuit elements. The performance of the test circuit element at various settings of a performance controlling parameter is determined. That performance controlling parameter is then applied across the one or more further circuit elements. The... Agent: Nixon & Vanderhye, PC

20080168409 - Method, apparatus and computer program product for electrical package modeling: A method, apparatus, and computer program product for creating a model representing an electrical network residing in an integrated circuit package.... Agent: Ibm Microelectronics Intellectual Property Law

20080168410 - Properties in electronic design automation: One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements... Agent: Mentor Graphics Corp. Patent Group

20080168411 - Method and apparatus for determining the timing of an integrated circuit design: A system that determines the timing of an integrated circuit (IC) design is presented. During operation, the system receives a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design. Next, the system estimates capacitances for cells within the IC design based on... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080168412 - Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip: One embodiment of the present invention relates to a process that generates a clock-tree on an integrated circuit (IC) chip. During operation, the process starts by receiving a placement for a chip layout, where the placement includes a set of registers at fixed locations in the chip layout. The process... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080168413 - Method for analyzing component mounting board: A method for analyzing a component mounting board comprising a step (A) for forming a multilayer substrate shell model of a multilayer wiring board, a step (B) for forming a multilayer component shell model divided by element division lines based on the bonding position of a component to the surface... Agent: Steptoe & Johnson LLP

20080168414 - method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design.: A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.... Agent: Ibm Microelectronics Intellectual Property Law

20080168415 - Method and tool for designing electronic circuits on a printed circuit board: The invention relates to a design method and tool for designing electronic circuits on a printed circuit board (10), wherein at least one self-contained, pre-composed domain is used, wherein the domain (110, 120, 130, 140, 150, 150, 160) is a module chosen from a pre-composed architecture library, comprising self-contained pre-designed... Agent: W. Riyon Harding International Business Machines Corporation

20080168416 - Methods and systems for determining pitch of lithographic features: A method is provided for determining pitch of lithographic features of a mask. The method includes determining a bias based on an interaction between a plurality of reference features positioned according to a lithographic parameter of the mask, applying the bias to a plurality of lithographic features of the mask,... Agent: Texas Instruments Incorporated

20080168417 - Integrated assist features for epitaxial growth bulk tiles with compensation: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set... Agent: Fortkort & Houston P.C.

20080168418 - Integrated assist features for epitaxial growth bulk/soi hybrid tiles with compensation: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask... Agent: Fortkort & Houston P.C.

20080168419 - Optical proximity correction improvement by fracturing after pre-optical proximity correction: A method for fabricating a mask used to make integrated circuits is provided using an improved OPC process whereby a pre-fracturing OPC process is performed on the target design of the integrated circuit. The pre-fractured OPC design is then fractured and a post-fracturing OPC process performed to make the final... Agent: Law Office Of Delio & Peterson, LLC.

20080163135 - Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs: A method and apparatus for optimizing cooling system performance using full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for optimizing the cooling of an electronic system incorporating at least one semiconductor chip includes receiving full-chip temperature data for the semiconductor chip(s) and configuring... Agent: Moser, Patterson & Sheridan, LLP

20080163134 - Method and system for model-based design and layout of an integrated circuit: Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that... Agent: Bingham Mccutchen LLP

20080163136 - Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs: A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of... Agent: Dillon & Yudell LLP

20080163137 - Method of determining stopping powers of design structures with respect to a traveling particle: A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N... Agent: Schmeiser, Olsen & Watts

20080163139 - Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs: Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and... Agent: Bingham Mccutchen LLP

20080163140 - Methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review: Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also... Agent: Baker & Mckenzie LLP

20080163138 - Power supply noise analysis model generating method and power supply noise analysis model generating apparatus: An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply... Agent: Staas & Halsey LLP

20080163146 - Apparatus for integrated input/output circuit and verification method thereof: An apparatus for integrated input/output circuit and a verification method thereof are provided. The apparatus effectively reduces the chip area occupation and cost, and decreases the resistance on an electrical transmission path of the integrated input/output circuit to improve the circuit efficiency. The apparatus comprises a metal structure and a... Agent: J.c. Patents

20080163143 - Method and apparatus for verifying system-on-chip model: A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the... Agent: The Farrell Law Firm, P.c.

20080163144 - Method of verifying design of logic circuit: A method of verifying a design of logic circuit of a semiconductor device having a first circuit block to which the power continuously applied and a second circuit block receiving the power which turns on/off in response to the state of operation modes includes replacing a first basic logic cell... Agent: Junichi Mimura Oki America Inc.

20080163142 - Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs: Disclosed are an improved method, system, and computer program product for a method or system with concurrent models to more accurately determine and represent the three-dimensional design features of electronic designs. Some embodiments disclose a method or a system for determining the design feature characteristics based upon their respective three-dimensional... Agent: Bingham Mccutchen LLP

20080163145 - Probabilistic noise analysis: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design... Agent: Lsi Corporation

20080163141 - Supplant design rules in electronic designs: Disclosed is an improved method, system, and computer program product for electronic designs with supplant design rules. According to some embodiments of the invention, the foundry-imposed design rules are replaced by one or more supplant design requirements which define absolute or relative threshold(s) for a design feature characteristic. Some other... Agent: Bingham Mccutchen LLP

20080163147 - Method, computer program product, and apparatus for static timing with run-time reduction: Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080163148 - Method, system, and computer program product for timing closure in electronic designs: Disclosed is an improved method, system, and computer program product for timing closure with concurrent models for fabrication, metrology, lithography, and/or imaging processing analyses for electronic designs. Some embodiments of the present invention disclose a method for timing closure with concurrent process model analysis in which a design tool with... Agent: Bingham Mccutchen LLP

20080163149 - System and medium for placement which maintain optimized timing behavior, while improving wireability potential: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths,... Agent: International Business Machines Corporation

20080163150 - Method and system for model-based routing of an integrated circuit: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.... Agent: Bingham Mccutchen LLP

20080163151 - Method for the definition of a library of application-domain-specific logic cells: The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080163152 - Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells: A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080163154 - Side lobe image searching method in lithography: A method for detecting the presence of side lobes in a full chip layout having a main pattern designed on a mask includes surrounding the main pattern with a pattern of polygons or circles. A lithography rule check is performed and uses the pattern of polygons or circles to search... Agent: Akin Gump LLP - Silicon Valley

20080163153 - Verifying mask layout printability using simulation with adjustable accuracy: A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy... Agent: Hoffman Warnick Llc