Data processing: design and analysis of circuit or semiconductor mask inventions 06/08

20080155482 - Automated optimization of vlsi layouts for regularity: VLSI lithographic fidelity is improved via reducing the pattern space of difficult patterns or structures in a design layout for an integrated circuit design, and thereby increasing the regularity of the design, by converting patterns or structures that are similar but not identical to one another into a smaller set... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20080155483 - Database-aided circuit design system and method therefor: A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage error-detection function, by making use of an artificial intelligence simulation database, storing the determination criterions for the optimized circuits, searching... Agent: Rabin & Berdo, Pc

20080155484 - System and method for memory element characterization: A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed... Agent: Keusey, Tutunjian & Bitetto, P.c.

20080155485 - Multilevel ic floorplanner: To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller... Agent: Smith-hill And Bedell, P.c.

20080155487 - Electronic element arrangement method and voltage controlled oscillator using the same: A method for arranging electronic elements is provided. The method is suitable for a set of N electronic elements in which N is an odd number. The set of N electronic elements include a first electronic element subset and a second electronic element subset. The electronic elements of the first... Agent: Joe Mckinney Muncy

20080155486 - Systems and methods for reducing wiring vias during synthesis of electronic designs: Systems and methods for reducing wire vias during synthesis of electronic designs. Exemplary embodiments include an electronic design via reduction method, including marking a plurality of nets, each net having at least two pin connections as unprocessed, determining whether there are further unprocessed nets, selecting one of the plurality of... Agent: Cantor Colburn LLP - Ibm Research Triangle Park

20080155488 - Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit: A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires... Agent: Lsi Logic Corporation Corporate Legal Department

20080155489 - Macrocell, integrated circuit device, and electronic instrument: A macrocell including a physical layer circuit includes a transmitter circuit and a receiver circuit connected with pads for differential signals DP and DM. The transmitter circuit includes a transmission driver which drives a signal line for the DP and a transmission driver which drives a signal line for the... Agent: Oliff & Berridge, Plc

20080155490 - Method for reducing coupling noise, reducing signal skew, and saving layout area for an integrated circuit: Methods for reducing coupling noise, reducing signal skew, and saving layout area for an integrated circuit. Aspects of one method may include prioritizing a plurality of clock signals for layout on a chip. The clock signals may comprise functional and test clock signals and test clock signals, where the functional... Agent: Mcandrews Held & Malloy, Ltd

20080155491 - Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit: An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits (I0a-c). The stream processing circuits (IOa-c) have control parameter inputs for receiving control parameter values. In order to facilitate design of circuits that receive data with a variable block size, a control circuit (14) is... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080148196 - Fast evaluation of average critical area for ic: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080148195 - Method and system for inspection optimization: A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.... Agent: Bingham Mccutchen LLP

20080148194 - Method and system for process optimization: A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.... Agent: Bingham Mccutchen LLP

20080148197 - Parametric-based semiconductor design: A parametric-based design methodology interlocks the design of library elements used in a semiconductor product design with the testing protocol used for the resulting semiconductor products such that parametric assumptions made regarding library elements used in a semiconductor product design may be used to disposition products such as semiconductor chips... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20080148198 - Hotspot totalization method, pattern correction method, and program: A hotspot totalization method includes the following arrangement. Data related to a mask pattern is generated on the basis of data related to a test pattern formed by laying out a plurality of kinds of basic cells at a plurality of locations. A predicted pattern to be formed on a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080148202 - Circuit pattern design supporting system and circuit pattern designing method: In a circuit pattern designing method, a distance calculation data is provided to indicate a relation of a shape of a via bundle and an inter-via-bundle distance in which an over-etched portion is generated in a bottom of a via after an etching; and a provisional layout data is provided... Agent: Mcginn Intellectual Property Law Group, Pllc

20080148201 - Design structure and system for identification of defects on circuits or other arrayed products: A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample... Agent: Harrington & Smith, Pc

20080148199 - Electrostatic discharge device verification in an integrated circuit: Computer-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the... Agent: Ryan, Mason & Lewis, LLP

20080148200 - Method for checking the layout of an integrated circuit: According to one aspect, a method for checking the layout of an integrated circuit or integrated circuit mask comprising a plurality of objects, said method comprising the steps of selecting from the plurality of objects a reference object in the layout, selecting from the plurality of objects a displacement object... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080148205 - Circuit delay analyzer, circuit delay analyzing method, and computer product: Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between... Agent: Staas & Halsey LLP

20080148204 - Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical... Agent: Downs Rachlin Martin Pllc

20080148203 - Latch placement for high performance and low power circuits: A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to... Agent: Ibm Corporation (jvm)

20080148206 - Method of designing semiconductor integrated circuits, and semiconductor integrated circuits that allow precise adjustment of delay time: Standard cell libraries and methods of designing semiconductor integrated circuits are provided. At least one of delay-adjusting cell data and load-capacitor cell data is stored in the cell library for a specified type standard cell in addition to the standard cell data. The specified type standard cell may be utilized... Agent: Oliff & Berridge, Plc

20080148208 - Method for improving a printed circuit board development cycle: Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probes insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in... Agent: Agilent Technologies, Inc. Legal Department, Dl429

20080148207 - Semiconductor integrated circuit device featuring processed minimum circuit pattern, and design method therefor: In a semiconductor integrated circuit design method for carrying out a design of circuit patterns, a plurality of circuit patterns are defined, and each of the circuit patterns is composed of at least one minimum unit area. One of the circuit patterns is selected, and an expansion area is defined... Agent: Young & Thompson

20080148210 - Integrated circuit selective scaling: The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to... Agent: Hoffman, Warnick & D'alessandro Llc

20080148209 - Method of designing semiconductor integrated circuit using test point insertion adjustable to delay time: A method of designing a semiconductor integrated circuit is based on a TPI (Test Point Insertion) technique. The design method includes: inserting a test point into a target node in a designed circuit and designating delay time for a test point path connected to the test point. Thereafter, a layout... Agent: Mcginn Intellectual Property Law Group, Pllc

20080148211 - Design rules checking augmented with pattern matching: Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a... Agent: Winstead Sechrest & Minick P.c.

20080148212 - Place and route tool that incorporates a metal-fill mechanism: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and... Agent: Bingham Mccutchen LLP

20080148213 - Routing method for reducing coupling between wires of an electronic circuit: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.... Agent: Ibm Microelectronics Intellectual Property Law

20080148214 - Method and system for configuring fpgas from vhdl code with reduced delay from large multiplexers: Systems and methods are disclosed for mapping large multiplexers defined in VHDL (Very high speed integrated circuit Hardware Description Language) code to circuitry within an FPGA (field programmable gate array) in order to reduce the time required to synthesize and decompose such VHDL structures into FPGAs. It was recognized that... Agent: O'keefe, Egan, Peterman & Enders LLP

20080148215 - Optimization of memory accesses in a circuit design: Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset of variables in a separately accessible memory space, and... Agent: Klarquist Sparkman, LLP

20080148216 - Method and system for mask optimization: A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.... Agent: Bingham Mccutchen LLP

20080148218 - Mask data generation method, mask formation method, pattern formation method: There is provided an OPC method for obtaining a desired shape in the area where accuracy is required in the case where the area where OPC accuracy is required and the area where no/little OPC accuracy is required are adjacent. At the boundary part between the area where OPC accuracy... Agent: Young & Thompson

20080148217 - Selective shielding for multiple exposure masks: A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with... Agent: Klarquist Sparkman, LLP

20080141183 - Cad apparatus, method, and computer product for designing printed circuit board: In a computer aided design (CAD), apparatus, an editing unit displays an editing screen for editing a circuit diagram. An association-data acquiring unit acquires association data that defines an association between a first pin of a first connector included in the circuit diagram being edited on the editing screen and... Agent: Staas & Halsey LLP

20080141185 - Method and system of dynamic power cutoff for active leakage reduction in circuits: The present invention relates to a novel active leakage power reduction technique, referred to as the dynamic power cutoff technique (DPCT). The DPCT method of the present invention can reduce active leakage, standby leakage, and dynamic power by applying the dynamic power cutoff technique to a circuit. In the method... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.a.

20080141184 - Optimization of flip flop initialization structures with respect to design size and design closure effort from rtl to netlist: A method for optimizing a design of a circuit is disclosed. The method generally includes the steps of (A) identifying a plurality of first flip flops in the design and (B) replacing each of the first flip flops in a file of the design that do not have to be... Agent: Lsi Corporation

20080141186 - Semiconductor integrated circuit and design method for semiconductor integrated circuit: The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two first power supply lines in the same interconnect layer; an actual operation flipflop connected to one of the two first... Agent: Mcdermott Will & Emery LLP

20080141187 - Software controlled transistor body bias: Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080141188 - Method and apparatus for limiting power dissipation in test: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20080141192 - Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance: A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the... Agent: Moser, Patterson & Sheridan, LLP

20080141189 - Method for robust statistical semiconductor device modeling: According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation... Agent: Farjami & Farjami LLP

20080141190 - Process variation tolerant memory design: Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if... Agent: Qualcomm Incorporated

20080141191 - Test method for unit re-modification: The present invention described a test method for unit re-modification, in which there is a test end and a host end. The method generated a sample pattern at a test end, generates a control pattern and modifies a re-modification unit. Otherwise, an experimental pattern is generated and then whether or... Agent: Birch Stewart Kolasch & Birch

20080141195 - Analysis optimizer: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined... Agent: Klarquist Sparkman, LLP

20080141194 - Check support apparatus, method, and computer product: A check support apparatus includes a design-data acquiring unit, an associating unit, and a checking unit. The design-data acquiring unit acquires design data including pin information that indicates association between a pin name and a net name of each pin of the first connector and a pin name and a... Agent: Staas & Halsey LLP

20080141196 - Layout data generation equipment of semiconductor integrated circuit, data generation method and manufacturing method of semiconductor device: A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080141193 - Properties in electronic design automation: One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements... Agent: Mentor Graphics Corp. Patent Group

20080141197 - Semiconductor device design method, semiconductor device design system, and computer program: A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter... Agent: Young & Thompson

20080141201 - Black box timing modeling method and computer system for latch-based subsystem: Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input... Agent: Rothwell, Figg, Ernst & Manbeck, P.c.

20080141198 - Methodology and system for setup/hold time characterization of analog ip: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This... Agent: Jianq Chyun Intellectual Property Office

20080141200 - Methods and apparatuses for timing analysis of electronic circuits: Methods and apparatuses for timing analysis are provided using stages having an input and at least one output. A circuit portion connected to the output is taken into account when analyzing the stage.... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080141199 - Methods and apparatuses for timing analysis of electronics circuits: Methods and apparatuses for performing timing analyses of an electronic circuit are provided. Waveforms of signals in the circuit are determined, and timing checks are performed based on these waveforms.... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080141202 - Semiconductor integrated circuit and method of designing the same: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock... Agent: Mcdermott Will & Emery LLP

20080141203 - Iterative method for refining integrated circuit layout using compass optical proximity correction (opc): The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping... Agent: Hoffman, Warnick & D'alessandro Llc

20080141204 - Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same: A structure for controlling the size of a transistor may include: an active region; a first gate line on the active region; one or more second gate lines on the active region; and source or drain regions arranged in three or more divided active regions that result from the first... Agent: Harness, Dickey & Pierce, P.L.C

20080141205 - Cad apparatus, method, and computer product for designing printed circuit board: In a computer aided design (CAD) apparatus, an association-data acquiring unit acquires association data that defines an association between pins of a first connector and those of a second connector to be connected to the first connector, and an assignment of signals to the pins. A part-information acquiring unit acquires... Agent: Staas & Halsey LLP

20080141206 - Fast dual-vdd buffer insertion and buffered tree construction for power minimization: Integrated circuit apparatus and methods are described for inserting multi-Vdd buffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing trees of the interconnect tree despite the insertion of the multi-Vdd buffers. Techniques are described... Agent: John P. O'banion O'banion & Ritchey LLP

20080141208 - Layout method of semiconductor integrated circuit and computer readable storage medium storing layout program thereof: The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is used for laying out a semiconductor integrated circuit by a step (S32) of searching a... Agent: Mcginn Intellectual Property Law Group, Pllc

20080141207 - Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program: A wiring design system for semiconductor integrated circuit which realizes a low power consumption in a grid-shaped clock wiring within a semiconductor integrated circuit is provided. A wiring design system 10 for semiconductor integrated circuit which designs the gird-shaped clock wiring for uniformly distributing the clock signals to the flip... Agent: Scully Scott Murphy & Presser, Pc

20080141209 - Method and system for designing printed circuit board for electronic circuit: Disclosed is a method including a step for selecting a component, a step for preparing a timing database including terminal information, input/output attribute and AC specifications of the component selected, a step for creating a circuit diagram from circuit design information, a step for extracting connection information and performing timing... Agent: Nec Corporation Of America

20080141210 - Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout: An apparatus and program product automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080141211 - Opc verification using auto-windowed regions: A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using... Agent: International Business Machines Corporation Dept. 18g

20080141212 - Semiconductor mask and method of making same: A method of making a semiconductor device is disclosed. A target mask pattern is provided which includes features to be exposed on the mask, and features to be non-exposed on the mask. The to be exposed features are fractured by searching for geometries on the target mask pattern that meet... Agent: Slater & Matsil LLP

20080134105 - Apparatus, method and program for designing integrated circuit: In a preferred embodiment, a CPU extracts a regular structure in a layout of an integrated circuit using layout graphic information, net list information, and constraint information with reference to regularity information of an array-structure, a row-structure, and the like, stored in a magnetic disk storage to evaluate the regular... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080134107 - Computer-aided design system to automate scan synthesis at register-transfer level: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection,... Agent: Jim Zegeer, Esq. Suite 108

20080134104 - Design methodology of guard ring design resistance optimization for latchup prevention: A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS circuit and the corresponding power supply. By comparing the calculated guard ring to power supply path resistance value to resistance... Agent: Scully, Scott, Murphy & Presser, P.c.

20080134103 - Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise: A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the... Agent: Dillon & Yudell LLP

20080134108 - Method and system for creating and programming an adaptive computing engine: A system for creating an adaptive computing engine (ACE) includes algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations, and provides mapping of the algorithmic operations to heterogeneous nodes. The mapping is for initially configuring the heterogeneous nodes to provide appropriate hardware circuit functions that... Agent: Nixon Peabody, LLP

20080134106 - Method and system for improving the manufacturability of integrated circuits: At a particular stage in design of an integrated circuit, DFM improvements are identified which might conflict with design requirements applicable during a subsequent stage in the design flow. These DFM improvements are “reserved” that is, they are not implemented right away. However, an instance of a DFM-optimized version of... Agent: Freescale Semiconductor, Inc. Law Department

20080134109 - Analog design retargeting: An analog retargeting system and method are disclosed for converting a circuit from a source technology to a target technology. Thus, an analog circuit in a source technology can be converted to another technology while maintaining substantially the same circuit behavior and specifications as the original design. The conversion includes... Agent: Klarquist Sparkman, LLP

20080134110 - Logic transformation and gate placement to avoid routing congestion: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage.... Agent: Schmeiser, Olsen & Watts

20080134111 - Regional pattern density determination method and system: A method and system of determining a localized measure of regional pattern density in a fabrication process of a chip are disclosed. In one embodiment, the method includes determining pattern density values for each cell of a plurality of cells of interest; averaging the pattern density values for each cell... Agent: Hoffman, Warnick & D'alessandro Llc

20080134115 - Metastability effects simulation for a circuit description: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned... Agent: Trellis Intellectual Property Law Group, Pc

20080134113 - Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver: A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability... Agent: Dillon & Yudell LLP

20080134112 - Method for compensating performance degradation of rfic using em simulation: Provided is a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an EM simulation. The method includes the steps of: (a) extracting the design specifications of the RFIC so as design and simulate a circuit; (b) designing the layout of the designed and simulated circuit,... Agent: Lowe Hauptman Ham & Berner, LLP

20080134114 - Phase abstraction for formal verification: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create... Agent: Bever, Hoffman & Harms, LLP

20080134116 - Method, computer program product, and tool for timing performance of a hierarchical chip design having multiple partition instances: Timing resources are saved in timing performance of a hiearchial chip design having multiple partition instances. A netlist of the chip design is loaded into a timing model, including only one instance of each partition type in the chip design. The timing model is instructed to ignore boundary timing. The... Agent: Cantor Colburn LLP - Ibm Rochester Division

20080134117 - System and method for efficient analysis of point-to-point delay constraints in static timing: A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows... Agent: International Business Machines Corporation Dept. 18g

20080134118 - Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout: The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of... Agent: Mcdermott Will & Emery LLP

20080134119 - Automated electrostatic discharge structure placement and routing in an integrated circuit: A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step... Agent: Ryan, Mason & Lewis, LLP

20080134120 - Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium: A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a... Agent: Amin, Turocy & Calvin, LLP

20080134121 - Cad apparatus, method of editing graphic data, and compter product: A CAD apparatus includes a layer-information storage unit and a layer displaying unit. The layer-information storage unit stores therein information that defines a superposing order, availability of display, and availability of edit of layers that form graphic data subjected to processing. When displaying a layer that is defined as available... Agent: Staas & Halsey LLP

20080134122 - Methods for tiling integrated circuit designs: Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then routing all tiles in parallel, each tile being independently routed by a standard router. Thereafter, routed tiles are... Agent: Blakely Sokoloff Taylor & Zafman

20080134123 - Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method: An FPGA-information managing unit retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from a package-designing CAD apparatus, and... Agent: Staas & Halsey LLP

20080134124 - Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method: An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. When creating a symbol library, if an FPGA... Agent: Staas & Halsey LLP

20080134125 - Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method: An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape... Agent: Staas & Halsey LLP

20080134126 - Data processing in digital systems: A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can... Agent: Schmeiser, Olsen & Watts

20080134127 - Methods and apparatus for implementing parameterizable processors and peripherals: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically... Agent: Weaver Austin Villeneuve & Sampson LLP Attn: Altera

20080134128 - Maximum/variable shifter widths to allow alternating phase-shift implementation for dense or existing layouts: In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter... Agent: Texas Instruments Incorporated

20080134129 - Design rule checking for alternating phase shift lithography: In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating a first set of polygons to define a trim photomask, generating a second set of polygons to define a phase photomask, and determining which edges of the first set of polygons... Agent: Texas Instruments Incorporated

20080134130 - Local coloring for hierarchical opc: A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC... Agent: Law Office Of Delio & Peterson, Llc.

20080134131 - Simulation model making method: A method of making a simulation model, includes specifying a feature factor which characterizes a pattern layout of a mask pattern, specifying a control factor which affects a dimension of a resist pattern to be formed on a substrate by means of a lithography process using the mask pattern, determining... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP