Data processing: design and analysis of circuit or semiconductor mask inventions 05/08

20080126999 - Method and system for conducting a low-power design exploration: Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding to the RTL netlist, generating one or more low-power RTL netlists using the... Agent: Cadence Design Systems, Inc. C/o Novak Druce And Quigg LLP

20080127000 - Method of ic design optimization via creation of design-specific cells from post-layout patterns: A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole... Agent: Paul D. Greeley Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080127001 - Power consumption analyzing method and computer- readable storage medium: A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. The method comprises an... Agent: Staas & Halsey LLP

20080127002 - System and program product for incremental design reduction via iterative overapproximation and re-encoding strategies: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design... Agent: Dillon & Yudell LLP

20080127003 - Opposite-phase scheme for peak current reduction: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock... Agent: Rabin & Berdo, PC

20080127010 - Compact chip package macromodels for chip-package simulation: A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080127011 - Electronic package evaluation apparatus, electronic package optimizing apparatus, and computer-readable recording medium in which electronic package evaluation program is recorded: When reliability evaluation of the whole electronic package is performed, the time required for simulation is decreased, while solder connection parts, in particular, are accurately analyzed. The whole analysis model creating unit creates a solder connection part model which has the same volume, height, and connection area as the volume,... Agent: Staas & Halsey LLP

20080127004 - Method for computing the critical area of compound fault mechanisms: Disclosed is a method of calculating critical area based on both independent and dependent compound fault mechanisms. This critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080127005 - Method of correlating silicon stress to device instance parameters for circuit simulation: Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080127007 - Method to combine address anonymous hash array with clock, data pack and bit anonymous arrays to gather data of registers: A method and system for combining address anonymous hash arrays with clock, datapack and bit anonymous arrays to gather data of registers is disclosed. The method includes receiving a set of process inputs and a set of user inputs associated with a target system and processing a set of user-requested... Agent: Dillon & Yudell LLP

20080127009 - Method, system and computer program for automated hardware design debugging: The present invention provides a method, system and computer program for automated debugging for pre-fabricated digital synchronous hardware designs implemented in Hardware Description Language (HDL). Required information is captured by interacting with the verification environment after verification fails. This capture information is used to build a diagnosis problem where the... Agent: Miller Thompson, LLP

20080127006 - Real-time data stream decompressor: Method, system, and program product for expanding the effective capacity of embedded memory by storing data in a compressed form and reading the data out with subsequent data decompression, including adaptive decompression and data conversion. The system and method for compression and decompression of HDL code between HDL code storage... Agent: International Business Machines Corporation

20080127008 - Test solution development method: A test solution for one or more circuits implementing a communication standard is based on a design specification received from a development organization and a communication standard. The test solution is evaluated with one or more prototype circuits and is selectively modified based on the evaluation with the prototype circuits.... Agent: Vedder Price Kaufman & Kammholz

20080127012 - Conveyor belt style cross-point: An ASIC based hardware accelerated simulation engine accelerates the process of logic verification of integrated circuit designs utilizing a field of ASIC chips. The ASIC chips are interconnected by direct connections, with the communication between these chips has to be accomplished by switching technology internal to the chips. The switching... Agent: International Business Machines Corporation

20080127014 - Method and system for equivalence checking of a low power design: Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of... Agent: Cadence Design Systems, Inc. C/o Novak Druce And Quigg LLP

20080127015 - Method and system for verifying power specifications of a low power design: Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in... Agent: Cadence Design Systems, Inc. C/o Novak Druce And Quigg LLP

20080127013 - System for estimating a terminal capacitance and for characterizing a circuit: A method for estimating a terminal capacitance associated with a terminal of a cell including a digital circuit includes providing first and second capacitance values associated with an upper and lower bound, respectively, on the terminal capacitance, providing results of a timing analysis of the digital circuit, and determining an... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080127016 - Floorplanning apparatus and computer readable recording medium storing floorplanning program: The present invention is aimed to efficiently realize a reduction in size of and dead space in a semiconductor integrated circuit while securing freedom of placement and wiring of internal components of placement objects and suppressing an increase of constraints of CAD system. A floorplanning apparatus has a temporary placement... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080127018 - Clock aware placement: The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are... Agent: Ibm Corporation (jvm)

20080127017 - Constrained detailed placement: A computer implemented method and a computer program product which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080127019 - Method and system for designing a memory register: Disclosed is a system and method for designing a register layout. According to some embodiments of the present invention, a technology specification is combined with project specifications to produce a set of project specific layout constraints. The project specific constraints may be used to produce a layout.... Agent: International Business Machines Corporation Dept. 18g

20080127021 - Method and system for designing test circuit in a system on chip: A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains... Agent: Freescale Semiconductor, Inc. Law Department

20080127020 - System and method for automatic elimination of voltage drop, also known as ir drop, violations of a mask layout block, maintaining the process design rules correctness: A system and method for automatic correction of voltage drop, also known as IR Drop violations of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness, are disclosed. The method includes analyzing polygons or signals for voltage drop violations, in a mask... Agent: Danny Rittman

20080127025 - Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit: The invention relates to an automated method for inserting dummy surfaces (95) into the various layers of the physical design (121) of multilayer integrated circuits organized in interconnected units (2) containing interconnected blocks (30) composed of interconnected cells (3), implemented by an integrated circuit design system (100). The multilayer integrated... Agent: Miles & Stockbridge PC

20080127023 - Method for controlling peak current: A method for controlling a peak current is provided. The method first uses a plurality of registers to encode a plurality of states of a circuit and generates an original state code. Then, the original state code is re-encoded to reduce the difference between the sum of charging current of... Agent: Jianq Chyun Intellectual Property Office

20080127022 - Method for managing net data of a layout: A method for managing net data of a layout is provided. The method comprises first establishing a net data classification index list in which a net name corresponds to a sub group; comparing a newly added net name with the net data classification index list; classifying the newly added net... Agent: Harness, Dickey & Pierce, P.L.C

20080127024 - Methods, systems, and media to improve manufacturability of semiconductor devices: Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20080127026 - Logic synthesis method and device: The present invention provides a logic synthesis method and the like that can shorten the execution time and the confirmation time required for logic re-synthesis and logic equivalence checking. The logic synthesis method characteristically includes the steps of: extracting logically different portions between an existing gate level logic circuit and... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20080127028 - Integrated circuits verification checks of mask layout database, via the internet method and computer software: A system and method for integrated circuits verification checks of mask layout database, via the internet are disclosed. The method includes the submission of mask layout database for a specific verification check, over the internet to a main server. All required setup files are also submitted over the internet to... Agent: Danny Rittman

20080127027 - Printability verification by progressive modeling accuracy: A fast method of verifying a lithographic mask design is provided wherein catastrophic errors are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models, including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding... Agent: International Business Machines Corporation Dept. 18g

20080127029 - Closed-loop design for manufacturability process: A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the... Agent: International Business Machines Corporation Dept. 18g

20080127030 - Laser repair system and glass mask used for the same: m

20080127031 - Method and device for correcting slm stamp image imperfections: The invention relates to production and precision patterning of work pieces, including manufacture of photomask for photolithography and direct writing on other substrates, such as semiconductor substrates. In particular, it relates to applying corrections to pattern data, such as corrections for distortions in the field of an SLM exposure stamp.... Agent: Haynes Beffel & Wolfeld LLP

20080120581 - Computer product for supporting design and verification of integrated circuit: Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step;... Agent: Staas & Halsey LLP

20080120580 - Design structures incorporating interconnect structures with improved electromigration resistance: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080120583 - Method and program for designing semiconductor integrated circuit, method and program for supporting design of semiconductor integrated circuit, and method and program for calculating wiring parasitic capacitance: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of... Agent: Mcdermott Will & Emery LLP

20080120579 - Methods, systems and user interface for evaluating product designs in light of promulgated standards: Systems, methods and interfaces for evaluating proposed product designs having interconnected devices in light of promulgated industry standards.... Agent: John S. Beulick Armstrong Teasdale LLP

20080120582 - Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium: A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list,... Agent: Amin, Turocy & Calvin, LLP

20080120585 - Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus: A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality... Agent: Amin, Turocy & Calvin, LLP

20080120584 - Timing variation characterization: Methods, systems, and devices for designing and/or analyzing of integrated circuits are disclosed.... Agent: Occhiuti Rohlicek & Tsao, LLP

20080120586 - Density-based layer filler for integrated circuit design: A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may identify open areas on a given design layer in which one or more minimum density rules are not met and may... Agent: Mhkkg/sun

20080120589 - Mask pattern correction program and system: The present invention provides a mask pattern correction program for correcting a design pattern which serves as a source to form a mask pattern so that, by exposure of a mask with a pattern formed thereon onto a substrate, the mask pattern is transferred as designed, the mask pattern correction... Agent: Sonnenschein Nath & Rosenthal LLP

20080120587 - Integrated circuit design system, integrated circuit design program, and integrated circuit design method: An integrated circuit design system able to generate circuit data enabling a clear grasp of power switch cells and circuit cells whose power is cut off without obstructing the efficiency of the design, a method of same, and a program of same, wherein in the description of RTL data generated... Agent: Rader Fishman & Grauer Pllc

20080120588 - Methods for creating primitive constructed standard cells: A high-level logic description is developed based on a non-primitive-based standard cell library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic... Agent: Martine Penilla & Gencarella, LLP

20080115092 - Addressing power supply voltage drops within an integrated circuit using on-cell capacitors: Herein described are at least a standard cell that is less prone to the negative effects of dynamic IR power supply voltage drops and a method of implementing the standard cell. The standard cell incorporates at least one on-cell capacitor positioned between a power supply rail and a ground rail.... Agent: Mcandrews Held & Malloy, Ltd

20080115095 - Method for feedback circuit design: A method and system for feedback circuit design are disclosed. In one aspect, a method of feedback circuit design includes simulating a reference circuit design having a feedback stage at a target crossover frequency, determining an initial phase margin at the target crossover frequency, and adding an impedance network to... Agent: Blakely Sokoloff Taylor & Zafman

20080115096 - Properties in electronic design automation: One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements... Agent: Mentor Graphics Corp. Patent Group

20080115097 - Properties in electronic design automation: One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements... Agent: Mentor Graphics Corp. Patent Group

20080115098 - Method of designing a synchronous circuit of vlsi for clock skew scheduling and optimization: A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function... Agent: Nikolai & Mersereau, P.a.

20080115100 - Chip area optimization for multithreaded designs: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a... Agent: Welsh & Katz, Ltd

20080115099 - Spatial curvature for multiple objective routing: Spatial curvature techniques for multiple objective routing is described. In one or more embodiments, routing between components of an integrated circuit may be determined by transforming pin configurations (e.g., nets) associated with the integrated circuit into a curved space which accounts for multiple design objectives as geometric distance. In the... Agent: Lee & Hayes, Pllc

20080115101 - Program conversion apparatus: Provided is a program conversion apparatus for converting a type of program into another type of program in which a circuit, which has a spec that a user wants, is described. The program conversion apparatus converts the type of program into the another type of program based on a description... Agent: Mcdermott Will & Emery LLP

20080115102 - System and method for automatic elimination of connectivity mismatches during construction of a mask layout block, maintaining process design rule correctness: A system and method for automatic elimination of connectivity mismatches during construction of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness are disclosed. The method includes analyzing a selected polygon or net for connectivity, in a mask layout block and comparing... Agent: Danny Rittman

20080115093 - Systems and media to improve manufacturability of semiconductor devices: Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson Pllc

20080115094 - Logic transformation and gate placement to avoid routing congestion: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage.... Agent: Schmeiser, Olsen & Watts

20080109767 - Layout method of semiconductor circuit, program and design support system: A method of a layout a semiconductor circuit has obtaining transistor characteristic information on the basis of layout information about regions formed with transistors, obtaining a polynomial expression representing a relationship between characteristic values of a circuit including of the transistors and the transistor characteristic information, calculating a plurality of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080109766 - Locating critical dimension(s) of a layout feature in an ic design by modeling simulated intensities: A computer is programmed to perform lithography simulation at a number of locations in a transverse direction relative to a length of a feature of an IC design, to obtain simulated intensities at the locations. The computer is further programmed to determine constants of a predetermined formula that models a... Agent: Silicon Valley Patent Group LLP

20080109770 - High-performance fet device layout: A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one... Agent: Schmeiser, Olsen & Watts

20080109771 - Parameter calculation apparatus, method and storage medium: The present invention obtains a plurality of existing parameters each with a different frequency, select a frequency whose parameter should be calculated and calculates a parameter in the selected frequency, using the plurality of obtained existing parameters with different frequencies. Thus, at least one of the parameter of a frequency... Agent: Staas & Halsey LLP

20080109773 - Analyzing impedance discontinuities in a printed circuit board: Analyzing impedance discontinuities in a printed circuit board, where the printed circuit board is made up of layers of dielectric substrate having signal traces and power planes disposed upon the layers of substrate, the signal traces include trace segments, and the printed circuit board described by a computer-aided design (‘CAD’),... Agent: International Corp (blf)

20080109772 - Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data: A method and system for validating a design rule checking program. The method and system includes creating a hierarchal structure such that each layer of the hierarchal structure corresponds to a process layer of a device or subregion of a shape. The method and system further includes inserting the created... Agent: Greenblum & Bernstein, P.L.C

20080109778 - Setting method of line pitch/line width layout for logic circuit: A setting method of line pitch/line width layout for a logic circuit is provided. In the setting method, a circuit integration procedure is utilized to find the conformable circuit code and retrieve the corresponding circuit setting by string comparison from a logic circuit setting file, so as to integrally generate... Agent: Rabin & Berdo, Pc

20080109780 - Method of and apparatus for optimal placement and validation of i/o blocks within an asic: A novel system and procedure for placement and validation of I/O pins within an ASIC package module. The system reads and a plurality of data files containing chip design, technology and package related information. The parsed data is stored in a single I/O assignment information database that functions to store... Agent: International Business Machines Corporation Dept. 18g

20080109779 - System simulation and graphical data flow programming in a common environment: Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various embodiments of the methods comprise displaying a graphical data flow diagram connected to a system diagram, e.g., where the graphical data flow diagram and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080109782 - Method and system for pin assignment: Methods and systems for assigning package pins of an electronic device to logical pins of a device design to be implemented on the electronic device are disclosed. An example method includes receiving a technology description file for the electronic device, where the technology description file includes a catalog of information... Agent: Mcdonnell Boehnen Hulbert & Berghoff, LLP

20080109768 - Impurity concentration distribution predicting method and program for deciding impurity concentration distribution: First and second evaluation substrates are prepared, a direction perpendicular to a surface of the first evaluation substrate being defined by first indices, and the direction defined by the first indices being inclined from a normal direction of a surface of the second evaluation substrate. Ion implantation is performed for... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080109769 - Method and system for reversing the effects of sequential reparameterization on traces: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step... Agent: Dillon & Yudell LLP

20080109775 - Combined memories in integrated circuits: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may... Agent: Unity Semiconductor Corporation

20080109776 - Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver: A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability... Agent: Dillon & Yudell LLP

20080109774 - Method and system for parametric reduction of sequential designs: A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut... Agent: Dillon & Yudell LLP

20080109777 - Hardware verification programming description generation apparatus, high-level synthesis apparatus, hardware verification programming description generation method, hardware verification program generation method, control program and computer-readable rec: A hardware verification programming description generation apparatus includes: a behavior synthesis section, for a circuit of hardware that operates in accordance with a multi-phase clock, for dividing the hardware into blocks corresponding to clock systems and performing a behavior synthesis on each of the divided blocks, based on a behavioral... Agent: Birch Stewart Kolasch & Birch

20080109781 - Method and system for reversing the effects of sequential reparameterization on traces: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step... Agent: Dillon & Yudell LLP

20080104548 - Method and system for tuning a circuit: The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that... Agent: Morrison & Foerster LLP

20080104549 - Read-only memory device and related method of design: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address... Agent: Fox Rothschild, LLP

20080104550 - Compensating for layout dimension effects in semiconductor device modeling: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance... Agent: Williams, Morgan & Amerson

20080104551 - Design structure for providing optimal field programming of electronic fuses: A design structure for providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in... Agent: Greenblum & Bernstein, P.L.C

20080104552 - Power consumption optimizing method for semiconductor integrated circuit and semiconductor designing apparatus: Disclosed in a power consumption optimizing method for optimizing the power consumption in a semiconductor integrated circuit, which is employed in circuit designing in which the specification of the semiconductor integrated circuit is described in HDL and from the source described in said HDL, logic composition and layout design are... Agent: Mcdermott Will & Emery LLP

20080104554 - Esd analysis device and esd analysis program used for designing semiconductor device and method of designing semiconductor device: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate... Agent: Foley And Lardner LLP Suite 500

20080104553 - Method and apparatus for integrated hierarchical electronics analysis: A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies are for use with chassis... Agent: Duke W. Yee

20080104556 - Assertion generating system, program thereof, circuit verifying system, and assertion generating method: An assertion generating system is disclosed. In an assertion generating system 207, a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state... Agent: Dickstein Shapiro LLP

20080104557 - Integrated sizing, layout, and extractor tool for circuit design: Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of design points, where a design point comprises a design of the circuit that meets a set of predefined design... Agent: Morrison & Foerster LLP

20080104561 - Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit: A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080104562 - Method and program for designing semiconductor integrated circuit: The method of designing a semiconductor integrated circuit of the embodiment is characterized in: reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which a variation of a property value is not taken into consideration, and reading from... Agent: Staas & Halsey LLP

20080104563 - Timing verification method and timing verification apparatus: Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Then, in a first-time timing verification process, voltage drop... Agent: Staas & Halsey LLP

20080104565 - Design data dependency managing apparatus, design data dependency managing method and program: A design data dependency managing apparatus comprises an input/output data storing unit for storing design input/output dependency information indicating a dependency between design input/output data, which becomes an input/output of a design, and other design input/output data in association with the design input/output data, and a design execution environment constructing... Agent: Staas & Halsey LLP

20080104566 - Optimization of rom structure by splitting: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets... Agent: Fox Rothschild, LLP

20080104555 - Testing pattern sensitive algorithms for semiconductor design: A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving... Agent: Hoffman, Warnick & D'alessandro LLC

20080104558 - Method and system for enhanced verification through structural target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more... Agent: Dillon & Yudell LLP

20080104559 - Method and system for enhanced verification through structural target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more... Agent: Dillon & Yudell LLP

20080104560 - Method and system for parametric reduction of sequential designs: A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut... Agent: Dillon & Yudell LLP

20080104564 - Clustering circuit paths in electronic circuit design: Techniques are disclosed for clustering circuit paths in an electronic design automation process for use in improving the timing characteristics of the overall circuit design. Circuit paths included in the cluster may be subjected to placing and routing as a group to relocate instances of circuit components included in the... Agent: Klarquist Sparkman, LLP

20080104567 - Apparatus and method for allocating component, and computer readable medium: There is provided an apparatus that creates a component allocation plan for an electronic apparatus including first and second allocation layers in which components are allocated, including: a storage configured to store first and second component information indicating sizes of a plurality of first components and a plurality of second... Agent: Amin, Turocy & Calvin, LLP

20080104568 - Systematic yield in semiconductor manufacture: Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on... Agent: Andrew M. Calderon Greenblum And Bernstein P.L.C