Data processing: design and analysis of circuit or semiconductor mask inventions 03/08

20080077889 - Parameterized semiconductor chip cells and optimization of the same: A method is provided for designing an integrated circuit utilizing an arrangement of at least one library cell having a plurality of parameterized input connection points disposed along a rod, a plurality of parameterized output connection points disposed along a wire and a cell structure to which the rod and... Agent: Cantor Colburn LLP - IBM Austin

20080077892 - Circuit unit designing apparatus, circuit unit designing method, and circuit unit designing program: A circuit unit designing apparatus configured to design a circuit unit in which, on a substrate, a plurality of circuit components are disposed, includes a circuit designing part carrying out circuit design; an initial characteristic calculating part calculating characteristics of the circuit unit from characteristics of the substrate and the... Agent: Staas & Halsey LLP

20080077891 - Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned... Agent: Scully, Scott, Murphy & Presser, P.C.

20080077894 - Method for generating a design rule map having spatially varying overlay budget: The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information... Agent: Beyer Weaver LLP - Kla Tencor

20080077893 - Method for verifying interconnected blocks of ip: The present invention provides a method for verifying interconnected blocks in a top-block by creating one or more assertions for each input/output of one or more blocks to be used within the top-block, creating one or more assertions for each input/output of the top-block, providing a stimulus intended to cause... Agent: Texas Instruments Incorporated

20080077897 - Circuit design method and circuit design system: A circuit design method causing a computer to conduct a circuit design is disclosed, including the step of calculating a power consumption of an entire chip based on a voltage of each of cells after an IR-drop occurs.... Agent: Staas & Halsey LLP

20080077896 - Method and apparatus for editing timing diagram, and computer product: A timing diagram is displayed on GUI of a timing diagram editing apparatus. Numerical information indicating the repetition number for which a waveform image within the arbitrary number of clocks is repeated is received, and the repetition number is determined based on the numerical information. A sequence image is displayed... Agent: Staas & Halsey LLP

20080077895 - Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components: A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and... Agent: Cantor Colburn LLP - IBM Research Triangle Park

20080077898 - Placer with wires for rf and analog design: The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections... Agent: The Webb Law Firm, P.C.

20080077899 - Converging repeater methodology for channel-limited soc microprocessors: A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints... Agent: Osha Liang L.L.P./sun

20080077901 - Generalized constraint collection management method: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for... Agent: Cadence Design Systems, Inc. C/o Novak Druce And Quigg LLP

20080077900 - Generation of engineering change order (eco) constraints for use in selecting eco repair techniques: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect... Agent: Silicon Valley Patent Group LLP

20080077902 - Method of determining range of change in design, design change range determining apparatus, and design change range determining system: A design change range determining apparatus assigns a link between the one and another elements to generate link information table regarding the assigned link, and when the element is specified through an input unit, retrieves link information table to obtain the parent node associated with the specified element, obtains a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080077904 - Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method: A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on... Agent: Staas & Halsey LLP

20080077907 - Neural network-based system and methods for performing optical proximity correction: An optical proximity corrected mask design is generated from a given a target mask design by processing the target mask design through a feature trained neural network, configured to perform an optical proximity correction of geometric features, to obtain a representation of a first corrected mask design. The target mask... Agent: Gerald B Rosenberg New Tech Law

20080077890 - Novel optimization for circuit design: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result.... Agent: Blakely Sokoloff Taylor & Zafman

20080077903 - Timing violation debugging inside place and route tool: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a... Agent: Lsi Corporation

20080077906 - Interactive interface resource allocation in a behavioral synthesis tool: A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the... Agent: Klarquist Sparkman, LLP

20080077905 - Video processing architecture definition by function graph methodology: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource... Agent: Mayer Brown LLP

20080072181 - Ratioed feedback body voltage bias generator: A design structure embodied in a machine readable medium used in a design process includes a current mirror circuit that includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node... Agent: Ibm Corporation

20080072187 - Method, system, and program product for pre-compile processing of hdl source files: Pre-compilation processing including pre-compilation operations on HDL source code files, including creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger... Agent: International Business Machines Corporation

20080072188 - System and method for modeling metastability decay through latches in an integrated circuit model: A system and method for modeling metastability decay through latches in an integrated circuit model are provided. With the system and method, asynchronous clock boundaries are identified in the integrated circuit model and latches in a receive clock domain are enumerated. Latches within a range of the asynchronous clock boundary... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080072193 - Apparatus and method of expressing circuit version identification: An apparatus and a method of expressing circuit version identification (VID) are disclosed. The apparatus includes a plurality of conductive layers and a circuit VID unit, wherein each conductive layer is provided with a first conductive portion, a second conductive portion and a third conductive portion. The first conductive portion... Agent: Jianq Chyun Intellectual Property Office

20080072192 - Capacitor network reduction: Some aspects provide determination of mutual capacitances among a plurality of floating nets and a plurality of non-floating nets, determination of a self-capacitance of each of the plurality of non-floating nets based on the mutual capacitances, and, for each of the plurality of non-floating nets, association of a ground capacitance... Agent: Buckley, Maschoff & Talwalkar LLC

20080072194 - Method for designing device, system for aiding to design device, and computer program product therefor: A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to... Agent: Young & Thompson

20080072191 - Sanity checker for integrated circuits: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080072190 - Validating one or more circuits using one or more grids: In one embodiment, a method for validating one or more circuits using one or more grids includes accessing a circuit and generating one or more seeds for executing one or more instances of validation on the circuit. Each instance of validation comprising one or more tasks. The method also includes... Agent: Baker Botts L.L.P.

20080072195 - Validation processing apparatus: A validation processing apparatus is to be provided, which allows a user to easily check whether a request designated by the user is satisfied by a data processing system, which is the object to be validated, and to easily check a result of coverage measurement in the data processing system... Agent: Scully Scott Murphy & Presser, PC

20080072197 - System and method for asynchronous clock modeling in an integrated circuit simulation: A system and method for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080072200 - Method and radiation hardened phase frequency detector for implementing enhanced radiation immunity performance: A method and radiation hardened phase frequency detector (PFD) for implementing enhanced radiation immunity performance, and a design structure on which the subject PFD circuit resides are provided. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs,... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080072204 - Layout design of multilayer printed circuit board: A layout design of a multilayer printed circuit board (PCB) is provided, which makes use of partial electromagnetic band gap (EBG) structure to constitute a power layer or a ground layer. The EBG structure is mainly used on the linear transmission path from the port of the first integrated circuit... Agent: Rabin & Berdo, PC

20080072205 - Method and apparatus for designing a logic circuit using one or more circuit elements having a substantially continuous range of values: Methods and apparatus are provided for designing a logic circuit using one or more circuit elements having a substantially continuous range of values. A circuit is designed based on a functional description of the circuit and one or more circuit constraints. The circuit is initially designed using a library of... Agent: Ryan, Mason & Lewis, LLP

20080072206 - Unrolling hardware design generate statements in a source window debugger: Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified... Agent: International Business Machines Corporation

20080072185 - Method and system for reduction of and/or subexpressions in structural design representations: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from... Agent: Dillon & Yudell LLP

20080072184 - Method of achieving timing closure in digital integrated circuits by optimizing individual macros: Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than... Agent: International Business Machines Corporation

20080072183 - Novel optimization for circuit design: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result.... Agent: Blakely Sokoloff Taylor & Zafman

20080072182 - Structured and parameterized model order reduction: Model-order reduction techniques are described for RLC circuits modeling the VLSI layouts. A structured model order reduction is developed to preserve the block-level sparsity, hierarchy and latency. In addition, a structured and parameterized model order reduction is developed to generate macromodels for design optimizations of VLSI layouts. The applications are... Agent: John P. O'banion O'banion & Ritchey LLP

20080072186 - Method and system for reduction of and/or subexpressions in structural design representations: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from... Agent: Dillon & Yudell LLP

20080072189 - Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent rlc extraction and modeling techniques: m

20080072196 - Systems, methods, and media for block-based assertion generation, qualification and analysis: Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions,... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20080072198 - Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations: The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The... Agent: Deborah Neville Neville Law Group

20080072199 - Method for designing semiconductor integrated circuit: The effective distance Deff_i between a well boundary and an active region of a transistor is used as a parameter for expressing a well proximity effect. For example, a delay library is created using the rising time Tslew of a signal input to the gate, load capacitance Cload at the... Agent: Mcdermott Will & Emery LLP

20080072201 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080072202 - Techniques for super fast buffer insertion: A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from... Agent: Ibm Corporation (jvm)

20080072203 - System and method of automated wire and via layout optimization description: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining... Agent: Greenblum & Bernstein, P.L.C

20080072207 - Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs: Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs are provided. One method includes generating simulated images illustrating how each of the different reticle designs will be printed on a wafer at different values of one or more parameters of the... Agent: Baker & Mckenzie LLP

20080072208 - Mask defect inspecting method, semiconductor device manufacturing method, mask defect inspecting apparatus, defect influence map generating method, and computer program product: A mask defect inspecting method comprises preparing detection sensitivities of defects on a plurality of portions of a mask pattern on a photomask, the detection sensitivities being determined according to influences of the defects upon a wafer, and inspecting defects on the plurality of portions based on the detection sensitivities.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080066021 - Method of optimal parameter adjustment and system thereof: A method of optimal parameter adjustment includes randomly generating a first parameter group, setting each parameter into a device to detect a fitness function value corresponding to each parameter, copying parameters according to the fitness function value to form a second parameter group, randomly selecting parameter pairs from the second... Agent: Birch Stewart Kolasch & Birch

20080066024 - Enabling netlist for modeling of technology dependent beol process variation: A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical... Agent: Hoffman, Warnick & D'alessandro LLC

20080066023 - Method and apparatus for fast identification of high stress regions in integrated circuit structure: Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volumetric regions corresponding to those planar regions that were found... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20080066022 - Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs: A method and apparatus for optimizing cooling system performance using full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for optimizing the cooling of an electronic system incorporating at least one semiconductor chip includes receiving full-chip temperature data for the semiconductor chip(s) and configuring... Agent: Patterson & Sheridan L.L.P.

20080066025 - Method for analyzing characteristic of circuit included in integrated circuit based on process information and the like: A circuit analyzing method of the present invention comprises the steps of (a) applying, for a characteristic having a variation width of characteristics of an element included in a circuit to be analyzed, any one of a maximum value and a minimum value of the variation width as a representative... Agent: Mcdermott Will & Emery LLP

20080066027 - Computationally efficient design rule checking for circuit interconnect routing design: Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding... Agent: Hickman Palermo Truong & Becker, LLP

20080066028 - Logic circuit verifying apparatus: A logic circuit verifying apparatus is provided with: a first storage unit for storing thereinto circuit design information described in a hardware description language, in which a script description has been embedded in a description described in the hardware description language; a data converting unit for converting the hardware description... Agent: Mcdermott Will & Emery LLP

20080066035 - Method and design system of semiconductor integrated circuit: Disclosed is a design method for optimizing the timings at which a plurality of power supply switches in a power gating circuit in a semiconductor integrated circuit by the steps of (A) providing a motion model of the power gating circuit, (B) setting a constraint on in-rush current, (C) performing... Agent: Foley And Lardner LLP Suite 500

20080066038 - Method and apparatus for designing semiconductor integrated device using noise current and impedance characteristics of input/output buffers between power supply lines: In a method for designing a semiconductor integrated device, there are prepared a first power supply cell having a first decoupling capacitance and a second power supply cell having a second decoupling capacitance larger than the first decoupling capacitance. One of the first and second power supply cells is arranged... Agent: Foley And Lardner LLP Suite 500

20080066037 - Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors: A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear... Agent: Cantor Colburn LLP - IBM Austin

20080066039 - Semi-flattened pin optimization process for hierarchical physical designs: In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal... Agent: International Business Machines Corporation

20080066043 - Method and system for clock tree generation: A method for generating a clock tree between a clock source and a plurality of logic units is disclosed. The logic units are defined to operate according to a clock signal generated from the clock source. The method includes: categorizing the logic units into a plurality of first-level groups according... Agent: North America Intellectual Property Corporation

20080066045 - Methods and system for configurable domain specific abstract core: The present invention provides a configurable domain specific abstract core (DSAC) for implementing applications within any domain. The DSAC comprises at least one function specific abstract module (FSAM) configurable at a plurality of stages for implementing a predetermined function belonging to one or more applications in the domain. The FSAM... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080066046 - Hardware definition language generation for frame-based processing: An automatic code generation application is used to automatically generate code and build programs from a textual model or graphical model for implementation on the computational platform based on the design. One or more model elements may be capable of frame-based data processing. Various options and optimizations are used to... Agent: Lahive & Cockfield, LLP/the Mathworks

20080066047 - System and method for employing patterning process statistics for ground rules waivers and optimization: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080066026 - Power network analyzer for an integrated circuit design: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing... Agent: Silicon Valley Patent Group LLP

20080066032 - Measure of analysis performed in property checking: The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value... Agent: Trellis Intellectual Property Law Group, PC

20080066029 - Method and system alerting an entity to design changes impacting the manufacture of a semiconductor device in a virtual fab environment: A design coordination engine coordinates design implementation among a manufacturing facility, a customer, an IP vendor, and a design group during the design phase of a semiconductor device. The design coordination engine includes a tracking module configured to track design information updates in a design database. The design coordination engine... Agent: Haynes And Boone, LLP

20080066033 - Method and system for performing heuristic constraint simplification: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state... Agent: Dillon & Yudell LLP

20080066034 - Method and system for performing heuristic constraint simplification: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state... Agent: Dillon & Yudell LLP

20080066031 - Method for verification using reachability overapproximation: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is... Agent: Dillon & Yudell LLP

20080066030 - Systems, methods, and media for block-based assertion generation, qualification and analysis: Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions,... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20080066036 - Chip having timing analysis of paths performed within the chip during the design process: An integrated Circlet chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A... Agent: International Business Machines Corporation

20080066041 - Auxiliary pattern generation for cell-based optical proximity correction: Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modified for a plurality of standard cells to permit incorporation of... Agent: Greer, Burns & Crain

20080066040 - Integrated circuit chip with repeater flops and method for automated design of same: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080066042 - Method and system for creating, viewing, editing, and sharing output from a design checking system: Existing text output from a design rule checker is put in appropriate input format, and automatically displayed as text within a design tool using existing design tool capabilities, such as highlighting, zooming, and drawing box-regions. A graphical display of the output of the rule checker includes the informative text. Design... Agent: Law Office Of Delio & Peterson, LLC.

20080066044 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080059916 - Method for automatically modifying integrated circuit layout: This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080059922 - Graph pruning scheme for sensitivity analysis with partitions: A method of analyzing a circuit simulation comprising pruning a signal flow graph. Pruning the signal flow graph includes selecting a current vertex from a multiple input vertices in the signal flow graph. Each one of the input vertices is connected to a primary input of the signal flow graph.... Agent: Martine Penilla & Gencarella, LLP

20080059921 - Method and apparatus for optimizing power consumption in a multiprocessor environment: A method and apparatus for reducing net power consumption in a computer system includes identifying a plurality of processing states operable to execute a task. A processing state and current drain pattern is selected that is most power efficient. A selected processing state may include one or more processing elements... Agent: Advanced Micro Devices, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20080059926 - Method of calculating a model formula for circuit simulation: It is an object of the invention to obtain a model formula for a circuit simulator that can be applied to a semiconductor device in which a channel length thereof becomes further shorter. A method of calculating a model formula for circuit simulation of a semiconductor device is provided. The... Agent: Kratz, Quintos & Hanson, LLP

20080059925 - Method, system, and program product for automated verification of gating logic using formal verification: As described herein the automated verification methodology parsing scripts auto generate test bench hardware design langaue, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. The resulting design verification tool then... Agent: International Business Machines Corporation

20080059931 - Apparatus and methods for congestion estimation and optimization for computer-aided design software: A method of performing placement of resources in a computer-aided design (CAD) tool includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used for performing another congestion analysis.... Agent: Law Offices Of Maximilian R. Peterson

20080059934 - Apparatus and method for designing semiconductor devices: Apparatus and method for designing semiconductor devices enabling to design layout of through-holes automatically between same-potential upper- and lower-layer power wiring traces without omissions and with a minimum labor. Area of overlap between same-potential, different-layer power wiring traces is extracted from designed power wiring traces. In order to detect area... Agent: Mcginn Intellectual Property Law Group, PLLC

20080059938 - Method of and system for designing semiconductor integrated circuit: A method of designing a semiconductor integrated circuit by a computer, comprises: (A) reading an RTL data indicating RTL description of the semiconductor integrated circuit; and (B) providing a gating cell for clock gating during logic synthesis of the RTL description. The gating cell includes a latch circuit that latches... Agent: Sughrue Mion, PLLC

20080059917 - Antenna manufacturing method and communication equipment manufacturing method: An antenna manufacturing method including the step of inputting as variables shape of a case, position of an antenna in the case, shape of the antenna, position of antenna peripheral components in the case, and shape of the antenna peripheral components, and the step of computing optimum value of the... Agent: Wenderoth, Lind & Ponack L.L.P.

20080059919 - Computer program for balancing power plane pin currents in a printed wiring board: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080059920 - Method and apparatus for removing dummy features from a data structure: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080059918 - Systematic yield in semiconductor manufacture: Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are... Agent: Greenblum & Bernstein, P.L.C

20080059924 - Design structures incorporating interconnect structures with liner repair layers: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080059923 - Lsi power consumption calculation method and calculation program: A logic simulation is executed for a first netlist, activity rate data is determined for the gated clock buffer, the power consumption is calculated from the activity rate data. Thereafter, given a modified second netlist having at least a portion of the cells of the first netlist, activity rate data... Agent: Staas & Halsey LLP

20080059928 - Assertion description conversion device, method and computer program product: An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion description language for verification of an inputted design description of a broader term to identify a verification target; design description searching unit searching a description on the... Agent: Amin, Turocy & Calvin, LLP

20080059929 - Ic design modeling allowing dimension-dependent rule checking: A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at... Agent: Hoffman Warnick & D'alessandro, LLC

20080059930 - Mesa optical sensors and methods of manufacturing the same: In a first aspect, a first method of determining radiation intensity is provided. The first method includes the steps of (1) providing a semiconductor device having (a) a silicon mesa; and (b) photo-gate conductor material along at least three sidewalls of the silicon mesa; (2) forming a depletion region in... Agent: Ibm Corporation, Intellectual Property Law

20080059927 - Method and device and their use for checking the layout of an electronic circuit: A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a... Agent: Slater & Matsil, L.L.P.

20080059932 - Parallel electronic design automation: shared simultaneous editing: A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while... Agent: Banner & Witcoff, Ltd.

20080059935 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example,... Agent: Fish & Richardson P.C.

20080059936 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: Fish & Richardson P.C.

20080059933 - Method and system for designing fan-out nets connecting a signal source and plurality of active net elements in an integrated circuit: The present invention relates to a method for designing fan-out nets connecting a signal source and a plurality of net elements in an integrated circuit. In order to make fan-out nets more robust against opens while keeping the risk due to short circuits in an acceptable degree, the method comprises... Agent: International Business Machines Corporation

20080059937 - Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality... Agent: Adeli & Tollen, LLP

20080059939 - Performance in model-based opc engine utilizing efficient polygon pinning method: Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the... Agent: Law Office Of Delio & Peterson, LLC.