Data processing: design and analysis of circuit or semiconductor mask inventions 02/08

20080052645 - Method and apparatus for determining lsi type, method and apparatus for supporting lsi design, and computer product: In manufacturing a structured ASIC, after production of an intermediate product with a transistor layer or the transistor layer and a metal layer, the transistor speed of each intermediate product is measured and, using the speed and associated statistical data, a maximum transistor speed delay is estimated. Based on the... Agent: Staas & Halsey LLP

20080052644 - String matching engine for arbitrary length strings: An efficient finite state machine implementation of a string matching that relies upon a Content Addressable Memory (CAM) or a CAM-equivalent collision-free hash-based lookup architecture with zero false positives used as a method for implementing large FSMs in hardware using a collision-free hash-based look up scheme with low average case... Agent: Beyer Weaver LLP

20080052646 - Lithography aware leakage analysis: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a... Agent: Townsend And Townsend And Crew, LLP

20080052647 - Computer development apparatus: A computer development apparatus includes hardware-parts where design data on hardware parts are caused to correspond to each other for each of information for identifying the hardware parts, software-parts where design data on software parts are caused to correspond to each other for each of information for identifying the software... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080052653 - Lithography aware timing analysis: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a... Agent: Townsend And Townsend And Crew, LLP

20080052652 - Method and apparatus for fixing best case hold time violations in an integrated circuit design: The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until... Agent: Henry Groth Lsi Logic Corporation

20080052651 - Methods to generate state space models by closed forms for general interconnect and transmission lines, trees and nets, and their model reduction and simulations: There is provided a set of methods for generating state space models of general VLSI interconnect and transmission lines, trees and nets by closed forms with exact accuracy and low computation complexity. The state space model is built by three types of models: the branch model, the connection model and... Agent: Prof. Sheng-guo Wang

20080052657 - Semiconductor device layout method and layout program: It is an aspect of the embodiments discussed herein to provide a semiconductor device layout method and a semiconductor device layout program that enable the minimum necessary decoupling capacitances to be placed efficiently according to a circuit configuration, placement positions, operation timings, and clock tree of functional circuits.... Agent: Staas & Halsey LLP

20080052660 - Method of correcting a designed pattern of a mask: A method of correcting a design pattern of a mask takes into account the overlay margin between adjacent one of actual patterns that are stacked on a substrate. First, a pattern of a photomask for forming a first one of the actual patterns on a substrate is conceived. Also, information... Agent: Volentine & Whitt PLLC

20080052661 - Optical proximity correction (opc) processing method for preventing the occurrence of off-grid: An optical proximity correction (OPC) processing method may include at least one of the following steps: Detecting coordinate values of individual piece patterns constituting a graphic design system (GDS). Merging to the form of a specific pattern, composed of outermost coordinate values, on the basis of the detected coordinate values.... Agent: Sherr & Nourse, PLLC

20080052648 - Method and system for enchanced verification through binary decision diagram-based target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is... Agent: Dillon & Yudell LLP

20080052650 - Method for verification using reachability overapproximation: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is... Agent: Dillon & Yudell LLP

20080052649 - Power network analyzer for an integrated circuit design: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing... Agent: Silicon Valley Patent Group LLP

20080052655 - Chip having timing analysis of paths performed within the chip during the design process: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A... Agent: International Business Machines Corporation

20080052654 - Methods and apparatuses for transient analyses of circuits: Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group... Agent: Blakely Sokoloff Taylor & Zafman

20080052656 - Slack sensitivity to parameter variation based timing analysis: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing,... Agent: Hoffman, Warnick & D'alessandro LLC

20080052658 - Structure for dynamically adjusting distributed queuing system and data queuing receiver reference voltages: A design structure embodied in a machine readable medium used in a design process includes an apparatus for automatically setting DQS (Distributed Queuing System) and DQ (Data Queuing) receiver reference voltages, the apparatus including a delay string to measure a number of delay elements that match a DQS high time... Agent: Cantor Colburn LLP - IBM Rochester Division

20080052659 - Electrically programmable pi-shaped fuse structures and design process therefore: Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second... Agent: Ibm Corporation Department 417

20080046846 - System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization: A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The... Agent: Marko P. Chew

20080046847 - Method for improving yield of a layout and recording medium having the layout: A yield of a semiconductor layout may be improved by selecting a pattern that does not satisfy at least one of multiple rules within the layout, adding a margin to a predetermined value of the at least one of the rules associated with selected pattern, based on a ground rule... Agent: Lee & Morse, P.C.

20080046848 - Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction: A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle... Agent: Lsi Logic Corporation Corporate Legal Department

20080046849 - Method for changing physical layout data using virtual layer: A method for changing physical layout data using a virtual layer is provided. The method codes a target design and synthesizes a logic for it. It may generate a virtual layer, places logic blocks at positions and route them for connection to execution elements. Wiring resistance or capacitance values may... Agent: Sherr & Nourse, PLLC

20080046851 - Partitioning electronic circuit designs into simulation-ready blocks: A partitioning method for an integrated circuit (IC) design includes providing a textual file representing the design as library-specific cells and interconnections, including timing data for the cells and timing data derived from the design after placement and routing. The design is flattened to cell level. Edge-triggered flip-flops (ETFF's) are... Agent: Anatoly S. Weiser

20080046853 - Method for generating fill and cheese structures: A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame;... Agent: Davidson, Davidson & Kappel, LLC

20080046852 - System and method of automated wire and via layout optimization description: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining... Agent: Greenblum & Bernstein, P.L.C

20080046856 - Degeneration technique for designing memory devices: A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input... Agent: Nixon & Vanderhye, PC

20080046850 - Integrated circuit implementing improved timing driven placements of elements of a circuit: An integrated circuit chip has more “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack... Agent: International Business Machines Corporation

20080046854 - Method and system to redistribute white space for minimizing wire length: Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined optimal wire length. In accordance with the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080046855 - Connectivity-based symbol generation in wiring diagrams: A computer-implemented method includes inputting a netlist and generating symbols and connections formed according to the netlist and a selected wiring harness layout dimension. A wiring harness diagram is generated along the layout dimension according to the symbols and the connections.... Agent: Klarquist Sparkman, LLP

20080040694 - Methods and apparatus for boolean equivalency checking in the presence of voting logic: In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of... Agent: Ibm Corporation Intellectual Property Law, Dept. 917

20080040697 - Design structure incorporating semiconductor device structures with voids: Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a gate electrode of a device, such as a field effect transistor, having an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080040696 - Design structures incorporating shallow trench isolation filled by liquid phase deposition of sio2: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase deposited silicon dioxide (LPD-SiO2). The shallow trench isolation region is used to isolate two active regions formed on a silicon-on-insulator (SOI) substrate.... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080040695 - System and method for accurately modeling an asynchronous interface using expanded logic elements: A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080040698 - Method and system for designing semiconductor circuit devices to reduce static power consumption: A method and system are disclosed for designing a complex integrated electronic circuit architecture including a plurality of circuit portions integrated into a single chip structure. The method includes providing at least one library of cells with a variable channel length L; creating a layout of an integrated circuit using... Agent: Graybeal, Jackson, Haley LLP

20080040700 - Behavioral synthesizer, debugger, writing device and computer aided design system and method: The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for processing at a logic synthesizing stage, placement and routing stage, debugging stage, writing stage of circuit information to a reconfigurable device,... Agent: Young & Thompson

20080040699 - Same subgraph detector for data flow graph, high-order combiner, same subgraph detecting method for data flow graph, same subgraph detection control program for data flow graph, and readable recording medium: A same sub-graph detection apparatus for data flow graph is disclosed. An embodiment of the present invention detects a sub-graph at a high speed, in which an area-size reduction effect is large. The same sub-graph detection apparatus for data flow graph according to an embodiment of the present invention includes... Agent: Harness, Dickey & Pierce, P.L.C

20080034333 - System and method for converting a measuring program: A computer based method for converting a measuring program is provided. The method includes the steps of: reading a measuring program to be converted from a measuring program storage area; converting a measure element sub-program having an initial format into a converted measure element sub-program having a designated format; converting... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080034334 - Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit: The present invention relates to the testing of functional or IP cores forming part of a system on chip, SoC. The invention is implemented using a testing means and a communication means to test at least one functional or IP core. The testing means comprises a wrapper in which the... Agent: Clark & Brody

20080034336 - Electro-migration verifying apparatus, electro-migration verifying method, data structure and netlist used in the same: An electro-migration verifying method is comprised of: a data inputting process step; a netlist updating process step (first process operation) for updating a netlist which is constructed by a wiring line parasitic element and a device element based upon a current density limit value database, a characteristic variation database, and... Agent: Mcdermott Will & Emery LLP

20080034337 - integrated circuit design closure method for selective voltage binning: Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to achievable performance. Each performance interval is independently optimized for performance versus power by... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080034340 - Apparatus for designing circuit and method for designing circuit: An apparatus for designing a circuit comprises an arranging element which arranges a first wiring required a predetermined clearance between the first wiring and other wirings and a second wiring being thinner in a wiring width than the first wiring, a calculating element which calculates a particular part of the... Agent: Sughrue Mion, PLLC

20080034339 - Pattern matching system for layout shapes using walsh patterns: A pattern matching system, based on an orthogonal sub-space projection of layout shapes using Walsh patterns, performs a preliminary density feature extraction of a circuit design layout, allows a user to define a pattern, and performs a high resolution search of the layout to locate all instances of the pattern.... Agent: International Business Machines Corporation Dept. 18g

20080034341 - Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices: Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20080034343 - System and method for checking for sub-resolution assist features: In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking program divides each edge of each main feature into sections, forms a set of segments by searching perpendicularly over a distance to determine if any portion... Agent: Texas Instruments Incorporated

20080034344 - Overlay mark: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region... Agent: Birch Stewart Kolasch & Birch

20080034332 - Optimization of geometry pattern density: Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with fill polygons A pattern of fill polygons also is generated, to fill the fill regions. The layout... Agent: Banner & Witcoff, Ltd.

20080034335 - Design structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080034338 - Timing analysis method and device: A timing analysis device for preventing the amount of data and the number of analysis operations from increasing in a statistical analysis, while improving the timing convergence in a path included in a net under relatively strict timing conditions. The timing analysis device performs a static timing analysis to extract... Agent: Staas & Halsey LLP

20080034342 - Distributed autorouting of conductive paths: A server computer maintains a master database for a PCB design, and a copy of the PCB design is provided to multiple client computers. The server assigns each client a different pair of pins for which a connection must be routed. When a client completes an assigned routing task, it... Agent: Banner & Witcoff, Ltd.