Data processing: design and analysis of circuit or semiconductor mask inventions 01/08

20080028344 - Pattern correction apparatus, pattern optimization apparatus, and integrated circuit design apparatus: To provide a pattern correction apparatus which enables easy correction of a trace which is not present on trace grids, a pattern correction apparatus which makes a correction to a pattern of an integrated circuit includes a trace movement section for moving, among traces forming the pattern of the integrated... Agent: Mcdermott Will & Emery LLP

20080028342 - Simulation apparatus and simulation method used to design characteristics and circuits of semiconductor device, and semiconductor device fabrication method: Disclosed is a simulation apparatus including an input unit, storage unit, arithmetic unit, controller, and output unit. The input unit inputs a first potential at the source end, which corresponds to the gate end of a TFT, on that surface of a thin polysilicon film which faces the gate, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080028346 - Method and system for determining required quantity of testing points on a circuit layout diagram: A method and system is proposed for determining the required quantity of testing points on a circuit layout diagram generated by a computer-aided circuit layout design program on a computer platform. The proposed method and system is characterized by the use of a graphic file scanning method for finding and... Agent: Law Offices Of Mikio Ishimaru

20080028347 - Transformation of ic designs for formal verification: A memory is encoded with data that represents a reference IC design, a retimed IC design, and logical relationships, wherein at least one logical relationship describes combinational logic without reference to structural information, such as actual cells that have been instantiated in the IC designs. The logical relationships are used... Agent: Silicon Valley Patent Group LLP

20080028351 - Memory macro with irregular edge cells: A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080028352 - Automatically routing nets with variable spacing: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on... Agent: Aka Chan LLP

20080028353 - Method for treating parasitic resistance, capacitance, and inductance in the design flow of integrated circuit extraction, simulations, and analyses: An extraction, simulation, and analysis combined method is employed to account for the parasitic couplings from interconnect wires. Variations of parasitic resistance, capacitance, and inductance are used in circuit analysis calculators, including considering the variations of the parasitics on worst case circuit performance, skewing, and statistical Monte Carlo analysis. Each... Agent: Law Office Of Delio & Peterson, LLC.

20080028356 - Method and apparatus for supporting ic design, and computer product: A logical-group creating unit creates a logical group from a cell included in a selected range of a logical drawing that is specified in a logical page. A logical-group extracting unit extracts a same/similar logical group by determining whether logical drawings of created logical groups are same or similar to... Agent: Staas & Halsey LLP

20080028360 - Methods and systems for performing lithography, methods for aligning objects relative to one another, and nanoimprinting molds having non-marking alignment features: Methods of performing lithography include calculating a displacement vector for a lithography tool using an image of a portion of the lithography tool and a portion of a substrate and an additional image of a portion of an additional lithography tool and a portion of the substrate. Methods of aligning... Agent: Hewlett Packard Company

20080028359 - Termination structure, a mask for manufacturing a termination structure, a lithographic process and a semiconductor device with a termination structure: Termination structure for a pattern, especially an at least partially regular spaced pattern used in the manufacturing of semiconductor devices, especially DRAM-chips, wherein the termination structure comprises at least a first line-shaped element and at least one extension element adjacent to the first line-shaped element partially increasing the width of... Agent: Slater & Matsil LLP

20080028345 - Apparatus and method for integrated circuit design for circuit edit: A method and apparatus for optimizing an integrated circuit design for post-fabrication circuit editing and diagnostics. The method and apparatus is specifically directed to adding designed-for-edit modifications and designed-for-diagnostics structures to an integrated circuit design for post-fabrication circuit editing with a charged-particle beam tool. An integrated circuit design may be... Agent: Sughrue Mion, PLLC

20080028343 - Semiconductor integrated circuit and method of designing the same: A semiconductor integrated circuit comprising: a clock gating cell to which an enable signal and a clock signal are input, so as to output a gated clock signal generated by output-controlling said clock signal according to said enable signal; a first flip-flop circuit to which a first input data signal... Agent: Amin, Turocy & Calvin, LLP

20080028348 - Designing method of electronic component: A designing method of an electronic component aiming at increase in designing efficiency is provided. The designing method has step (21) of setting a predetermined electrical characteristic, step (22) of determining an electric constant of the component with a first electric circuit simulation to satisfy the predetermined electrical characteristic, step... Agent: Wenderoth, Lind & Ponack L.L.P.

20080028349 - Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip: In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the... Agent: Miles & Stockbridge PC

20080028350 - Nonlinear receiver model for gate-level delay calculation: A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more... Agent: Bever, Hoffman & Harms, LLP

20080028354 - Parallel programmable antifuse field programmable gate array device (fpga) and a method for programming and testing an antifuse fpga: The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an... Agent: Sierra Patent Group, Ltd.

20080028355 - Method and software tool for designing an integrated circuit: A method of designing an integrated circuit for an application having standards having a plurality of primitives, each of the primitives having a corresponding response. The method includes generating a macros description of each of the primitives and the response corresponding to each of the primitives, wherein the macros description... Agent: Eckert Seamans Cherin & Mellott

20080028357 - Method of automatic generation of micro clock gating for reducing power consumption: A method and apparatus for reducing transitions thereby reducing power consumption for a clocked output state-holding element having inputs that are respective logic functions of one or more clocked input state-holding elements. A respective valid line is associated with each of the clocked input state-holding elements whose value indicates whether... Agent: International Business Machines Corporation Dept. 18g

20080028358 - Quick and accurate modeling of transmitted field: Systems and techniques to quickly and accurately model a transmitted electromagnetic field through a mask, to design a mask, and to create a library of corrections including edge corrections, edge-to-edge corrections, and corner corrections.... Agent: Fish & Richardson, PC

20080028361 - Pattern evaluation method and evaluation apparatus and pattern evaluation program: A pattern evaluation method for evaluating a mask pattern includes generating desired wafer pattern data corresponding to the evaluation position of a mask pattern, generating mask pattern contour data based on an image of the mask pattern, and performing a lithography/simulation process based on the mask pattern contour data and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080022234 - Automatic trace shaping method: An automatic trace shaping method comprises the steps of: setting sets of coaxial equiangular octagons each having sides parallel with a predetermined reference line; performing a process for tentatively disposing the traces each having segments passing between the adjacent vias so that such segments overlap any sides of the equiangular... Agent: John F. Mcnulty, Esquire Paul & Paul

20080022235 - System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells: A system and a method of creating context dependent yield variants of integrated circuit (“IC”) design components and using these variants during a physical design of an IC block to maximize manufacturing yield are described. A plurality of variants of each design component is generated and characterized with manufacturing yield... Agent: Marko Chew

20080022238 - Layout evaluating apparatus: To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual index value generating unit for generating first individual index values, a second individual index value generating unit for generating... Agent: Staas & Halsey LLP

20080022245 - Layout architecture having high-performance and high-density design: A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth... Agent: Jianq Chyun Intellectual Property Office

20080022247 - Layout method and semiconductor device: The present invention is provided with a plural cell including a transistor pair. The plural cells are arranged at equal intervals so as to configure a cell group. A inter-cell distance between a transistor in one of the cell and a transistor the other cell in each of adjacent cells... Agent: Mcdermott Will & Emery LLP

20080022250 - Chip finishing using a library based approach: A method, software in the form of a computer readable medium, and a system for designing an integrated circuit. The method comprises providing in a library of shapes, a at least one shape used to define regions of the integrated circuit in which no active chip circuits are placed; and... Agent: David Aker

20080022249 - Extending poly-silicon line with substantially no capacitance penalty: A structure and method for extending poly-silicon lines to resolve the problem of across chip linewidth variations are provided. A shorter poly-silicon line is extended by an extension line to approximately the same length as a longer neighboring poly-silicon line. The shorter poly-silicon line and the extension line are separated... Agent: Hoffman, Warnick & D'alessandro LLC

20080022251 - Interactive schematic for use in analog, mixed-signal, and custom digital circuit design: For application to analog, mixed-signal, and custom digital circuits, a system and method to improve the flow of setting up a set of simulations, a characterization, or optimization problem via an interactive circuit schematic. A system and method to visualize circuit simulation data in which at least one of the... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080022253 - Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information: A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation.... Agent: Wagner, Murabito & Hao LLP

20080022254 - System and method for improving mask tape-out process: An integrated circuit (IC) design system includes an IC design module for generating various portions of a mask layout according to a predefined specification of an integrated circuit, a mask module for assembling the various portions of the mask layout and forming a tape-out of the mask layout for mask... Agent: Haynes And Boone, LLP

20080022256 - Manufacturing method of mask and optimization method of mask bias: In a fabrication method of a semiconductor device a manufacturing method of a mask and an optimization method of a mask bias incorporating an optical proximity correction are provided. The manufacturing method of the mask incorporating an optical proximity correction can form a pattern in an excellent quality in a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080022232 - Data-mining-based knowledge extraction and visualization of analog/ mixed-signal/ custom digital circuit design flow: A system and method of generating a set of circuit simulation data, applying data mining to for knowledge extraction from the data, and graphically presenting the extracted knowledge in a format that is easy to digest to a designer.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080022233 - Method, apparatus, and computer program product for enhancing a power distribution system in a ceramic integrated circuit package: A method, apparatus, and computer program product are disclosed for automatically enhancing a power distribution system (PDS) in a ceramic integrated circuit package. The package includes multiple layers. The entire package is divided into a three-dimensional grid that includes multiple different grid cells. Information is associated with each one of... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080022237 - Device modeling for proximity effects: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from... Agent: Ibm Microelectronics Intellectual Property Law

20080022236 - System-on-a-chip for processing multimedia data and applications thereof: A system-on-a-chip integrated circuit includes a multimedia module that produces rendered output data and a high-speed interface. A processing module generates output multimedia data in accordance with at least a portion of a multimedia application in response to input multimedia data received from either the multimedia module or the high-speed... Agent: Garlick Harrison & Markison

20080022239 - System and method for determining and visualizing tradeoffs between yield and performance in electrical circuit designs: A system and method for providing visualization of tradeoff between statistical parameters and performance for an electrical circuit design.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080022242 - Board layout check apparatus and board layout check method: There is provided a board layout check apparatus for checking whether or not a guard wiring is appropriately formed, wherein a place which must be corrected is clearly displayed. The board layout check apparatus includes a printed board obtained by forming a guard wiring on a printed wiring layer, a... Agent: Birch Stewart Kolasch & Birch

20080022243 - Design structure for implementing dynamic data path with interlocked keeper and restore devices: A keeper device design structure for dynamic logic used in integrated circuit designs includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled... Agent: Richard M. Kotulak International Business Systems Corporation

20080022241 - Method for the functional verification of at least one analog circuit block: A method is provided for verifying at least one circuit block or a circuit, which has at least two interconnected circuit blocks, in which for digitalizing the signal values, in a first verification step, at least one line is supplied with the signal at the input of the block, in... Agent: Mg-ip Law, PLLC

20080022240 - Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method: A pattern data verification method for a semiconductor device, including extracting, from design data, design data corresponding to an edge portion of a mask pattern to obtain an edge portion of a pattern on a substrate to be processed, when the pattern is obtained on the substrate to be processed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080022244 - Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method: A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080022246 - Method for modeling large-area transistor devices, and computer program product therefor: A method models the electrical characteristics of wide-channel transistors, such as power transistors, by generating a lumped-element distributed circuit model. More specifically, the active area of the transistor is organized in elementary transistor cells, which are substituted by active lumped elements. Similarly the passive area of the transistor is organized... Agent: Seed Intellectual Property Law Group PLLC

20080022248 - Circuit element function matching despite auto-generated dummy shapes: Methods, systems, program products are disclosed that control placement of dummy shapes about sensitive circuit elements such that the dummy shapes are at least substantially similar for each circuit element even though the dummy shapes are auto-generated. In one embodiment, the invention includes providing dummy shape pattern pitch information to... Agent: Hoffman, Warnick & D'alessandro LLC

20080022252 - Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a... Agent: Mcdermott Will & Emery LLP

20080022255 - Method for interlayer and yield based optical proximity correction: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with... Agent: John A. Jordan, Esq

20080016476 - Hierarchical analog layout synthesis and optimization for integrated circuits: In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing... Agent: Orion Law Group

20080016475 - Method, system and program product for automated transistor tuning in an integrated circuit design: A method of tuning an integrated circuit design includes holding a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizing transistors forming a register within the integrated circuit design and thereafter optimizing transistors forming one or more clock buffers coupled... Agent: Dillon & Yudell LLP

20080016477 - Method for soft error modeling with double current pulse: A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward... Agent: Ibm Corporation (jvm)

20080016479 - Slew constrained minimum cost buffering: A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew arc added to the solution. When a buffer is selected for... Agent: Ibm Corporation (jvm)

20080016480 - System and method for driving values to dc adjusted/untimed nets to identify timing problems: A system and method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080016483 - Hierarchical analog layout synthesis and optimization for integrated circuits: In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing... Agent: Orion Law Group

20080016487 - Determining position accuracy of double exposure lithography using optical metrology: In determining position accuracy of double exposure lithography using optical metrology, a mask is exposed to form a first set of repeating patterns on a wafer, where the repeating patterns of the first set have a first pitch. The mask is then exposed again to form a second set of... Agent: Morrison & Foerster LLP

20080016478 - Parasitic impedance estimation in circuit layout: The present invention in one embodiment performs estimation of parasitic impedances in a circuit. Leaf cells of circuit components are evaluated such that their parasitic impedances are estimated, and the leaf cells are placed in a physical layout. Parasitic impedances of interconnect wiring is evaluated, and the interconnect wire routing... Agent: Schwegman, Lundberg & Woessner, P.A.

20080016481 - System and method for detecting a defect: The system includes a timing analyzer 412 for extracting a critical path in which a high accuracy is required for a signal transmission operation as compared with other portions based on circuit design data, a critical path extractor 413 for comparing the circuit design data with layout design data on... Agent: Crowell & Moring LLP Intellectual Property Group

20080016482 - Density driven layout for rram configuration module: A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place... Agent: Lsi Logic Corporation Timothy R. Croll

20080016484 - Early hss rx data sampling: A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data... Agent: Ibm Corporation

20080016485 - Mothod and system for designing a timing closure of an integrated circuit: Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between... Agent: Rosenberg, Klein & Lee

20080016486 - System and method of assessing reliability of a semiconductor: A system for assessing reliability of a semiconductor product design, the system comprising a first database for storing circuits data specifying cells of available circuits for semiconductor products; an input unit for input of reliability qualification data of tested semiconductor products; an uploading unit for uploading semiconductor product design data;... Agent: Goodwin Procter L.l.p

20080010618 - Method and device for designing semiconductor integrated circuit: A method and device for designing a semiconductor integrated circuit that easily reduces off leakage current. Wires connected to input terminals of a standard cell are exchanged with one another and a gate net list is changed so as to reduce off leakage current in accordance with a net probability... Agent: Freescale Semiconductor, Inc. Law Department

20080010619 - System and method of modification of integrated circuit mask layout: Integrated circuit mask layouts are modified for the purpose of migration to abide a new set of design rules, or for the purpose of optimization for timing, power, signal integrity and manufacturability, among other purposes. The modified layout is required to satisfy a set of constraints generated from design rules,... Agent: Marko Chew

20080010620 - Alignment of product representations: A system, method, and computer program for identifying a plurality of product representations; formulating a plurality of logical expressions from said plurality of product representations; and aligning each of said plurality of logical expressions with a variance completeness and a consistency and appropriate means and computer-readable instructions.... Agent: Ugs Corp.

20080010622 - System and method for analyzing response values sum of differential signals: A method for analyzing response values sum of differential signals includes: receiving configurations of simulation parameters; simulating differential signal paths with an analog transmission channel according to a design file; analyzing the analog transmission channel into different channel modes according to received configurations; simulating a plurality of pulse signals into... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080010621 - System and method for stopping functional macro clocks to aid in debugging: A system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in at least one... Agent: Dillon & Yudell LLP

20080010623 - Semiconductor device verification system and semiconductor device fabrication method: A semiconductor device verification system capable of verifying operation with great accuracy. A pattern matching verification system outputs interference pattern information. A physical verification system compiles the interference pattern information and a design rule and extracts a design rule applied to the interference pattern information. The physical verification system then... Agent: Staas & Halsey LLP

20080010624 - Object-oriented layout data model and integrated circuit layout method using the same: An integrated circuit layout method directly extracts plural primitive objects from a user's existing layout to expedite a new layout for reuse and migration and to gain the benefits of full coverage and minimal cost of layout design. The integrated circuit layout method comprises the steps of capturing a set... Agent: Volentine & Whitt PLLC

20080010627 - Method for automatically generating at least one of a mask layout and an illumination pixel pattern of an imaging system: c) optimizing an intensity distribution I(r) in an image plane for the semiconductor device subject to a merit function, by means of a stochastic variation by at least one of the group of the discrete mask tiles and the illumination pixels using the pre-calculated tile spread functions Vq(r) of the... Agent: Slater & Matsil LLP

20080010628 - Method of manufacturing a mask: A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first... Agent: F. Chau & Associates, LLC

20080010617 - Method of designing passive rc complex filter of hartley radio receiver: An object of this invention is to provide a method of designing a complex transfer function which can be realized in a passive RC complex filter at the same time while perfectly succeeding to features of a prototype lowpass characteristic. In this invention, as a first step, a prototype lowpass... Agent: Reed Smith LLP

20080010625 - Auto connection assignment system and method: A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating... Agent: Schmeiser, Olsen & Watts

20080010626 - System and method for creating a standard cell library for use in circuit designs: A standard cell library including a first set of cells including mixed threshold voltage cells. Each mixed threshold voltage cell includes a first threshold voltage device having a first threshold voltage and a second threshold voltage device having a second threshold voltage, in which the first threshold voltage is different... Agent: Sawyer Law Group LLP