Data processing: design and analysis of circuit or semiconductor mask inventions 12/07

20070300192 - Method for optimizing of pipeline structure placement: Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The... Agent: International Business Machines Corporation

20070300194 - Film thickness predicting program, recording medium, film thickness predicting apparatus, and film thickness predicting method: A film thickness predicting apparatus compares a measurement value of a copper plating formed on wiring grooves of various patterns measured using a TEG and a film thickness of the copper plating calculated based on a plating model and a condition file. The film thickness predicting apparatus then delivers optimal... Agent: Staas & Halsey LLP

20070300195 - Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules: In some embodiments, a method is provided for determining a localized region of overlap of first and second features from respective first and second conductive layers, and determining which enclosure rules to apply to vias formed between the first and second features. In a further aspect of the invention, a... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20070300198 - Method for creating box level groupings of components and connections in a dynamic layout system: A system and method for automatically generating a dynamic layout of a top-level canvas with an internal box layout structure providing a storage element, and a processing element capable of receiving requests to assign a plurality of components within the canvas; assessing both component data and associated connectivity data component... Agent: Tung & Associates

20070300199 - Design data creating method, design data creating apparatus and computer readable information recording medium: A design data creating method, for creating design data to which predetermined design constraint requirements are added, includes a display data converting step of converting input design constraint requirements into display data for displaying on a design drawing displayed on a display device; and a control data converting step of... Agent: Staas & Halsey LLP

20070300200 - Integrated circuit design system: The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.... Agent: Ishimaru & Zahrt LLP

20070300201 - System for configuring an integrated circuit and method thereof: With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring an integrated circuit comprises a reconfigurable integrated circuit 101, a memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070300202 - Compact standard cell: A standard cell, placed between a power rail and a ground rail in an integrated circuit, has active areas with connecting arms that extend beneath the power rail and ground rail. The connecting arms conduct current between the power and ground rails and the source regions of transistors in the... Agent: Nixon Peabody, LLP

20070300191 - Efficient electromagnetic modeling of irregular metal planes: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using... Agent: Ibm Corporation (jvm)

20070300193 - Enhanced computer-aided design and methods thereof: A Computer-Aided Design (CAD) system operates according to a method (100) having the steps of placing (102) a plurality of cells of one or more circuits in a layout, generating (106) a plurality of fanin trees from the layout, applying (110) fanin tree embedding on the plurality of fanin trees,... Agent: Akerman Senterfitt

20070300196 - Delay calculating method in semiconductor integrated circuit: An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a... Agent: Mcdermott Will & Emery LLP

20070300197 - Circuit design support method, device thereof, and circuit design support program: To enable automatic calculation of a circuit element value and a waveform by a computer. In a circuit design support for calculating a circuit element value of an analog electronic circuit to be designed, by causing a computer to execute a program having a description of a repetition calculation equation... Agent: Norris, Mclaughlin & Marcus, P.A.

20070300203 - Methods and media for forming a bound network: Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base functions that include two-input threshold OR functions and two-input... Agent: Wilmerhale/columbia University

20070294647 - Transferring software assertions to hardware design language code: Systems and methods are disclosed for transferring assertions in a software programming language source file to an HDL source file. In one such method, a first source file contains source code in a software programming language and a second source file contains HDL source code translated from the source code... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070294648 - Ic layout optimization to improve yield: A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the... Agent: Ibm Microelectronics Intellectual Property Law

20070294651 - Active trace assertion based verification system: A computer processes simulation data indicating values of circuit signals as functions of simulation time to determine whether a circuit exhibits a property defined by an assertion. The assertion expresses the property as a sequence of expressions, each a function of one or more variables, where each variable represents a... Agent: Smith-hill And Bedell, P.C.

20070294653 - Method, structures and computer program product for implementing enhanced wiring capability for electronic laminate packages: A method, structures and computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070294658 - Multi-project system-on-chip and its method: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a... Agent: Birch Stewart Kolasch & Birch

20070294649 - Method and system for logic equivalence checking: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.... Agent: Bingham Mccutchen LLP

20070294650 - Method and system for logic equivalence checking: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.... Agent: Bingham Mccutchen LLP

20070294652 - System and method for designing a common centroid layout for an integrated circuit: An exemplary common centroid layout design system receives various inputs about an integrated circuit (IC) design. Based on such inputs, the system calculates a common centroid unit, which represents an array of segments of each device in the IC design. The number of segments for each device within the common... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070294654 - Method for using mixed multi-vt devices in a cell-based design: A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization... Agent: Duane Morris LLPIPDepartment (tsmc)

20070294655 - Automatically generating an input sequence for a circuit design using mutant-based verification: One embodiment of the present invention provides a system that automatically generates an input sequence for a circuit design using mutant-based verification. During operation, the system receives a description of the circuit design. Next, the system determines a target value for a control signal in the description and a mutant... Agent: Park, Vaughan & Fleming LLP

20070294656 - Deterministic system and method for generating wiring layouts for integrated circuits: The present disclosure generally pertains to automatic wiring systems and methods for generating wiring layouts for integrated circuits. In one exemplary embodiment, a wiring router ensures that the wiring for multiple device segments is matched. That is, the wiring router defines the wiring paths such that the same or substantially... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070294657 - Methods and apparatus for defining manhattan power grid structures having a reduced number of vias: A method for producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating... Agent: Adeli Law Group PLC

20070294659 - Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations,... Agent: Ropes & Gray LLP Patent Docketing 39/361

20070288875 - Skew clock tree: A method, graphical user interface, and computer program product on a computer readable medium are disclosed for presenting a user with a display of a skew clock tree for a digital circuit design. In the preferred embodiment, a computer system receives timing analysis data for a digital circuit. The computer... Agent: Townsend And Townsend And Crew, LLP

20070288874 - System and method for designing multiple clock domain circuits: A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements... Agent: Hinckley, Allen & Snyder, LLP

20070288876 - Method and mechanism for extraction and recognition of polygons in an ic design: Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of... Agent: Bingham Mccutchen LLP

20070288877 - Design support method, design support apparatus, computer product: A design support apparatus includes a detecting unit, a determining unit, and an inserting unit. The detecting unit detects a via that connects wirings in a circuit to be designed that is expressed by layout information. The determining unit determines the connection position of a dummy via that does not... Agent: Staas & Halsey LLP

20070288879 - Semiconductor apparatus design method and execution program therefor: A design method places a dummy line in floating state in a line layer of a semiconductor apparatus by using a computer. The method includes a first step of reading layout data and placing a dummy line with a longitudinal side lying in parallel with a signal line in an... Agent: Foley And Lardner LLP Suite 500

20070288878 - Template-based gateway model routing system: A routing tool allows a user to create a set of routing templates, each specifying the shape of a routing corridor and identifying the corridor's terminal edges. Each routing template also specifies a set of constraints on routing of an unspecified number of conductors that are to be routed between... Agent: Smith-hill And Bedell, P.C.

20070288881 - Method of merging designs of an integrated circuit from a plurality of sources: The present invention is a method by which a first party provides a first design for a first integrated circuit to a second party that has a second design for a second integrated circuit, whereby the first design is to be integrated within the second design, The method provides a... Agent: Dla Piper US LLP

20070288882 - Methods and apparatus for simulating distributed effects: In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern (200) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout (100), and partitioning the physical layout into... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070288871 - Methods and apparatuses for designing integrated circuits: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent... Agent: Blakely Sokoloff Taylor & Zafman

20070288872 - Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications: A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070288873 - System for and method of analyzing printed board carrying chassis, printed board carrying chassis structure, program, and recording medium: A structure has a printed board carried by a metal chassis. A printed board carrying chassis analyzing system, a printed board carrying chassis analyzing method, a printed board carrying chassis structure, and a printed board carrying chassis analyzing program are provided to achieve a screw-fastened arrangement for predicting unnecessary radiation... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20070288880 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Saile Ackerman LLC

20070283297 - Signal processing circuit: A signal processing circuit includes a first circuit including a first clock signal generator with an output for a first clock signal and a second clock signal generator with an output for a second clock signal and an input for a comparison signal. The second clock signal is generated by... Agent: Slater & Matsil, L.L.P.

20070283299 - A method and apparatus to target pre-determined spatially varying voltage variation across the area of the vlsi power distribution system using frequency domain analysis: A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070283300 - Method and system for changing a description for a state transition function of a state machine engine: The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070283302 - Lsi analysis method, lsi analysis apparatus, and computer product: In an LSI analysis apparatus, a logic element pair extracting unit extracts an unselected logic element pair when an input unit receives circuit description input. A searching unit searches for an input pattern causing the extracted pair to perform concurrent transition. When an input pattern causing concurrent transition is found,... Agent: Staas & Halsey LLP

20070283301 - System and method of eliminating electrical violations: A system and method for correcting electrical violations, the method including examining a plurality of nets for at least one electrical violation in a sequential order of a first output-to-input traversal, and determining a net correction in each net of the plurality of nets having an electrical violation prior to... Agent: Frank C. Nicholas Cardinal Law Group

20070283304 - System and method for propagating phase constants in static model analysis of circuits: A system and method for propagating phase constants for static circuit model analysis are provided. The mechanisms of the illustrative embodiments make use of multiple phases of constant propagation to handle sequential elements in a circuit model. The phases are determined based on an oscillating clock input. In one exemplary... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070283305 - System and method for providing an improved sliding window scheme for clock mesh analysis: A method is provided and includes accessing a description of a chip, which includes sequential elements and a clock mesh. Items used include: the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh. Additionally, the method includes... Agent: Baker Botts L.L.P.

20070283306 - Layout cells, layout cell arrangement, method of generating a layout cell, method of generating a layout cell arrangement, computer program products: A layout cell includes layout cell information including information about at least one component, and a layout cell identifier identifying the layout cell. The layout cell identifier includes geometrical information about the layout cell.... Agent: Slater & Matsil LLP

20070283308 - Enhanced op3 algorithms for net cuts, net joins, and probe points for a digital design: Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a user interface enabling the user to provide preferences, limitations, and constraints in order to bias the search to be conducted, as well as using... Agent: Deborah W. Wenocur

20070283310 - Semiconductor device: A semiconductor device provided on a semiconductor substrate having a cell placing area disposed on a semiconductor substrate, the cell placing area including a plurality of basic cells supplied with power from a local power supply line, a global power supply line to supply power to the local power supply... Agent: Young & Thompson

20070283311 - Method and system for dynamic reconfiguration of field programmable gate arrays: A field programmable gate array (FPGA) and methods for executing operations using an FPGA are provided. The method includes providing a first dynamic macro and a second dynamic macro in the FPGA. The first dynamic macro and the second dynamic macro each represent logic within the FPGA that can be... Agent: Sawyer Law Group LLP

20070283312 - Method and apparatus for determining an accurate photolithography process model: One embodiment of the present invention provides a system that determines an accurate process model. During operation, the system receives process data. Next, the system receives an optical model which models an optical system of a photolithography process. The system then determines a stack model using the optical model, wherein... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070283298 - Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof: A design structure comprising an integrated circuit architecture, circuit structure, and/or instructions for fabrication thereof. The circuit structure includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently... Agent: Scully, Scott, Murphy & Presser, P.C.

20070283303 - Verification equipment of semiconductor integrated circuit, method of verifying semiconductor integrated circuit and process of manufacture of semiconductor device: The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070283307 - Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device: The layout making equipment of a semiconductor integrated circuit is provided with a logic circuit schematic design section that design a logic circuit diagram, based on a specification data on a circuit, a layout data creation section that creates a layout data, based on the logic circuit diagram, a logic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070283309 - Data models for describing an electrical device: A method and product are described for creating a model of a physical layout and/or a circuit layout of an electrical device. The layouts are defined in a user interface. A text file having metadata elements in a hierarchical format is produced that can be used by other programs.... Agent: Abb Inc. Legal Department-4u6

20070283313 - Mask pattern generating method: Disclosed herein is a mask pattern generating method for generating a mask pattern to be formed in a Levenson phase shift mask used in a light exposure process for exposing a photoresist film formed on a fabricated film to be patterned into a conductive layer to light when the conductive... Agent: Sonnenschein Nath & Rosenthal LLP