Data processing: design and analysis of circuit or semiconductor mask inventions 11/07

20070277128 - System and method for sensing shape of chip: In one embodiment of a system for sensing the shape of a chip, a support plate is provided that preferably includes at least one chip mounted thereon. A lower lighting unit is preferably disposed below the support plate to emit light through the support plate and around or between the... Agent: Marger Johnson & Mccollom, P.C.

20070277131 - Method for a fast incremental calculation of the impact of coupled noise on timing: A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more... Agent: International Business Machines Corporation Dept. 18g

20070277132 - Method of improving electronic component testability rate: A method of improving the electronic component testability rate is provided. The method includes the steps of: designing a circuit, providing electronic component data of the circuit, extracting the test data of electronic components, providing a circuit board and making a test position table, providing an electronic component test fixture... Agent: Apex Juris, PLLC Tracy M Heims

20070277133 - Model correspondence method and device: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the... Agent: Larson Newman Abel Polansky & White, LLP

20070277134 - Efficient statistical timing analysis of circuits: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An quadratic timing model is used to represent each delay element along a circuit path, wherein each element's delay has a first-order relationship to local variations... Agent: Dewitt Ross & Stevens S.c. Wisconsin Alumni Research Foundation

20070277135 - Method and device for testing delay paths of an integrated circuit: A method of testing critical delay paths of an integrated circuit design is disclosed. The method includes predicting and ranking a set of critical delay paths based on a set of predicted-delay characteristics. Integrated circuits based on the integrated circuit design are tested to determine a set of actual delay... Agent: Larson Newman Abel Polansky & White, LLP

20070277137 - Contact resistance and capacitance for semiconductor devices: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are... Agent: Texas Instruments Incorporated

20070277138 - Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design: A new method of searching paths that are suffering ESD is proposed in this invention, improving the design flow of a VLSI circuit and reducing the cost of designing the ESD circuits in a whole chip, comprising three parts, the circuit flattening, the closure algorithm, and the supernode algorithm. The... Agent: Nikolai & Mersereau, P.A.

20070277142 - Lsi design supporting apparatus and lsi design supporting program used for designing and manufacturing lsi: A computer program product for supporting an LSI design, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (c). The step (a) is a step of supplying parameters corresponding to a target to be created for an operation... Agent: Foley And Lardner LLP Suite 500

20070277145 - Iterative method for refining integrated circuit layout using compass optical proximity correction (opc): The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping... Agent: Hoffman, Warnick & D'alessandro LLC

20070277146 - Lithography simulation method, program and semiconductor device manufacturing method: A lithography simulation method which predicts the result that a pattern formed on a mask is transferred onto a sample by use of a simulation based on pattern data of the mask includes subjecting a mask layout containing a pattern whose periodicity is disturbed to the simulation. At this time,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070277129 - Technology migration for integrated circuits with radical design restrictions: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of... Agent: Hoffman, Warnick & D'alessandro LLC

20070277130 - System and method for architecture verification: A Verification environment, comprising a testbench and a test harness, which is used to automatically verify the operation of a processor device as described by a hardware description language (HDL) against the desired operation as specified by the instruction set architecture (ISA). Also described is a method of generating test... Agent: Knobbe Martens Olson & Bear LLP

20070277136 - Method of designing semiconductor device: A method of designing a semiconductor device includes: (A) dividing a layout region of a semiconductor chip into matrix by a unit region; and (B) determining an interconnection layout such that an occupation ratio of a high-density region to the layout region is less than 50%. Here, the high-density region... Agent: Young & Thompson

20070277140 - Method and system for routing: Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In... Agent: Bingham Mccutchen LLP

20070277139 - Semiconductor integrated circuit and designing method of the same, and electronic apparatus using the same: A designing method of a semiconductor integrated circuit, by which a semiconductor integrated circuit with a small amount of wire routing, a small layout area and low wire capacitance can be achieved effectively. The designing method of the semiconductor integrated circuit of the invention has a logic synthesis step of... Agent: Nixon Peabody, LLP

20070277141 - Integrated circuit arrangement, and method for programming an integrated circuit arrangement: According to the suggested principle, a comparator (9) is provided in an integrated circuit (1), which reads out an externally attachable component (4) and compares the value with the value of a reference component (6). The comparison result is forwarded to a control unit (12) which addresses at least one... Agent: Fish & Richardson PC

20070277144 - Conversion of circuit description to an abstract model of the circuit: A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the abstraction level. By changing the abstraction level, the conversion is not simply a code conversion from one language to another,... Agent: Klarquist Sparkman, LLP

20070277143 - Skeleton generation apparatus and method: A skeleton generation method includes: creating a netlist which is a circuit connection information input file format for analog circuit simulation, as subcircuit descriptions corresponding to function blocks of a system, on the basis of input and output information on the function blocks; constructing a function block skeleton of a... Agent: Frommer Lawrence & Haug LLP

20070271533 - System lsi verification system and system lsi verification method: According to one embodiment, a system LSI verification system that verifies a processor module included in a system LSI, the system comprising: a circuit description storage that stores description data that describes a design of the processor module; a verification task generator that generates a verification task file based on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070271536 - Clock model for formal verification of a digital circuit description: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in... Agent: Trellis Intellectual Property Law Group, PC

20070271537 - Command-language-based functional engineering change order (eco) implementation: In one implementation, the invention can be a computer-implemented method for generating an engineering change order (ECO) netlist for an integrated circuit (IC). The method includes performing a formal equivalence check between an implementation netlist and a reference netlist to identify one or more corresponding failed compare points in the... Agent: Mendelsohn & Associates, P.C.

20070271535 - Method for crosstalk elimination and bus architecture performing the same: The present invention discloses a method for crosstalk elimination in high-performance processors. The method, based on the combination of a deassembler and an assembler, eliminates crosstalk with fewer extra wires. The method of the present invention includes the steps of: deassembling a first piece of data to a plurality of... Agent: John S. Egbert Egbert Law Offices

20070271534 - Trace equivalence identification through structural isomorphism detection with on the fly logic writing: A method for performing trace equivalent identification by structural isomorphism detection, the method comprising: synthesizing a first netlist into a second netlist, the second netlist including two-input AND gates, inversions, inputs, constants, and registers; constructing a third netlist, the third netlist being a pseudo-canonical netlist that uses calls to algorithms... Agent: Cantor Colburn LLP - IBM Austin

20070271538 - Process for designing a circuit for synchronizing data asychronously exchanged between two synchronous blocks, and synchronization circuit fabricated by same: a step (22) for adding the said resolution time to the synthesis time parameter of the said critical flip-flop or flip-flops, the said time parameter comprising the propagation time of the active edge of the clock timing signal of the receiving block, from the input of the said signal to... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070271539 - Method and apparatus for automatic creation and placement of a floor-plan region: A method and apparatus for floor-plan region creation and placement is provided. Design information may be received. Module area may be estimated for each module in an integrated circuit. Individual module may be selected for regioning, and region size and dimensions for module may be determined. Region parameters may be... Agent: Lsi Corporation

20070271541 - Cell arrangement method for designing semiconductor integrated circuit: Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is... Agent: Mcdermott Will & Emery LLP

20070271540 - Structure and method for reducing susceptibility to charging damage in soi designs: Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a... Agent: Cantor Colburn LLP-ibm Burlington

20070271542 - Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation: A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along... Agent: Ibm Corporation (jvm)

20070271543 - Buffer insertion to reduce wirelength in vlsi circuits: Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning... Agent: Ibm Corporation (jvm)

20070271544 - Security sensing module envelope: A circuit module for user data entry is provided with a cover in electrical communication with the circuit module. The cover has a plurality of circuit elements and circuit traces which result in particular electrical characteristics sensed by the circuit module.... Agent: Nath & Associates, PLLC

20070271545 - Designing an asic based on execution of a software program on a processing system: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070266346 - Method of design for manufacturing: Disclosed is a system and method for enhancing integrated circuit designs and predicting the manufacturability. Design for manufacturability, or DFM, is an integration of DFM advisories; a DFM data kit presented in a DFM unified format; and DFM utilities utilizing the DFM data kit and the DFM advisories for enhancing... Agent: Haynes And Boone, LLP

20070266348 - Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device: A hazard check method and device for making hazard checks of logic circuits containing asynchronous paths and multi-cycle paths. The hazard check device includes a means for equivalent conversion to only pre-embedded conjunctive normal form blocks if not all of the blocks in the logic circuit were embedded conjunctive normal... Agent: Foley And Lardner LLP Suite 500

20070266352 - Method, apparatus, and system for lpc hot spot fix: Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method for creating a layout from a circuit design is described. The method includes applying a first set of hot spot conditions to a global route to produce a... Agent: Haynes And Boone, LLP

20070266355 - Distributed simultaneous simulation: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one... Agent: F. Chau & Associates, LLC

20070266356 - Ic design flow enhancement with cmp simulation: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP... Agent: Haynes And Boone, LLP

20070266358 - Yield calculation method: A yield of a device including a plurality of memory circuits is calculated. In the calculation, in the case where at least two or more memory circuits out of the plural memory circuits share a fuse used for redundancy repair, the two or more memory circuits sharing the fuse are... Agent: Mcdermott Will & Emery LLP

20070266360 - Metal thickness simulation for improving rc extraction accuracy: An integrated circuit (IC) design method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a patterned structure defined by the design layout, generating a dielectric thickness and a metal thickness on one of the plurality... Agent: Haynes And Boone, LLP

20070266362 - Method for detection and scoring of hot spots in a design layout: A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to... Agent: Haynes And Boone, LLP

20070266347 - Method of automatic synthesis of sequential quantum boolean circuits: A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an... Agent: Bacon & Thomas, PLLC

20070266349 - Directed random verification: A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested coverage event, and finds a logical, deterministic crossover point between at least two test cases. Once a... Agent: Ibm Microelectronics Intellectual Property Law

20070266351 - Method and system for evaluating computer program tests by means of mutation analysis: The invention relates to a method and system for evaluating computer program tests by means of mutation analysis. The inventive method comprises the execution (F7) of mutated programs (Pj) with the insertion (F1) of mutations (Mj) and the identification (F12) of mutated programs (Pj) which, with a pre-determined test (Tk),... Agent: Oliff & Berridge, PLC

20070266350 - Microwave circuit performance optimization by on-chip digital distribution of operating set-point: A method and circuit are outlined allowing the performance of an RF circuit to be established through the use of digital calibration data, which is stored within a programmable memory store and used to establish the control signal inputs of the RF circuit elements.... Agent: Kenyon & Kenyon LLP

20070266353 - Predictive event scheduling in an iterative resolution network: A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input.... Agent: Bingham Mccutchen LLP

20070266354 - Enhanced structural redundancy detection: A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection algorithm; determining whether a... Agent: Cantor Colburn LLP - IBM Austin

20070266357 - Timing analysis method and timing analysis apparatus: A signal timing analysis method for analyzing timing of a signal propagated along a path including instances. The method includes performing a delay calculation, generating files storing delay information, input slew rate, and output capacitance, performing static timing analysis (STA) based on the delay information, and generating an analysis result.... Agent: Staas & Halsey LLP

20070266359 - Relative floorplanning for improved integrated circuit design: A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a... Agent: Townsend And Townsend And Crew, LLP

20070266361 - Logic verification method, logic verification apparatus and recording medium: There is provided a logic verification method for performing logic verification of an integrated circuit by using device data defining functions of the integrated circuit. The logic verification method includes reading device data made up by a plurality of pieces of logic module data each including (i) first circuit data... Agent: J C Patents, Inc.

20070266364 - Method and system for context-specific mask writing: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.... Agent: Bingham Mccutchen LLP

20070266363 - System and method of automatically generating kerf design data: A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in... Agent: Greenblum & Bernstein, P.L.C

20070266365 - Integrated circuit design meethod, design assistance program and integrated circuit design system using such integrated circuit design method: [SOLVING MEANS] A trial integrated circuit is produced based on pattern information for a trial production, without using a photomask, under a common design circumstance which can be utilized in both a photomaskless step of producing an integrated circuit based on pattern information without using a photomask and a photomask... Agent: Rader Fishman & Grauer PLLC

20070261008 - Method and apparatus for user interface in home network and electronic device and storage medium therefor: A user interface method and apparatus which allow a user to intuitively control electronic devices connected to a home network by using a virtual 3D space layout diagram, and electronic devices and storage media therefor are provided. The user interface method includes: generating a virtual 3D space layout diagram based... Agent: Sughrue Mion, PLLC

20070261012 - Systematic generation of scenarios from specification sheet: A method of generating a scenario includes generating a specification model by describing a specification in a predetermined descriptive language, extracting a plurality of operations from the specification model, generating a plurality of operation descriptions, each of which corresponds to one of the operations and includes an operation name and... Agent: Staas & Halsey LLP

20070261010 - Nonlinear driver model for multi-driver systems: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used... Agent: Bever, Hoffman & Harms, LLP

20070261009 - Programmable devices to route signals on probe cards: A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to... Agent: N. Kenneth Burraston Kirton & Mcconkie

20070261011 - Modeling small mosfets using ensemble devices: A method of modeling statistical variation of field effect transistors having fingers physically measures characteristics of existing transistors and extracts a scaled simulation based on the characteristics of the existing transistors using a first model. The method creates synthetic single finger data using the scaled simulation. The method physically measures... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070261013 - Designer's intent tolerance bands for proximity correction and checking: A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions,... Agent: International Business Machines Corporation Dept. 18g

20070261014 - System and method for design entry and synthesis in programmable logic devices: A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of... Agent: Townsend And Townsend And Crew LLP/ 015114

20070261015 - Logic circuit and method of logic circuit design: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The... Agent: Martin D. Moynihan Prtsi, Inc.

20070261016 - Masking techniques and templates for dense semiconductor fabrication: A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is formed using pitch multiplication and a second pattern is formed using photolithography without pitch multiplication. The first pattern and the second pattern are transferred to a... Agent: Knobbe Martens Olson & Bear LLP

20070256038 - Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs: Methods and systems automate an approach to provide a way to convert a circuit design from a synchronous representation to an asynchronous representation without any designer or user interaction or redesign of the synchronous circuit. An optimized, automated, non-Interactive conversion of representations of synchronous circuit designs to and from representations... Agent: Jlb Consulting, Inc. C/o Intellevate

20070256042 - Method and system for incorporating via redundancy in timing analysis: A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized... Agent: Freescale Semiconductor, Inc. Law Department

20070256045 - V-shaped multilevel full-chip gridless routing: A router selects routes for nets interconnecting terminals of circuit devices within an area of an IC. The router organizes the IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary that is a probabilistic measure... Agent: Smith-hill And Bedell, P.C.

20070256037 - Net-list organization tools: The present invention provides an accurate and efficient method of organizing circuitry from a net-list of an integrated circuit, by the steps of generating a reference pattern; identifying the potential matches in the net-list using inexact graph matching; further analyzing the matches to determine if they match the reference pattern;... Agent: Price Heneveld Cooper Dewitt & Litton, LLP

20070256039 - Dummy fill for integrated circuits: Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variations caused by... Agent: Bingham Mccutchen LLP

20070256040 - Critical area computation of composite fault mechanisms using voronoi diagrams: Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC

20070256041 - Method and apparatus of core timing prediction: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused... Agent: Lsi Corporation

20070256043 - Method and system for implementing a mass data change tool in a graphical user interface: A method and system are provided for implementing a mass data change tool to update the column data for the selected rows in a table presented in the graphical user interface of a software application. The mass data change tool may include an additional row, a mass data change row,... Agent: Kenyon & Kenyon LLP

20070256044 - System and method to power route hierarchical designs that employ macro reuse: A method of routing a random logic macro (RLM) that is used multiple times in a hierarchical VLSI design without having to route each individual instantiation independently. Once an RLM has been routed and timed it can be copied and reused in a physical design as is, and does not... Agent: Greenblum & Bernstein, P.L.C

20070256046 - Analysis and optimization of manufacturing yield improvements: Techniques for improving the design of circuits, such as integrated microcircuits. A proposed circuit design is analyzed to identify design features associated with yield loss in manufactured circuits. Corrective design changes that will reduce the yield losses associated with the yield loss features then are designated. Once the corrective design... Agent: Banner & Witcoff, Ltd.

20070256047 - Integrated circuit with signal skew adjusting cell selected from cell library: An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and... Agent: Ryan, Mason & Lewis, LLP