Data processing: design and analysis of circuit or semiconductor mask inventions 10/07

20070250803 - High-level synthesis method and high-level synthesis system: The present invention generates a register transfer level description from a behavior description based on a result obtained by referring to a data path template wherein definition is given with respect to; a group of functional units where a generating method of a circuit in a register transfer level is... Agent: Mcdermott Will & Emery LLP

20070250796 - Method and computer program product for designing power distribution system in a circuit: A method for designing a power distribution system including: receiving a cross section file that contains the layout of a PCB including a location of one or more power sinks and sources on the PCB; creating an initial power distribution system; evaluating the initial power distribution system against a cost... Agent: Cantor Colburn LLP - IBM Austin

20070250797 - Method and system of modeling leakage: A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the... Agent: Greenblum & Bernstein, P.L.C

20070250798 - Method and apparatus in locating clock gating opportunities within a very large scale integration chip design: A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070250799 - Test case generation algorithm for a model checker: A method is provided for generating test cases automatically using an abstract system description in combination with a model-checking tool. The abstract system description can be used to design hardware/software systems and the generated test cases can be reused to verify the correctness of the implementation.... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc

20070250800 - Automated integrated circuit development: Customization methodology for integrated circuit (e.g., clocks) design customization using a software tool that integrates multiple integrated circuit development operations.... Agent: Blakely Sokoloff Taylor & Zafman

20070250801 - Method and apparatus to visually assist legalized placement with non-uniform placement rules: Embodiments of the present invention provide systems, methods and articles of manufacture for displaying semiconductor components in a graphical user interface and manipulating the position of semiconductor components. Embodiments of the present invention may check the placement of components against a plurality of placement rules and determine if a component... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070250802 - Switch with a pulsed serial link: A method for routing signals comprising: supplying to an input of a routing block having multiple outputs an information signal comprising a first edge and a second edge on a single line, the first and second edges being separated by a time period which represents information conveyed by the signal,... Agent: Docket Clerk

20070250804 - Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one... Agent: Pvf -- Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070250805 - System and method for examining mask pattern fidelity: A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted under a first set... Agent: Mark J. Marcelli Duane Morris LLP

20070245275 - Electromagnetic coupled basis functions for an electronic circuit: A method and system to efficiently create electromagnetic coupled basis functions for an electronic circuit that is defined by geometry data and topology data. The geometry data for the circuit are read, and a three-dimensional mesh of polygons for the circuit is created. External port geometry and internal port geometry... Agent: Law Offices Of Ronald M Anderson

20070245277 - Method and system for simulating state retention of an rtl design: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description... Agent: Morrison & Foerster LLP

20070245278 - Simulation of power domain isolation: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in... Agent: Morrison & Foerster LLP

20070245285 - Method and mechanism for implementing electronic designs having power information specifications background: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains;... Agent: San Francisco Office Of Novak, Druce & Quigg LLP

20070245271 - Frequency divider monitor of phase lock loop: A design structure for designing, manufacturing, and/or testing a frequency divider and monitoring circuit. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output... Agent: Schmeiser, Olsen & Watts

20070245270 - Method for manufacturing a programmable system in package: Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies several integrated circuits (“IC's”) for performing the set of operations. The method packages several of identified IC's into a single IC... Agent: Adeli Law Group, A Professional Law Corporation

20070245272 - Concurrent optimization of physical design and operational cycle assignment: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations concurrently to different operational cycles and different configurable circuits. In... Agent: Adeli Law Group, A Professional Law Corporation

20070245273 - Task concurrency management design method: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality... Agent: Knobbe Martens Olson & Bear LLP

20070245274 - Integrated circuit design apparatus and method thereof: An integrated circuit apparatus according to an aspect of the present invention includes: an input portion for inputting information on a physical form relating to a wiring and an element which are desired out of first schematic data as physical form information on the wiring and the element; a schematic... Agent: Amin, Turocy & Calvin, LLP

20070245276 - System, method and computer program product for designing connecting terminals of semiconductor device: A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O... Agent: John S. Pratt, Esq Kilpatrick Stockton, LLP

20070245279 - Method and system for verifying performance of an array by simulating operation of edge cells in a full array model: A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070245281 - Placement-driven physical-hierarchy generation: A method and system for performing placement-driven physical hierarchy generation in the context of an integrated circuit layout generation system is provided. This generation optimizes the physical hierarchy to improve placement of the cells in the layout, and the associated interconnect routability and delay. A new pre-clustering phase is introduced... Agent: Townsend And Townsend And Crew, LLP

20070245280 - System and method for placement of soft macros: An electronic design automation method of placing circuit components of an integrated circuit (“IC”) is provided. A synthesized circuit netlist including one or more soft macros is received and a rough global placement of this netlist is performed. A shaper function is determined. The shaper function evaluates a cost of... Agent: Townsend And Townsend And Crew, LLP

20070245284 - Dummy filling technique for improved planarization of chip surface topography: The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal... Agent: Bever, Hoffman & Harms, LLP

20070245283 - Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs: A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of... Agent: Greenblum & Bernstein, P.L.C

20070245282 - Systems, methods, and media for using relative positioning in structures with dynamic ranges: Systems, methods, and media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070245286 - Wiring layout apparatus, wiring layout method, and wiring layout program for semiconductor integrated circuit: A wiring layout apparatus includes a layout design unit configured to design a wiring layout for a semiconductor integrated circuit; a critical wiring detection unit configured to analyze a delay of signal propagation in the wiring layout so as to detect wiring strip conductors that configure a signal path whose... Agent: Amin, Turocy & Calvin, LLP

20070245289 - Memory re-implementation for field programmable gate arrays: Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based... Agent: Klarquist Sparkman, LLP

20070245287 - Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality... Agent: Adeli Law Group, A Professional Law Corporation

20070245288 - Operational cycle assignment in a configurable ic: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and... Agent: Adeli Law Group, A Professional Law Corporation

20070245291 - Incrementally resolved phase-shift conflicts in layouts for phase-shifted features: Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be placed to define critical features, wherein the pairs of shifters conform to... Agent: Bever Hoffman & Harms, LLP

20070245292 - Lithography simulation method, photomask manufacturing method, semiconductor device manufacturing method, and recording medium: A lithography simulation method includes obtaining a mask transmission function from a mask layout, obtaining an optical image of the mask layout by using the mask transmission function, obtaining a function which is filtered by applying a predetermined function filter to the mask transmission function, and correcting the optical image... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070245290 - Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry: Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070240087 - Semiconductor integrated circuit device and method of designing thereof: This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070240089 - Apparatus and method for correcting layout pattern data: A correcting apparatus of a layout pattern data includes a storage unit configured to store a layout pattern data having a hierarchical structure of cells; and a processing unit configured to correct the layout pattern data. The processing unit corrects the layout pattern data in units of cells, determines whether... Agent: Foley And Lardner LLP Suite 500

20070240092 - Methods of fabricating application specific integrated circuit (asic) devices that include both pre-existing and new integrated circuit functionality and related asic devices: A method of fabricating a semiconductor integrated circuit, such as an ASIC, and a semiconductor integrated circuit using the same, are cost effective and allow lower non-recurring engineering compared with a platform ASIC by separately embodying a cell-based base block chip and a custom block chip of a gate array... Agent: Myers Bigel Sibley & Sajovec

20070240083 - Processing apparatus: In a processing apparatus, a plurality of processors which perform different kinds of processing is integrated on a first semiconductor substrate. A plurality of memories to be managed by the plurality of processors integrated on the first semiconductor substrate is integrated on a second semiconductor substrate. The plurality of processors... Agent: Frommer Lawrence & Haug LLP

20070240082 - Shallow trench avoidance in integrated circuits: Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.... Agent: Lemoine Patent Services, PLLC C/o Portfolioip

20070240084 - System and method to improve chip yield, reliability and performance: Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules.... Agent: Greenblum & Bernstein, P.L.C

20070240085 - Method for computing the sensitivity of a vlsi design to both random and systematic defects using a critical area analysis tool: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070240086 - Range pattern definition of susceptibility of layout regions to fabrication issues: A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at... Agent: Silicon Valley Patent Group LLP

20070240088 - Vlsi artwork legalization for hierarchical designs with multiple grid constraints: A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be... Agent: Greenblum & Bernstein, P.L.C

20070240090 - Yield optimization in router for systematic defects: Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070240091 - Methods and systems for optimizing designs of integrated circuits: Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within... Agent: Blakely Sokoloff Taylor & Zafman

20070240093 - Architecture and method for providing integrated circuits: A customizable integrated circuit is programmed to provide both hardware task functions and interconnects. A plurality of execution units is executable concurrently to emulate hardware tasks. A plurality of programmable locations provides logical interconnect between the executable programs.... Agent: Donald J Lenkszus

20070240094 - Partially gated mux-latch keeper: Embodiments related to multiplexer latches (mux-latches) are presented herein.... Agent: Lee & Hayes, PLLC C/o Portfolioip

20070234244 - System and method for checking equivalence between descriptions: A behavior synthesis apparatus performs a behavior synthesis while optimizing an intermediate point pair, which is equivalent to each other only under a condition to be referenced. When an equivalence condition is provided for an intermediate cone, an equivalence condition setting unit provides the intermediate cone with the condition for... Agent: Sughrue Mion, PLLC

20070234248 - Method and apparatus for calculating power consumption, and computer product: A power consumption calculating apparatus includes a receiving unit, a specifying unit, a determining unit, an average calculating unit, an estimating unit, and a power consumption calculating unit. The receiving unit receives data of a target circuit. The specifying unit specifies a sequential circuit in the circuit. The determining unit,... Agent: Greer, Burns & Crain

20070234249 - Method and apparatus for supporting verification, and computer product: A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the... Agent: Staas & Halsey LLP

20070234254 - Timing analyzing method and apparatus for semiconductor integrated circuit: A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition. The best-case corner condition and the worst-case corner condition each include a temperature condition, with each temperature condition being a high temperature condition or a low... Agent: Staas & Halsey LLP

20070234261 - Design support device for semiconductor device, design support method for semiconductor device, and design support program for semiconductor device: The present invention provides a design support device for a semiconductor device, etc. which can significantly reduce processing steps required in constructing power source wiring patterns and can perform processing at a high speed using a small amount of resources by making conventional bump cells include global power source wiring... Agent: Staas & Halsey LLP

20070234264 - Lsi circuit designing system, antenna damage preventing method and prevention controlling program used in same: An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data after installation of wirings is read by layout reading processing and... Agent: Young & Thompson

20070234262 - Method and apparatus for inspecting element layout in semiconductor device: A method for inspecting the layout of elements included in a semiconductor device. The method includes setting paired layout inspection requirements including at least an element interval at which a paired layout is enabled, inspecting whether or not the elements that are to be inspected for paired layout satisfy the... Agent: Staas & Halsey LLP

20070234267 - Pipeline high-level synthesis system and method: According to one embodiment, a pipeline high-level synthesis system receives a high-level description and performs pipeline high-level synthesis for its loop description part to generate a pipelined circuit having a structure in which a plurality of combinational logic parts serially arranged are separated by pipeline registers. If a memory access... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070234240 - Automatically optimize performance of package execution: Various technologies and techniques are disclosed that automatically optimize package execution performance. A profiling phase executes each task in a control flow package and measures performance metrics, such as task execution length, task memory usage, task correlation to CPU versus input/output operations, network bandwidth, and running applications. An optimization phase... Agent: Microsoft Corporation

20070234241 - Data processing system and method: A data processing system and method is proposed. The data processing system is connected with a component library and an original design database. The component library includes component data including part numbers and attributes of components while the original design database stores original design data of pins, nets and codes... Agent: Edwards Angell Palmer & Dodge LLP

20070234242 - Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070234243 - Design data creating method, design data creating program product, and manufacturing method of semiconductor device: According to an aspect of the invention, there is provided a design data creating method of creating design data of a semiconductor device including extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070234247 - Automatic test component generation and inclusion into simulation testbench: Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the... Agent: Beyer Weaver LLP

20070234246 - Identifying layout regions susceptible to fabrication issues by using range patterns: A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside... Agent: Silicon Valley Patent Group LLP

20070234245 - Sub-system power noise suppression design procedure: Aspects of the disclosure provide methods and systems to design a distributed discrete capacitor bank incorporating power plane capacitance to concentrate the suppression of AC coupling to the frequencies caused by clocks and signal transitions. Aspects of the disclosure provide a procedure for designing a distributed capacitor bank from a... Agent: Oliff & Berridge, PLC.

20070234250 - Method and apparatus for supporting verification, and computer product: A verification supporting apparatus includes an acquiring unit that acquires a first verification-item list for a verification target, a functional specification of the verification target, and a sequential specification of the verification target; a keyword extracting unit that extracts a keyword about the verification target from the first verification-item list;... Agent: Staas & Halsey LLP

20070234251 - Data output clock selection circuit for quad-data rate interface: A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have... Agent: Bever, Hoffman & Harms, LLP

20070234252 - Method, system, and program product for computing a yield gradient from statistical timing: The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a... Agent: Hoffman, Warnick & D'alessandro LLC

20070234253 - Multiple mode approach to building static timing models for digital transistor circuits: A method and a system for building static models for transistor circuit design is described. This method includes performing an automatic timing model construction several times on certain problem CCCs, with different, typically incompatible sets of user-selected local information for each call. Each of the sets of local information is... Agent: H. Daniel Schnurmann Intellectual Property Law, IBM Corporation

20070234255 - Ramptime propagation on designs with cycles: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a... Agent: David Smith Lsi Logic Corporation

20070234256 - System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070234257 - Method and apparatus for circuit partitioning and trace assignment in circuit design: Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved... Agent: Blakely Sokoloff Taylor & Zafman

20070234259 - Cell placement in circuit design: A solution for managing a circuit design, which enables a cell to be incrementally placed in the circuit design based on a resulting wiring distance is provided. A cell to be placed in the circuit design is obtained along with a corresponding set of nets in the circuit design to... Agent: Hoffman, Warnick & D'alessandro LLC

20070234258 - Method for post-routing redundant via insertion in integrated circuit layout: The objective of the invention is to provide a method for post-routing redundant via insertion. The method is to construct a conflict graph from a post-routing design first, to find a maximal independent set (MIS) of the conflict graph, and to replace a single via with a double via for... Agent: Egbert Law Offices

20070234260 - Method for implementing overlay-based modification of vlsi design layout: A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device... Agent: Cantor Colburn LLP-ibm Burlington

20070234263 - Method and apparatus for describing and managing properties of a transformer coil: A method and apparatus for describing and managing properties of a transformer coil. A metadata text file is generated which contains metadata describing objects of the transformer coil. The objects are arranged hierarchically and have one or more related properties attached therewith. One or more properties of one object refer... Agent: Abb Inc. Legal Department-4u6

20070234265 - Method, system, and article of manufacture for implementing metal-fill with power or ground connection: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and... Agent: Bingham Mccutchen LLP

20070234266 - Method of optimizing ic logic performance by static timing based parasitic budgeting: Increasing need to gain higher performance and lower power in semiconductor chips and field programable gate arrays requires that optimization be done in a constructive manner with respect to physical layout. Increasing perfomance by parasitic budgeting which dictates what parasitics are acceptable to meet timing and power goals is presented.... Agent: Ronald Craig Fish

20070234268 - Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files,... Agent: Dillon & Yudell LLP

20070234269 - Light intensity distribution simulation method and computer program product: A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape distribution of an effective light source is defined includes extracting plural point light sources from a shape distribution of the effective... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP