Data processing: design and analysis of circuit or semiconductor mask inventions 09/07

20070226660 - Designing and operating of semiconductor integrated circuit by taking into account process variation: A method of designing a semiconductor integrated circuit includes defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused... Agent: Staas & Halsey LLP

20070226661 - Evolutionary design optimization using extended direct manipulation of free form deformations: An improved optimization of a design, based on direct manipulations of the object points of a design where the number and modifications of control points is kept as minimal as possible while the targeted movement of object points is realized.... Agent: Fenwick & West LLP

20070226665 - Accelerating high-level bounded model checking: An accelerated High-Level Bounded Model Checking method that efficiently extracts high-level information from the model, uses that extracted information to obtain an improved verification model, and applies relevant information on-the-fly to simplify the BMC-problem instances.... Agent: Brosemer, Kolefas & Associates, LLC (necl)

20070226666 - High-level synthesis for efficient verification: Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose... Agent: Brosemer, Kolefas & Associates, LLC (necl)

20070226664 - Method and system for verifying the equivalence of digital circuits: The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of... Agent: International Business Machines Corporation Dept. 18g

20070226671 - Apparatus and method of static timing analysis considering the within-die and die-to-die process variation: In a method and apparatus for designing semiconductor integrated circuit, a path delay information producing section produces path delay information by performing a static timing analysis based on delay information of a cell and subject circuit information. A correction table producing section calculates circuit-dependent delay variation for each combination of... Agent: Mcdermott Will & Emery LLP

20070226669 - Method and apparatus for repeat execution of delay analysis in circuit design: An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the... Agent: Greer, Burns & Crain

20070226672 - Layout determination method, method of manufacturing semiconductor devices, and computer readable program: A layout determination method determines a layout of semiconductor devices that are to be created on a substrate by carrying out an exposure process. The layout determination method determines a number of semiconductor devices to be created on one substrate, based on exposure data of the semiconductor devices, a time... Agent: Staas & Halsey LLP

20070226675 - Method of forming pattern writing data by using charged particle beam: A method of forming pattern writing data to write a predetermined pattern from layout data of a circuit by using a charged particle beam while deflecting the charged particle beam, includes inputting the layout data including a pattern ranging over a plurality of deflection regions, generating a partial pattern which... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070226659 - Extracting high frequency impedance in a circuit design using an electronic design automation tool: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented... Agent: Klarquist Sparkman, LLP

20070226662 - Method and apparatus of rapid determination of problematic areas in vlsi layout by oriented sliver sampling: A method and system for identifying problematic areas in a very large scale integrated (VLSI) layout. The method and system includes defining one or more sample area and overlaying the one or more sample area onto at least a portion of a layout having a plurality of structures. The method... Agent: Greenblum & Bernstein, P.L.C

20070226663 - Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits: A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. Ai(t)=>Zi(t)), wherein Ai(t) present an initial state and... Agent: 24ip Law Group Usa, PLLC

20070226668 - Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a... Agent: Bever, Hoffman & Harms, LLP

20070226667 - Static timing slacks analysis and modification: A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint... Agent: Hoffman, Warnick & D'alessandro LLC

20070226670 - Variable delay circuit, recording medium, logic verification method and electronic device: There is provided a variable delay circuit to be implemented in an integrated circuit, the variable delay circuit including: a variable delay assigning section that assigns a variable time delay to an input signal in an actual operation of the integrated circuit, the variable time delay being varied within a... Agent: Osha Liang L.L.P.

20070226673 - Method of reducing correclated coupling between nets: Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070226674 - System and method for semiconductor device fabrication using modeling: System and Method for Semiconductor Device Fabrication Using Modeling System and method for using adjustment patterns as well as physical parameters as targets to control mask structure dimensions using optical proximity correction. A preferred embodiment includes defining targets based on definition rules and adjusting mask layer structures based on the... Agent: Slater & Matsil LLP

20070226676 - Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method: A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070226677 - Performance in model-based opc engine utilizing efficient polygon pinning method: Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the... Agent: Law Office Of Delio & Peterson, LLC.

20070220453 - Method for forming reset operation verifying circuit: In a step 8, storage elements contained in sequential circuits are discriminated from each other with respect to circuit design data which contains the sequential circuit which is reset by an asynchronous reset signal and the sequential circuit which is not reset by the asynchronous reset signal. In a step... Agent: Mcdermott Will & Emery LLP

20070220452 - Semiconductor device: There is provided a semiconductor device including: plural macros each having plural normal blocks and a redundant block to be used as a replacement for a normal block; a first replacement information storage unit storing first replacement macro information to designate a macro to be subjected to the replacement out... Agent: Arent Fox PLLC

20070220457 - Method and apparatus for creating simplified false-path description on false path, and computer product: An apparatus for creating a simplified false-path description on a false path among paths in a target circuit extracts, from descriptions on the paths, a target path description on a target path. The apparatus judges whether the target path is a false path based on the target path description. The... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070220465 - Automatic estimation method, apparatus, and recording medium: Data for automatic layout processing is obtained, a plurality of values used for the estimation of an estimated value to be assigned for the automatic layout processing is prepared from the obtained data, and estimation of the estimated value is automatically performed using the prepared plurality of values. The estimation... Agent: Staas & Halsey LLP

20070220467 - Timing analysis method and apparatus, computer-readable program and computer-readable storage medium: A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit... Agent: Staas & Halsey LLP

20070220471 - Cell placement taking into account consumed current amount: A computer-readable record medium having a program embodied therein for causing a computer to place cells. The program includes codes for causing the computer to perform deriving an amount of current consumed by each cell constituting a net list, placing a cell of interest in a layout plane while securing... Agent: Arent Fox PLLC

20070220473 - System and apparatus for designing layout of a lsi: A judgment section determines whether or not a reduction in the power dissipation is possible by relocation of an improvement-target cell. If a reduction in the power dissipation is possible, a calculation section calculates the delay time of a target path including the improvement-target cell to obtain a possible shift... Agent: Mcginn Intellectual Property Law Group, PLLC

20070220475 - Information processing system, an information apparatus, macro executing method, and storage medium: An information processing system in which a warning is generated in advance when a macro including unsupported functions is executed, realizing improved usability for users. A multi-function apparatus and a server holding at least one macro indicative of a procedure for executing at least one function are connected to each... Agent: Rossi, Kimms & Mcdowell LLP.

20070220477 - Circuit-pattern-data correction method and semiconductor-device manufacturing method: Circuit-pattern-data correction method and semiconductor-device manufacturing method which prevent excessive correction from being made when model-based proximity-effect correction (OPC) is applied to a corrected circuit pattern, the excessive correction being caused by a step (difference in level) close to a circuit-pattern corner in the corrected circuit pattern, and the step... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070220450 - Computer-executable circuit drawing file integration interface and system thereof: A computer-executable circuit drawing file integration interface and system thereof is provided. The interface and system are used to merge more than one circuit drawing file into a consolidated circuit drawing file. The interface comprises a first file selection window, used to enable the user to select and preview the... Agent: Birch Stewart Kolasch & Birch

20070220451 - Method for modeling and documenting a network: A network documentation system computer program (302) for documenting a network (100) receives a configuration of elements (205) within the network (100). Methodology (320) of the program represents the elements (205) by nodes (336) in a model of the network (100). Each of the nodes (336) is defined by one... Agent: Meschkow & Gresham, P.L.C

20070220454 - Analyzing structural design relative to vibrational and/or acoustic loading: A computer-performed method of designing a structure. User-selected design parameters are input to a parametric model of the structure. Boundary conditions and load conditions are applied to the model to determine a response of the structure to the conditions. Based on the load conditions, an analysis method is selected. The... Agent: Harness, Dickey & Pierce, P.L.C

20070220455 - Method and computer program for efficient cell failure rate estimation in cell arrays: A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070220456 - On-chip test circuit and method for testing of system-on-chip (soc) integrated circuits: A system and method of testing IP cores contained in a system-on-chip integrated circuit is disclosed. An operation command is received on an input/output port of the circuit. The operation command includes an operation code component, data component(s), and expected time component. The received operation command is processed to supply... Agent: Kathy Manke Avago Technologies Limited

20070220459 - Capacitance extraction of intergrated circuits with floating fill: The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level... Agent: Peter A. Haas, Esquire

20070220463 - Inspection system: An inspection system applicable to a data processing device installed with a PCB (printed circuit board) design software and a display unit is proposed, wherein the PCB design software is used for creating PCB totems for a multi-layer PCB, the display unit is used to display an user interface provided... Agent: Edwards Angell Palmer & Dodge LLP

20070220461 - Method and system for sequential equivalence checking with multiple initial states: A method, system and computer program product for performing equivalence checking of a circuit design are disclosed. The method includes importing a first design comprising a first register set and a different second design comprising a second register set and importing a mapping between corresponding initial states of the first... Agent: Dillon & Yudell LLP

20070220458 - Method for detecting semiconductor manufacturing conditions: A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a... Agent: North America Intellectual Property Corporation

20070220464 - Method for dynamically adjusting parameter values of part heights to verify distances between parts: A method for dynamically adjusting parameter values of part heights to verify the distances between parts is provided. The method comprises, inputting multiple sets of limiting conditions for part heights through a setting interface; and verifying whether the parts are appropriately positioned in a circuit diagram according to the limiting... Agent: Rabin & Berdo, PC

20070220460 - Method for verifying line information in a layout and system thereof: A method for verifying line information in a layout and system thereof are provided. The verification method comprises obtaining and arranging a line data to classify the types of the line data; generating a corresponding line information record file after the line data is classified; sending a message appended with... Agent: Harness, Dickey & Pierce, P.L.C

20070220462 - Verification of an extracted timing model file: A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell... Agent: Lsi Corporation

20070220468 - Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits: A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack... Agent: Dillon & Yudell LLP

20070220466 - Methods and apparatus for reducing timing skew: Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout distance of each signal path. Among these identified signals, a longest signal path is found and the signal paths of the remaining identified signals are... Agent: Priest & Goldstein, PLLC

20070220469 - Method and system for designing and electronic circuit: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070220470 - Automating optimal placement of macro-blocks in the design of an integrated circuit: Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of optimalness for each placement is computed. A new set of placements is generated, with each placement being generated from multiple (“chosen placements”) of the first set of... Agent: Texas Instruments Incorporated

20070220472 - Computer aided wave-shaped circuit line drawing method and system: A computer aided wave-shaped circuit line drawing method and system is proposed, which is designed for use with a computer platform for providing a user-operated wave-shaped circuit line drawing function, and which is characterized by the utilization of computer-aided graphic drawing technology to allow a user to define a set... Agent: Edwards Angell Palmer & Dodge LLP

20070220474 - Method for facilitating power/ground wiring in a layout: A method for facilitating the power/ground wiring in layout is provided, which comprises searching more than one power line or more than one ground line according to the key words of the line names; specifying the power lines correspond to a power layer or the ground lines correspond to a... Agent: Harness, Dickey & Pierce, P.L.C

20070220476 - Multilayer opc for design aware manufacturing: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper... Agent: International Business Machines Corporation Dept. 18g

20070214437 - Semiconductor integrated circuit device and its circuit inserting method: A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable generator is off, a second circuit whose output frequently changes, an input controller which receives the respective outputs from the second circuit... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070214444 - Semiconductor memory device and semiconductor device: Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other components brought by the development of microfabrication process such as a process of fabricating large-capacity DRAMs as hard macros. A memory array region and... Agent: Stevens, Davis, Miller & Mosher, LLP

20070214438 - Method for static power characterization of an integrated circuit: A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to... Agent: North America Intellectual Property Corporation

20070214439 - Methods of deriving switch networks: A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as... Agent: Harness, Dickey & Pierce, P.L.C

20070214442 - A method for predicting inductance and self-resonant frequency of a spiral inductor: In this invention, a closed-form integral model for on-chip freely suspended rectangular spiral inductor is presented. The model of this invention bases on the Kramers-Kronig relations, field theory, and solid state physics to characterize a spiral inductor which RFIC designers could easily have the optimal design utilizing this analytical method.... Agent: Birch Stewart Kolasch & Birch

20070214443 - Circuit verification apparatus, circuit verification method, and signal distribution method for the same: A circuit to be verified is divided into a plurality of circuit parts. A plurality of programmable devices are provided for implementing functional operation of the divided circuit parts through a simulation. Wiring used in the circuit to be verified for supplying a signal SX to be given at the... Agent: Scully Scott Murphy & Presser, PC

20070214441 - Isolated pwell tank verification using node breakers: A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are... Agent: Texas Instruments Incorporated

20070214440 - Method for indicating differential signal lines in a layout: A method for indicating differential signal lines in a layout is provided, which comprises searching line groups having similar line names at first; dividing the line groups into a first line and a second line; confirming that the first and second lines are connected to a same circuit element; highlighting... Agent: Rabin & Berdo, PC

20070214445 - Element placement method and apparatus: A method and a device for performing placement of a plurality of elements for circuit design. A potential location is assigned to each element and a placement engine is assigned to each potential location. Pairing operations are performed, in parallel, between placement engines to determine whether to perform exchange of... Agent: Alessandro Steinfl C/o Ladas & Parry

20070214446 - Design stage mitigation of interconnect variability: The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid... Agent: Hoffman, Warnick & D'alessandro LLC

20070214447 - Behavioral synthesis apparatus, behavioral synthesis method, method for manufacturing digital circuit, behavioral synthesis control program and computer-readable recording medium: An A behavioral synthesis apparatus according to the present invention for performing a computer-automated synthesis of a circuit description of a register transfer level from a behavioral description describing a process operation of a circuit, wherein an output of a target computing unit is input to a plurality of subsequent... Agent: Birch Stewart Kolasch & Birch

20070214448 - Orientation dependent shielding for use with dipole illumination techniques: A method of printing a pattern having vertically oriented features and horizontally oriented features on a substrate utilizing dipole illumination, which includes the steps of: identifying background areas contained in the pattern; generating a vertical component mask comprising non-resolvable horizontally oriented features in the background areas; generating a horizontal component... Agent: Mcdermott Will & Emery LLP

20070209026 - Identifying parasitic diode(s) in an integrated circuit physical design: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction... Agent: Greenblum & Bernstein, P.L.C

20070209027 - Simulation method for semiconductor circuit device and simulator for semiconductor circuit device: A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias gate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated.... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20070209028 - Resonant tree driven clock distribution grid: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20070209029 - Slm lithography: printing to below k1=.30 without previous opc processing: Previously disclosed methods and devices are extended in this application by two-dimensional analysis of optical proximity interactions and by fashioning a computationally efficient kernel for rapid calculation of adjustments to be made. The computations can be made in realtime, whereby the use of OPC assist features can be reduced, with... Agent: Haynes Beffel & Wolfeld LLP

20070209030 - System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the... Agent: Winstead Sechrest & Minick P.C.