Data processing: design and analysis of circuit or semiconductor mask inventions 08/07

20070204245 - Method for accelerating the rc extraction in integrated circuit designs: The present invention provides a system and method for accelerating the resistance and capacitance (RC) extraction process by performing parallel and distributed processing. The method includes the dividing of a given integrated circuit (IC) design into a limited number of non-overlapping tile blocks, distributing tile blocks to standard RC extraction... Agent: Blakely Sokoloff Taylor & Zafman

20070204247 - Critical path estimating program, estimating apparatus, estimating method, and integrated circuit designing program: A computer-readable recording medium on which is recorded a program, which is used by a computer for estimating a critical path among a plurality of paths given as paths within an integrated circuit, for causing the computer to execute a process, the process comprising receiving from a memory inputs of... Agent: Staas & Halsey LLP

20070204248 - Delay analyzing method, delay analyzing apparatus, and computer product: A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain Ltd.

20070204251 - Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high... Agent: Young & Thompson

20070204253 - Routing display facilitating task of removing error: A layout editor apparatus draws line segments constituting a first interconnect line connecting between an output pin and a first input pin so as to draw the first interconnect line as a straight line formed of the line segments connected in a line extending from the output pin only in... Agent: Staas & Halsey LLP

20070204242 - Gate modeling for semiconductor fabrication process effects: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation... Agent: Trellis Intellectual Property Law Group, PC

20070204243 - Stress analysis method, wiring structure design method, program, and semiconductor device production method: A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070204246 - Method and system for logic verification using mirror interface: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost... Agent: Connolly Bove Lodge & Hutz LLP (ibm Microelectronics Division)

20070204244 - Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof: A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce... Agent: International Business Machines Corporation Dept. 18g

20070204249 - A method, apparatus and computer program product for optimizing an integrated circuit layout: A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact they have on the yield of the integrated circuit design. The layout is optimized according to the prioritized base ground rules... Agent: Ibm Microelectronics Intellectual Property Law

20070204252 - Methods and systems for placement: Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a... Agent: Walstein Bennett Smith Iii

20070204250 - Stress-managed revision of integrated circuit layouts: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070204254 - Circuit diagram drafting system and method and computer program product: A circuit diagram drafting system for drafting a circuit diagram comprised of a plurality of circuit components and connections connecting terminals of the circuit components, the circuit diagram drafting system provided with a display unit for displaying the circuit diagram and a managing unit for attaching and managing a line... Agent: Staas & Halsey LLP

20070204256 - Interconnection modeling for semiconductor fabrication process effects: In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object in a drawn design is determined based on... Agent: Trellis Intellectual Property Law Group, PC

20070204255 - Net routing: A solution for routing a net based on a slew and/or delay for one or more critical sinks in the net is provided. To this extent, the solution can generate electrical connection information for a circuit by generating a routing tree for each net in the circuit. When the net... Agent: Hoffman, Warnick & D'alessandro LLC

20070198957 - Circuit simulator and circuit simulation program storage medium: A circuit simulator includes: a DC analysis section which analyses a static stable potential on a transmission circuit if a capacitor which blocks a DC current while allowing an AC current to pass therethrough is connected in series in the line of the transmission circuit; and an initial potential application... Agent: Staas & Halsey LLP

20070198958 - Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout: One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070198967 - Computation of electrical properties of an ic layout: A system for calculating electrical properties of features to be created in an integrated circuit. All or a portion of a desired layout design is corrected for photolithographic or other process distortions using one or more resolution enhancement techniques. A simulated layout image of a corrected layout is used as... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070198965 - Simulation method and semiconductor device fabrication method: The simulation method is for simulating a pattern to be transferred onto a photoresist film by exposure using a photomask with a main pattern 10 and an assist pattern 12 formed on. The simulation is made, using data given by adding a bias value to a design dimension of the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070198955 - Method and apparatus for monitoring cross-sectional shape of a pattern formed on a semiconductor device: A method is provided for estimating a cross-sectional shape or for monitoring manufacturing process parameters of a semiconductor device pattern to be measured. In this method, in order to enable SEM-based management of the cross-sectional shape or manufacturing process parameters of the pattern to be measured, the association between the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070198956 - Method and system for improving yield of an integrated circuit: Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising... Agent: Morrison & Foerster LLP

20070198959 - Hardware-based hdl code coverage and design analysis: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the... Agent: Blakely Sokoloff Taylor & Zafman

20070198960 - Methods for tiling integrated circuit designs: Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then routing all tiles in parallel, each tile being independently routed by a standard router. Thereafter, routed tiles are... Agent: Blakely Sokoloff Taylor & Zafman

20070198961 - Technology migration for integrated circuits with radical design restrictions: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to... Agent: Hoffman, Warnick & D'alessandro LLC

20070198962 - Semiconductor integrated circuit and method of designing layout of the same: A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070198963 - Calculation system for inverse masks: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares... Agent: Klarquist Sparkman, LLP

20070198966 - Method for time-evolving rectilinear contours representing photo masks: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati

20070198964 - Multi-dimensional analysis for predicting ret model accuracy: A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the... Agent: Klarquist Sparkman, LLP

20070192757 - Pattern generation method and charged particle beam writing apparatus: A pattern generation method includes changing a dimension of a pattern included in each mesh-like region of a plurality of mesh-like regions by using an area of the pattern and a total sum of lengths of circumferential sides of the pattern included in each mesh-like region to correct a dimension... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070192758 - Exposure data generation method and device, exposure data verification method and device and storage medium: Exposure verification is applied to exposure data indicating a pattern to be exposed by a charged particle beam. If an error point is extracted from the exposure data by the exposure verification, the values of coefficients are modified and exposure data is regenerated taking into consideration the coefficients whose values... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070192751 - Method and apparatus to reduce random yield loss: One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070192752 - Influence-based circuit design: An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is... Agent: Hoffman, Warnick & D'alessandro LLC

20070192755 - Apparatus and method to facilitate hierarchical netlist checking: An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification or circuit properties within a circuit representation. For a hierarchical representation of a circuit, a minimum number of modified circuit entities are created and added to the hierarchical... Agent: Dickstein Shapiro LLP

20070192754 - Method for treating design errors of a layout of an integrated circuit: Embodiments of the invention provide a method for treating errors during the checking of a design of an integrated circuit. In one embodiment, the method includes checking the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells, detecting a design... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070192753 - Technique for generating input stimulus to cover properties not covered in random simulation: A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where wherein a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property... Agent: Osha Liang L.L.P./sun

20070192756 - Method for time-evolving rectilinear contours representing photo masks: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati

20070186194 - Simulation method and simulation program: There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained... Agent: Miles & Stockbridge PC

20070186196 - Position-dependent variation amount computation method and circuit analysis method: Using layout position information as input, in a position-dependent variation amount calculation step, position-dependent variation amount information which is a variation amount of a characteristic parameter or a shape parameter variable depending on an arrangement position of each element constituting a design target semiconductor integrated circuit is calculated. Thereafter, a... Agent: Mcdermott Will & Emery LLP

20070186205 - Managing and controlling the use of hardware resources on integrated circuits: Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed... Agent: Klarquist Sparkman, LLP

20070186195 - Method and system for debugging using replicated logic and trigger logic: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of... Agent: Blakely Sokoloff Taylor & Zafman

20070186197 - Design verification using formal techniques: Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance... Agent: Brake Hughes Bellermann LLP

20070186198 - Generation of an extracted timing model file: A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core.... Agent: Lsi Logic Corporation

20070186199 - Heuristic clustering of circuit elements in a circuit design: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070186200 - Method and apparatus for facilitating cell placement for an integrated circuit design: One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070186201 - Method for designing cell layout of semiconductor integrated circuit and computer readable medium in which a cell layout design program is recorded: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070186202 - Method and apparatus for insertion of filling forms within a design layout: A method and apparatus for insertion of filling forms within a design layout are described. One or more jog areas are identified within a circuit design layout. Subsequently, multiple filling forms are inserted within the circuit design layout, each filling form being configured to eliminate a corresponding jog area within... Agent: Qualcomm Incorporated

20070186203 - Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block: A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.... Agent: Staas & Halsey LLP

20070186204 - Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout: An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070186206 - System, masks, and methods for photomasks optimized with approximate and accurate merit functions: Photomask patterns are represented using contours defined by mask functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati

20070186208 - Mask-pattern determination using topology types: A method for determining a mask pattern is described. During the method, a first mask pattern that includes a plurality of second regions corresponding to the first regions of the photo-mask is provided. Then, a second mask pattern is determined based on the first mask pattern and differences between a... Agent: Wilson Sonsini Goodrich & Rosati

20070186207 - Method and apparatus for printing patterns with improved cd uniformity: An aspect of the present invention includes a method to pattern a workpiece with improved CD uniformity using a partially coherent electromagnetic radiation source. Said method including the actions of: determining, for a plurality of layers in said workpiece, CD uniformity as a function of a number of exposure flashes,... Agent: Haynes Beffel & Wolfeld LLP

20070180412 - Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole: A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and... Agent: Lee & Morse, P.C.

20070180410 - System and method for reducing the power consumption of clock systems: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed... Agent: Larson Newman Abel Polansky & White, LLP

20070180411 - Method and apparatus for comparing semiconductor-related technical systems characterized by statistical data: A method and an apparatus are provided for comparing a first semiconductor-related technical system with a second semiconductor-related technical system using statistical means. First statistical data characterizing the first technical system and second statistical data characterizing the second technical system are provided. A statistical test comparing the first statistical data... Agent: Brinks Hofer Gilson & Lione Infineon

20070180413 - Chip design verification apparatus and method: Chip design verification apparatus and method. The method of verifying the chip design includes a software side operation step of transmitting output data generated by the operation of the software block to the interface means, determining whether the output data of the hardware block received via the interface means is... Agent: Cantor Colburn, LLP

20070180414 - Facilitating structural coverage of a design during design verification: One embodiment of the present invention provides a method and a system that facilitates structural coverage of a design during a design verification process. During operation, the system receives a hardware description of the design, which contains one or more module instances and a set of structural coverage targets for... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070180415 - Method of leakage optimization in integrated circuit design: This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells, identifies corresponding candidate cells having the same function and swaps a candidate design cell having a least leakage... Agent: Texas Instruments Incorporated

20070180416 - System and method for design development: This invention relates to a system and methods for developing designs. In one embodiment, a method includes electronically distributing a specification for a design to a distributed community of designers, receiving designs from each of a subset of the community of designers in response to the distributed design specification, screening... Agent: Goodwin Procter LLP Patent Administrator

20070180418 - Clock scheme for circuit arrangement: The present invention provides a circuit arrangement comprising a clock conductor (230-3) coupled to a number of circuit components (210-c, 210-d, 210-e), each said circuit component being coupled to the clock conductor with a respective filter (240-1, 240-2), wherein at least one of the filters is arranged to pass a... Agent: Motorola, Inc.

20070180417 - System and method of spatial/tabular data presentation: A system and method of spatial/tabular data presentation. Display data is identified for display. Relations for the display data are identified. The display data is displayed in a data display having a tabular column and a spatial column. Data identifiers are displayed in the tabular column and spatial identifiers connected... Agent: Cardinal Law Group

20070180419 - Various methods and apparatuses to route multiple power rails to a cell: Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A... Agent: Blakely Sokoloff Taylor & Zafman

20070180420 - Designing a circuit apparatus with multiple propagation speeds of signals: Designing a circuit apparatus involves determining locations and lengths of routing paths for signals, routing paths of a first length range being located in a first layer, and routing paths of a second length range being located in a second layer; determining propagation speeds for the signals to propagate through... Agent: Hewlett Packard Company

20070180421 - Method and system for automatically generating schematics: Method and system for automatically generating schematic diagrams of an assembly is provided. The method includes providing one or more identifiers for an assembly, the identifiers providing index to an assembly and component database. A plurality of components for the assembly is retrieved from the database based on the identifiers... Agent: Klein, O'neill & Singh, LLP

20070180422 - Generating rules for nets that cross package boundaries: In an embodiment, data models are stitched into a stitched data model, where each of the data models has nets and at least one of the nets crosses a package boundary. A subset of the nets from the stitched data model are selected based on a constraint, and the subset... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070180423 - Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights: In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different... Agent: Dillon & Yudell LLP