Data processing: design and analysis of circuit or semiconductor mask inventions 07/07

20070174795 - System and method for synthesis reuse: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.... Agent: Morrison & Foerster LLP

20070174800 - Methods and systems for analyzing layouts of semiconductor integrated circuit devices: Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate,... Agent: Myers Bigel Sibley & Sajovec

20070174802 - Method of adjusting pattern density: A method of adjusting pattern density includes determining a reference pattern density, defining dummy generation fields and designed patterns, forming basic dummy patterns on the dummy generation fields, evaluating a total pattern density from a sum of a density of the designed patterns and a density of the basic dummy... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070174803 - Method for concurrent search and select of routing patterns for a routing system: A method for concurrent search and select of routing patterns for a routing system is provided. The provided method introduces a metric for indicating the goodness of a routing pattern for guiding the selection of search engine at the route finding stage. Next, the method explores routes based on a... Agent: Birch Stewart Kolasch & Birch

20070174793 - Automatic design device, automatic design method, and automatic design program: An automatic design device includes: a calculating section calculating additional geometries added to basic geometries including wiring lines and vias arranged on a chip region; a classifying section classifying the additional geometries into at least an additional graphic required for manufacture and an additional graphic required for circuit characteristics in... Agent: Foley And Lardner LLP Suite 500

20070174794 - Method and apparatus for automated synthesis of multi-channel circuits: Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a... Agent: Blakely Sokoloff Taylor & Zafman

20070174796 - Deflection analysis system and method for circuit design: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated... Agent: Scully Scott Murphy & Presser, PC

20070174797 - Predicting ic manufacturing yield by considering both systematic and random intra-die process variations: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070174798 - Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver: A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability... Agent: Dillon & Yudell LLP

20070174799 - Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver: A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable depth. A composite target is verified, using a... Agent: Dillon & Yudell LLP

20070174801 - Programmable via modeling: A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have... Agent: Connolly Bove Lodge & Hutz LLP

20070174805 - Debugging system for gate level ic designs: A register transfer level (RTL) IC design describing a IC as comprising a plurality of logic blocks communicating via signals and using a high level language to describe the logic blocks according to the logical relationships between signals they receive and signals they generate. A computer-aided synthesizer processes an RTL... Agent: Smith-hill And Bedell, P.C.

20070174804 - Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis: The device for logic synthesis comprises: means to store node table 8 storing Binary Decision Diagram for Characteristic Function (BDD_for_CF) of the characteristic function χ(X, Y) of the multiple-output logic function f(X), means to store LUTs 16, means to reduce by shorting 11 partitioning BDD_for_CF into the subgraphs B0 and... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070174806 - Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs: A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of... Agent: Dillon & Yudell LLP

20070174808 - Method and apparatus for determining a process model that uses feature detection: One embodiment can provide a system for determining a process model that models an effect of one or more semiconductor manufacturing processes. During operation, the system can receive a test layout. Next, the system can receive empirical data which is obtained using a process that includes subjecting the test layout... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070174807 - Semiconductor device manufacturing method, library used for the same, recording medium, and semiconductor device manufacturing system: To provide a semiconductor device manufacturing method of making a pattern formation possible with high precision at a high speed, the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each... Agent: Mcdermott Will & Emery LLP

20070168893 - System and method for generating a plurality of models at different levels of abstraction from a single master model: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070168894 - Method and device for supporting verification, and computer product: In a verification support device, a logical expression expressing an operation of a pattern generator can be acquired. The pattern generator includes a basic pattern generator, priority pattern generators, priority pattern selection conditions, and selector circuits. The selector circuits connect the basic pattern generator, the priority pattern generators, and the... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070168896 - Method and apparatus for verifying logic circuit: A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification... Agent: Mills & Onello LLP

20070168902 - Method for high-level synthesis of semiconductor integrated circuit: A Control Data Flow Graph (CDFG) which is an intermediate representation obtained by analyzing a behavioral-level circuit description of hardware, is subjected to a process of changing a shape of the CDFG by adding an operation before or after scheduling, so as to conceal design information. A CDFG to which... Agent: Mcdermott Will & Emery LLP

20070168895 - Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit: An automatic design method of a semiconductor integrated circuit includes: increasing an interval between a plurality of wiring patterns provided on a chip region to relieve a density of the wiring patterns based on first reference information including a criterion about a restriction of wiring length and second reference information... Agent: Foley And Lardner LLP Suite 500

20070168897 - Hierarchical signal integrity analysis using interface logic models: Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information... Agent: Bever, Hoffman & Harms, LLP

20070168898 - Method and system for detailed placement of layout objects in a standard-cell layout design: A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their... Agent: Lawrence Edelman The Law Office Of Lawrence Edelman

20070168899 - Design method and architecture for power gate switch placement and interconnection using tapless libraries: A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these... Agent: Macpherson Kwok Chen & Heid LLP

20070168900 - Vlsi timing optimization with interleaved buffer insertion and wire sizing stages: The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires... Agent: Lynn L. Augspurger IBM Corporation

20070168901 - Library creating apparatus and method, and recording medium recording library creating program thereon: In order to efficiently create a library of characteristic values of a low hierarchical circuit, which library is used in operation verification of circuitry including low hierarchical circuitry and high hierarchical circuitry, so that the time period necessary to create a library is considerably reduced, the present apparatus includes a... Agent: Staas & Halsey LLP

20070168903 - Method for correcting a mask design layout: A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction... Agent: Greer, Burns & Crain

20070162879 - System and method for approximating intrinsic capacitance of an ic block: A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compilable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC... Agent: Shreen K. Danamraj Danamraj & Youst, P.C.

20070162881 - Layout method, cad apparatus, computer-readable program and computer-readable storage medium: A layout method for a layout design of a circuit includes a simulation step carrying out a simulation of the circuit, a specifying step specifying a maximum current value to flow between terminals of each of elements of the circuit and specifying a shape of each of the elements, and... Agent: Staas & Halsey LLP

20070162883 - Method for creating new via: A method for creating new vias in an integrated circuit chip. The method automatically creates a plurality of new vias around an original via for electrically connecting two metal layers to each other in circuit layout data of the integrated circuit chip. The new vias also electrically connect the two... Agent: Rabin & Berdo, PC

20070162880 - Single event transient immune antenna diode circuit: An antenna diode circuit is described. The antenna diode circuit includes two diodes connected in series between a signal line and ground. Alternatively, the antenna diode circuit is connected in series between a signal line and a power supply. In addition to protecting the signal line from charge accumulation during... Agent: Honeywell International Inc.

20070162884 - Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides,... Agent: Mcdermott Will & Emery LLP

20070162882 - Design support system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, design support program of semiconductor integrated circuit and method of manufacturing semiconductor integrated circuit: According an aspect of the invention, there is provided a design support system of a semiconductor integrated circuit includes: a first unit configured to determine a wiring path by calculating wiring resource consuming information for carrying out a connection through a multi-cut via in case that the connection is carried... Agent: Foley And Lardner LLP Suite 500

20070162885 - Semiconductor device layout method, a computer program, and a semiconductor device manufacture method: A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value.... Agent: Cooper & Dunham, LLP

20070162886 - Customizable development and demonstration platform for structured asics: The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible enough for a number of possible application developments.... Agent: Lsi Logic Corporation

20070162889 - Method and apparatus for providing optical proximity features to a reticle pattern for deep sub-wavelength optical lithography: A method of generating a mask design having optical proximity correction features disposed therein. The methods includes the steps of obtaining a desired target pattern having features to be imaged on a substrate; determining an interference map based on the target pattern, the interference map defining areas of constructive interference... Agent: Mcdermott Will & Emery LLP

20070162888 - Method and apparatus to determine if a pattern is robustly manufacturable: One embodiment provides a method to determine if a pattern is robustly manufacturable. During operation, the system may receive a first pattern and a design intent, wherein the first pattern is intended to generate the design intent. Next, the system may determine a second pattern using the design intent, wherein... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070162887 - Method of fabricating photo mask: Provided is a method of fabricating a photo mask. The method includes preparing a model group including optical proximity correction (OPC) models and generating a preliminary mask layout using an integrated circuit (IC) layout. A contour image may be produced from the preliminary mask layout through a simulation using an... Agent: Harness, Dickey & Pierce, P.L.C

20070157131 - System and method for incremental synthesis: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design... Agent: Morrison & Foerster LLP

20070157141 - Library test circuit and library test method: A library test circuit for verifying functions of a plurality of standard cell library logic cells includes a core module including a plurality of standard cell library logic cells, each logic cell having a predetermined number of input vector combinations, the core module outputting test result signals according to a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070157146 - Method of packing-based macro placement and semiconductor chip using the same: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070157150 - Base project resource management and application synthesis: In one embodiment, a method for constructing an application includes detecting a change to a design of an application, evaluating the design against hardware resources associated with application projects to identify one or more applicable application projects, receiving a user selection of an applicable application project, and constructing the application... Agent: Blakely Sokoloff Taylor & Zafman

20070157154 - Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process: A method of decomposing a target pattern having features to be imaged on a substrate so as to allow said features to be imaged in a multi-exposure process. The method includes the steps of: (a) segmenting a plurality of the features into a plurality of polygons; (b) determining the image... Agent: Mcdermott Will & Emery LLP

20070157130 - Method for multi-cycle clock gating: An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The circuit design updater updates the circuit design with selected multi-cycle gating groups. Each gating group is associated with a single gating... Agent: Stephen C. Kaufman IBM Corporation

20070157132 - Process of automatically translating a high level programming language into a hardware description language: A process of automatically translating a high level programming language into a hardware description language (HDL), which can use a three-stage translation mechanism to generate the HDL codes corresponding to the functions described by the high level programming language. The first stage translates source codes coded by the high level... Agent: Bacon & Thomas, PLLC

20070157139 - Characterization and verification for integrated circuit designs: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics... Agent: Cadence Design Systems, Inc. C/o Bingham Mccutchen LLP

20070157133 - Circuit network analysis using algebraic multigrid approach: This application describes techniques for applying an algebraic multigrid method to analysis of circuit networks with irregular and regular circuit patterns. Adaptive processing may be applied to the grid coarsening and error smoothing operations to increase the processing speed.... Agent: Fish & Richardson, PC

20070157138 - Management of functions for block diagrams: A method is provided that includes pattern-matching portions of a block diagram model as being equivalent, and creation of a common set of instructions in place of the occurrences of the pattern-matched portions to enhance the efficiency of simulation or generated code for the block diagram model, such as by... Agent: Lahive & Cockfield, LLP

20070157137 - Method and apparatus for retrofitting semiconductor chip performance anaylsis tools with full-chip thermal analysis capabilities: A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than... Agent: Patterson & Sheridan L.L.P.

20070157134 - Method for testing a hardware circuit block written in a hardware description language: A method for testing a hardware circuit block written in a hardware description language (HDL) is provided, which can automatically produce a test pattern and an error message. The method includes converting an original class into a wrapper class, wherein the wrapper class, as compared to the original class, additionally... Agent: Bacon & Thomas, PLLC

20070157135 - Parallel multi-rate circuit simulation: A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is... Agent: Martine Penilla & Gencarella, LLP

20070157136 - Selectively reducing the number of cell evaluations in a hardware simulation: An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.... Agent: Klarquist Sparkman, LLP

20070157140 - Method and computer program product for trimming the analysis of physical layout versus schematic design comparison: A method, a computer program product, and an apparatus for performing a trimmed verification analysis comprising selecting layers of interest for a trimmed analysis, eliminating layer definitions for unselected layers to create a trimmed rundeck, and performing a layout versus schematic verification comparison to generate a trimmed error report for... Agent: Lsi Logic Corporation Legal Department - Ip

20070157142 - Method for classifying errors in the layout of a semiconductor circuit: A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of... Agent: Lerner Greenberg Stemer LLP

20070157143 - System for avoiding false path pessimism in estimating net delay for an integrated circuit design: A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function... Agent: Lsi Logic Corporation

20070157144 - Asic design using clock and power grid standard cell: An integrated power and clock grid which is capable of being placed and routed using ASIC software design tools. The integrated grid comprises three types of grid unit cells having power rails and clock lines. The power rails and clock lines comprise different orientations in the different grid unit cells.... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070157145 - Method and end cell library for avoiding substrate noise in an integrated circuit: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input from an integrated circuit design at least a portion of a block for placement and routing on a substrate and an outer boundary of the block, selecting an end cell from a set of... Agent: Lsi Logic Corporation

20070157148 - Circuit layout system for automatically indicating items to wait for modification and method thereof: A circuit layout system for automatically indicating items to wait for modified and method thereof are provided, wherein a set of items to wait for modified recorded on an amendment list is stored on the circuit layout software; the set of items to wait for modified is compared with the... Agent: Birch Stewart Kolasch & Birch

20070157147 - Hardware component graph to hardware description language translation method: An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components... Agent: Bacon & Thomas, PLLC

20070157149 - Design configuration method for an automation system: The invention relates to a projection method for an automation system, in addition to a device which is used to project an automation system. In order to simplify the projection of an automation system, projection data for at least one component (10, 10 12,14) of the automation system is combined... Agent: Henry M Feiereisen, LLC

20070157151 - Engineering change order cell and method for arranging and routing the same: There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070157152 - Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction: A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance... Agent: Lsi Logic Corporation

20070157153 - Yield-limiting design-rules-compliant pattern library generation and layout inspection: A method and system is provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match... Agent: Sandeep Jaggi Lsi Logic Corporation