Data processing: design and analysis of circuit or semiconductor mask inventions 06/07

20070150844 - Behavioral synthesizer system, operation synthesizing method and program: The present invention is intended to realize a behavioral synthesis system which can synthesize behavioral without inline-expanding a callee function even if a pointer is passed to the callee function during a behavioral synthesis of a caller function. The behavioral synthesis system comprises language analyzing means for analyzing the behavioral-level... Agent: Sughrue Mion, PLLC

20070150843 - Method for generating minimal leakage current input vector using heuristics: A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics includes transforming the integrated circuit to a logic representation with PMOS and NMOS parts and P and N devices of the integrated circuit into edges, selecting between PMOS and NMOS logic... Agent: Lin & Associates Intellectual Property

20070150845 - Designing apparatus, designing method, and program thereof: An apparatus and a program detect an error state of FSM coverage measurement, and shorten the checking time. The program for use in the FSM coverage measurement based on the language-described logical circuit and test bench is used to direct a computer to perform: a function of extracting an FSM... Agent: Staas & Halsey LLP

20070150846 - Methods and systems for placement: Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a... Agent: Walstein Bennett Smith Iii

20070150847 - Integrated circuit layout device, method thereof and program thereof: A layout device for an integrated circuit executes calculating a timing value with respect to each wiring path by a analysis based on connection information and delay information of wirings, determining a target value serving as an improvement target of the wiring path, detecting an error wiring path exhibiting the... Agent: Staas & Halsey LLP

20070150848 - Unallocatable space depicting system and method for a component on a printed circuit board: An unallocatable space depicting system is provided for depicting an unallocatable space for a component. The component forms a component shape on a printed circuit board layout. The unallocatable space depicting system includes a detecting module, a comparison module, and an incorporating module. The detecting module is used for detecting... Agent: North America Intellectual Property Corporation

20070150849 - Basic cell design method for reducing the resistance of connection wiring between logic gates: The basic cell design method of the present invention is a method for carrying out: extended pattern formation for extending the patterns of input wiring and output wiring in the longitudinal direction, forming first extended patterns that extend with a prescribed dimensional width in a direction perpendicular to the longitudinal... Agent: Mcginn Intellectual Property Law Group, PLLC

20070150850 - Photomask evaluation method, photomask evaluation apparatus, and semiconductor device manufacturing method: According to an aspect of the invention, there is provided a photomask evaluation method including, acquiring a pattern image of a photomask, generating sidewall angle data on the sidewall angle of a pattern from the pattern image, extracting a pattern outline from the pattern image to generate outline data, and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070143730 - Design method and system for generating behavioral description model: According to one embodiment, there is provided a design system for generating a behavioral description model used in a high-level synthesis system in circuit design. The design system includes an array expanding unit which expands an array for each element when the array is included in a process unit to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070143716 - Circuit layout compaction using reshaping: A critical path minimization technique uses a novel reshaping layout reorganization mechanism. Circuit objects and/or object fragments which belong to a critical path in a reference direction are reshaped using resources of an orthogonal direction. A fragment may decrease its size in the layout in the reference direction and increase... Agent: Freescale Semiconductor, Inc. Law Department

20070143717 - Formally proving the functional equivalence of pipelined designs containing memories: One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next,... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070143718 - Feature failure correlation: Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in... Agent: Banner & Witcoff, Ltd.

20070143719 - Synthesizing current source driver model for analysis of cell characteristics: A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using... Agent: International Business Machines Corporation Dept. 18g

20070143720 - A method , apparatus and computer program product for semiconductor yield estimation: A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.... Agent: Ibm Microelectronics Intellectual Property Law

20070143721 - System and method for plasma induced modification and improvement of critical dimension uniformity: Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved... Agent: Scully, Scott, Murphy & Presser, P.C.

20070143723 - Method of timing verification and layout optimization: In timing verification considering process variations in the fabrication of semiconductor integrated circuits, parasitic element extraction results are obtained with high accuracy by considering variations in interconnect configuration occurring randomly inside LSI to perform timing verification of worst-case or best-case simulation. For example, a plurality of capacitance libraries are prepared... Agent: Mcdermott Will & Emery LLP

20070143722 - System and method of criticality prediction in statistical timing analysis: A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge of interest, defining a cutset that divides the... Agent: Satheesh Karra IBM Corporation

20070143724 - Method and apparatus for diffusion based cell placement migration: A method, apparatus, and computer program product for cell placement in an integrated circuit design that use the principles of diffusion.... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070143725 - Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating... Agent: Lsi Logic Corporation

20070143726 - Circuit design apparatus, circuit design program, and circuit design method: A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines... Agent: Staas & Halsey LLP

20070143728 - Circuit layout methodology: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying... Agent: Scully, Scott, Murphy & Presser, P.C.

20070143727 - Method of designing layout of multipower integrated circuit: In a layout design, there are executed a step 201 of defining a permitted connecting relationship of an interface signal to be transmitted across different power supplies, a step 202 of extracting the interface signal between the different power supplies based on information about each of the power regions and... Agent: Mcdermott Will & Emery LLP

20070143729 - High speed camera bandwidth converter: Image data from a CMOS sensor with 10 bit resolution is reformatted to allow the data to pass through communications equipment that is designed to transport data with 8 bit resolution. The incoming image data has 1280 columns and 1024 rows with 10 bit resolution. The communication equipment can transport... Agent: Deputy Laboratory Counsel For Intellectual Property

20070143731 - Method and program for supporting register-transfer-level design of semiconductor integrated circuit: A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description,... Agent: John S. Pratt, Esq Kilpatrick Stockton, LLP

20070143733 - Method of compensating photomask data for the effects of etch and lithography processes: A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target... Agent: Martin Novack

20070143732 - Pixelated masks for high resolution photolithography: Some embodiments of the present invention include apparatuses and methods relating to pixelated masks for high resolution photolithography.... Agent: Intel Corporation C/o Intellevate, LLC

20070143734 - Method and system for improving aerial image simulation speeds: A method and system for improving aerial image simulation speeds. The method includes receiving a mask; generating a matrix of node values based on the mask, wherein each node value corresponds to a node of a plurality of nodes in a lattice; performing a one-dimensional (1-D) approximation of a plurality... Agent: Lsi Logic Corporation M/s D106

20070136698 - Method, system and apparatus for a parser for use in the processing of structured documents: Embodiments of systems, methods and apparatuses for a parser for generating one or more data structures representative of a structured document are disclosed. More specifically, embodiments of a parser may comprise hardware circuitry operable to receive a structured document, begin parsing the structured document as it is being received and... Agent: Blakely Sokoloff Taylor & Zafman

20070136699 - Dependency matrices and methods of using the same for testing or analyzing an integrated circuit: In a first aspect, a method of testing or analyzing an integrated circuit (IC) is provided. The method includes the steps of (1) generating information about a dependency between components of the IC based on a netlist describing the IC; and (2) reducing the generated information by at least one... Agent: Leslie J. Payne IBM Corporation, Dept. 917

20070136700 - Method and apparatus for structured asic test point insertion: Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC... Agent: Nec Laboratories America, Inc.

20070136701 - Extending incremental verification of circuit design to encompass verification restraints: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint... Agent: Ibm Corp. (ave) C/o Law Office Of Anthony England

20070136702 - Semiconductor device layout inspection method: An object of the invention is to discover at the chip level a portion of a high density of contact holes in wires of a large area that becomes a portion where wire defects will occur. In order to achieve this, the area ratio of the total area of wires... Agent: Stevens, Davis, Miller & Mosher, LLP

20070136708 - Clock skew compensation: A clock distribution approach includes distributing a clock signal from a clock tree to a first set of circuit elements characterized by a first circuit characteristic; and distributing a clock signal from a sub-tree of the clock tree to a second set of circuit elements characterized by a second circuit... Agent: Fish & Richardson PC

20070136706 - Exploration of the method of the interconnect effort in nano-technologies: Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert... Agent: Qualcomm Incorporated

20070136704 - Method and apparatus for generating memory models and timing database: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are... Agent: Lsi Logic Corporation Timothy R. Croll

20070136703 - Method and apparatus for performing temporal checking: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070136707 - Method and system for distributing clock signals on non-manhattan semiconductor integrated circuits: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that... Agent: Stattler, Johansen, And Adeli LLP

20070136705 - Timing analysis method and device: A timing analysis device for preventing the amount of data and the number of analysis operations from increasing in a statistical analysis, while improving the timing convergence in a path included in a net under relatively strict timing conditions. The timing analysis device performs a static timing analysis to extract... Agent: Staas & Halsey LLP

20070136709 - Floorplanning a hierarchical physical design to improve placement and routing: Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally,... Agent: Fenwick & West LLP

20070136710 - Layout design apparatus, layout design method, and computer product: A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame... Agent: Staas & Halsey LLP

20070136711 - Layout design apparatus, layout design method, and computer product: A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame... Agent: Staas & Halsey LLP

20070136712 - Semiconductor design support apparatus: The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of symmetry orthogonal to the first axis. The recognition pattern... Agent: Foley And Lardner LLP Suite 500

20070136713 - Method and apparatus for routing: Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e., the shape of route-segment ends) on a particular... Agent: Stattler, Johansen, And Adeli LLP

20070136714 - A method for ic wiring yield optimization, including wire widening during and after routing: Embodiments herein present a method, service, computer program product, etc. or performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070136715 - Semiconductor device and designing support method for the same: In a support method of designing a semiconductor device, a plurality of wiring lines are arranged in parallel in a wiring line layer to transfer a same signal. A wiring line inhibition area is set in the wiring line layer to cover a space between the plurality of wiring lines... Agent: Young & Thompson

20070136716 - Method for time-evolving rectilinear contours representing photo masks: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati

20070130548 - Point and click expression builder: In one embodiment, a method for constructing an application includes presenting to a user a list of possible elements for a logic expression. The possible elements may include one or more names of variables. The method further includes receiving a user selection of one or more elements from the list... Agent: Blakely Sokoloff Taylor & Zafman

20070130549 - Clock-gating through data independent logic: Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent... Agent: Stephen C. Kaufman IBM Corporation

20070130551 - Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line... Agent: Schmeiser, Olsen & Watts

20070130550 - Semiconductor integrated circuit and design method thereof: A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of logic blocks each of which is constituted by a first logic circuit and a second logic circuit. Such semiconductor integrated circuit is designed in... Agent: Fish & Richardson P.C.

20070130552 - Layout method and computer program product: A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the... Agent: Staas & Halsey LLP

20070130553 - Analog layout module generator and method: In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One... Agent: The Webb Law Firm, P.C.

20070130554 - Integrated circuit with dual electrical attachment pad configuration: According to the present invention, an integrated circuit has a terminal pad configuration such that the integrated circuit may be wire bonded or flip chip bonded. The terminal pad configuration uses staggered rows of pads to allow the different bonding.... Agent: Siemens Corporation Intellectual Property Department

20070130555 - Multilayer printed circuit board for high-speed differential signal, communication apparatus, and data storage apparatus: In the case where high speed differential signals are transmitted in differential transmission lines through via holes with open-stubs, signal waveforms are distorted due to impedance mismatch in the open-stubs of the via holes, thus causing jitter, which has become an issue of high speed signals. For differential transmission lines... Agent: Stanley P. Fisher Reed Smith LLP

20070130556 - Method and apparatus for generating technology independent delays: A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication process. The method initiates with describing an IC design through a hardware description language (HDL). The method includes identifying logic signal... Agent: Epson Research And Development Inc Intellectual Property Dept

20070130557 - Approximating wafer intensity change to provide fast mask defect scoring: To provide fast mask defect scoring, approximated wafer simulations (e.g. using one convolution) are performed on the defect inspection image and its corresponding reference inspection image. Using the approximated defect wafer image and the approximated reference wafer image generated by these approximated wafer simulations, a defect maximum intensity difference (MID)... Agent: Bever, Hoffman & Harms, LLP

20070130560 - Method of determining photo mask, method of manufacturing semiconductor device, and computer program product: A method of determining a photo mask, includes specifying a mask pattern for a photo mask for a first exposure apparatus, specifying a plurality of exposure conditions allowed to be set for a second exposure apparatus, predicting a projection image of the mask pattern to be projected on a substrate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070130558 - Methods and systems for pattern generation based on multiple forms of design data: In a pattern generation method, properties of designs are extracted in a mask data preparation system, and the properties are propagated to a lithography write system. A pattern is generated based on fractured design data and the extracted properties. By preserving the design intent to the lithography write system, the... Agent: Harness, Dickey & Pierce, P.L.C

20070130559 - Optical proximity correction on hardware or software platforms with graphical processing units: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute... Agent: Aka Chan LLP