Data processing: design and analysis of circuit or semiconductor mask inventions 05/07

20070124706 - Method and system for representing analog connectivity in hardware description language designs: System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or... Agent: Morrison & Foerster LLP

20070124708 - Contrast based resolution enhancement for photolithographic processing: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070124707 - Method and apparatus for facilitating variation-aware parasitic extraction: One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070124712 - Auxiliary method for circuit design: For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification... Agent: Kirton And Mcconkie

20070124713 - Logical cad navigation for device characteristics evaluation system: A navigation system for easily determining defective positions is provided. In the case of CAD navigation to defective positions, logical information for indicating defective positions is created in a CAD format, instead of CAD data of physical information indicating circuit design. Specifically, by attaching marks such as rectangles, characters, or... Agent: Mcdermott Will & Emery LLP

20070124709 - Method and system for design rule checking for an sip device: A method for checking design rules in an SiP (system in a package) design environment is provided. The method uses a commercial computer aided design tool to design and layout out an SiP, that is, to create a design database for the SiP. In the database, characteristics may be assigned... Agent: William J. Kolegraff

20070124711 - Multithreaded reachability: In one embodiment, a method for multithreaded reachability analysis includes partitioning a state space of a circuit under analysis into a plurality of partitions and assigning each partition to a thread to carry out a reachability analysis on the partition assigned to the thread. The threads carry out the reachability... Agent: Baker Botts L.L.P.

20070124710 - Timing analyzer apparatus and timing analysis program recording medium: By multiplying a square root of a sum of squares of a standard deviation of cells constituting a target circuit by a weight, or by calculating a square root of a sum of squares of a weighted standard deviation of the cells, the standard deviation of delay of the target... Agent: Staas & Halsey LLP

20070124714 - Method for designing semiconductor integrated circuit layout: According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none... Agent: Buchanan, Ingersoll & Rooney PC

20070124715 - Semiconductor integrated circuit and design method thereof: In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is... Agent: Mcdermott Will & Emery LLP

20070124717 - Method and program product for protecting information in eda tool design views: Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net names with unrelated unique identifiers prior to transferring the design views as part of a simulation model of a circuit design,... Agent: Dillon & Yudell LLP

20070124716 - Method for generalizing design attributes in a design capture environment: A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a... Agent: Lsi Logic Corporation

20070124718 - Mask manufacturing system, mask data creating method and manufacturing method of semiconductor device: A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070124719 - Method of forming a mask pattern for a semiconductor device: A method of forming a mask pattern from a design pattern. A method may effectively compensate for pattern distortion resulting from an optical proximity effect (OPE). A method may obtain a precise line width. A method includes a first mask design processing and a second mask design processing.... Agent: Sherr & Nourse, PLLC

20070124720 - Program for causing a computer to execute a method of generating mesh data and apparatus for generating mesh data: A method of generating mesh data by orthogonally dividing a target object into a mesh of elements by a plurality of grid lines orthogonally crossing each other includes the steps of (a) detecting vertexes of the target object; and (b) dividing the target object orthogonally by the grid lines passing... Agent: Staas & Halsey LLP

20070118822 - Confirmation system for authenticity of article and confirmation method: An article confirmation method has reading irreproducible fine characteristics from a genuine article, reading irreproducible fine characteristics from an article to be confirmed, comparing the irreproducible fine characteristics between the genuine article and the article to be confirmed, and determining authenticity of the article to be confirmed based on a... Agent: Oliff & Berridge, PLC

20070118823 - Method and system for automatically checking traces in segments: A method and system for automatically checking traces of a differential pair in segments in a printed circuit board (PCB) layout is proposed. A setting module sets a tolerance of length difference. A checking module segments the differential pair into a plurality of segments at places where the slopes thereof... Agent: Edwards & Angell, LLP

20070118824 - Methods, systems, and computer program products for improving yield in integrated circuit device fabrication and related devices: A method of improving yield in integrated circuit device fabrication includes calculating a fault rate for a design rule based on a plurality failure rates for a corresponding plurality of Design Of Experiment (DOE) rule values and based on numbers of features in a layout of interest corresponding to ones... Agent: Myers Bigel Sibley & Sajovec

20070118826 - Opc conflict identification and edge priority system: An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070118825 - Usage of a buildcode to specify layout characteristics: A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells). Buildcode representations are then assigned for each of a plurality of circuit components and features thereof to realize customization of at least... Agent: Akerman Senterfitt

20070118827 - Method and apparatus for integrated circuit fault isolation and failure analysis using linked tools cockpit: A microelectronic circuit debugging environment links development tools by correlating a selected element in a first tool with elements in the datasets of other tools. A signaling module instructs the other tools to display the correlated elements.... Agent: Blakely Sokoloff Taylor & Zafman

20070118828 - Generation of metal holes by via mutation: A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs... Agent: Brinks Hofer Gilson & Lione

20070118829 - Arc routing system and method: An arc routing system and method are disclosed, which are integrated to a PCB (printed circuit board) routing system for assisting the PCB routing system to route wires in an area of a printed circuit board with high component density. First, three neighboring points in a routing direction in the... Agent: Edwards & Angell, LLP

20070113208 - Memory compiler redundancy: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on... Agent: Berkeley Law & Technology Group, LLP

20070113209 - Chip design verifying and chip testing apparatus and method: A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the... Agent: Cantor Colburn, LLP

20070113210 - Method and apparatus for supporting verification, and computer product: In gates, a gate length is same as that of an isolated Poly on a layout, however, is different from that of the isolated Poly on an actual silicon wafer. When the distance between the gates that is spacing between the gate becomes larger to some degree, the proximity effect... Agent: Staas & Halsey LLP

20070113211 - Efficient statistical timing analysis of circuits: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each... Agent: Dewitt Ross & Stevens S.c. Excelsior Financial Centre

20070113213 - Flip flop function device, semiconductor integrated-circuit, and method and apparatus for designing semiconductor integrated circuit: A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library... Agent: Freescale Semiconductor, Inc. Law Department

20070113214 - Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070113212 - Method and apparatus for mapping design memories to integrated circuit layout: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are... Agent: Timothy R. Croll Lsi Logic Corporation

20070113215 - System and method for implementing package level ip preverification for system on chip devices: A method for implementing package-level intellectual property (PLIP) preverification for system on chip (SOC) devices includes providing at least one externally connected intellectual property (IP) core with an SOC. A package generic unit is provided with the IP core and is configured for providing external interface functions with respect to... Agent: Agilent Technologies Inc.

20070113216 - Photolithographic mask correction: An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with... Agent: Patentesque Law Group, LLP

20070106962 - Image processing method, recorded matter, storage medium, image processing apparatus, image forming method, image forming apparatus, image forming system, and ink: An image processing method of processing image data includes a color space conversion step of converting an input color signal of image data into an output color signal having cyan (C), magenta (M), and yellow (Y) values; a black generation/under color removal step of converting the CMY values into cyan... Agent: Cooper & Dunham, LLP

20070106961 - System and method for reformatting a motherboard design file: A method for reformatting a motherboard design file includes the steps of: converting the motherboard design file from a first format to a second format, and generating a converted temp file based on the motherboard design file; selecting information classes of the converted temp file; parsing contents from the converted... Agent: North America Intellectual Property Corporation

20070106960 - System and method for the development and distribution of a vhdl intellectual property core: Provided is a system and method for the development and distribution of a VHDL Intellectual Property (“IP”) Core. In particular, the system includes a module for regulating source control of core design files, a module for extracting or adding information to a file, and for controlling file release consistent with... Agent: Lathrop & Gage Lc

20070106963 - Method and system for predicate-based compositional minimization in a verification environment: A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output functions and one or more next-state functions... Agent: Dillon & Yudell LLP

20070106964 - Optimized microchip and related methods: Various embodiments of an optimized microchip and methods of fabricating and operating the same are provided. One microchip embodiment, among others, comprises a repeater-type transistor located in a first path corresponding to a first path type, the repeater-type transistor having a parameter at a first design value, and a logic-type... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070106965 - Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed,... Agent: Mcdermott Will & Emery LLP

20070106967 - Layout analysis method and apparatus for semiconductor integrated circuit: A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of... Agent: Staas & Halsey LLP

20070106966 - Method and apparatus for extracting characteristic of semiconductor integrated circuit: A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.... Agent: Staas & Halsey LLP

20070106970 - Method and apparatus for supporting integrated circuit design: An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs, based on the clock tree, a plurality of groups each of which includes a part of elements of same... Agent: Staas & Halsey LLP

20070106969 - Method of automatically routing nets according to parasitic constraint rules: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.... Agent: Aka Chan LLP

20070106968 - Opc trimming for performance: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form... Agent: Law Office Of Delio & Peterson, LLC.

20070106971 - Apparatus for a routing system: The invention details methods and apparatus for a routing system or router that includes a model. The model can be in many different forms including but not limited to: resolution enhancement technologies such as OPC; lithography model including but not limited to aerial image; pattern-dependent functions; functions for timing/signal integrity/power;... Agent: Birch Stewart Kolasch & Birch

20070106973 - Diffused aerial image model semiconductor device fabrication: A lithography method has a simulation method for mathematically approximating a photoresist film pattern with a Diffused Aerial Image Model (“DAIM”) for semiconductor device fabrication. The DAIM is applied with at least two acids having heterogeneous diffusion characteristics.... Agent: Heller Ehrman LLP

20070106972 - Method for fabricating integrated circuit features: The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process.... Agent: International Business Machines Corporation Dept. 18g

20070101301 - Simulation appartus, simulation method, and semiconductor device: An apparatus for simulating a current-voltage characteristic of a device includes an atomic structure creating unit that creates an atomic structure model of the device, an electronic structure calculating unit that calculates an electronic structure in the atomic structure model, a first IV characteristic calculating unit that calculates the current-voltage... Agent: Harness, Dickey & Pierce, P.L.C

20070101302 - Mixed signal circuit simulator: The waveform created by a circuit simulator is selected. The input data 11 inputted by an inputting means are obtained for a point on the waveform or the waveform. The selected waveform and the input data 11 are analyzed by a waveform analyzing means 12 to create circuit parameter updating... Agent: Mcdermott Will & Emery LLP

20070101303 - Method and apparatus for integrated circuit layout optimization: A method and apparatus for integrated circuit layout optimization are provided. In the conventional art, the major challenges in building integrated circuits (IC) at sub-wavelength geometries include i) to ensure the design intent is faithfully transferred onto silicon; ii) to ensure the design is manufacturable, or with acceptable yield subject... Agent: Birch Stewart Kolasch & Birch

20070101304 - Fast/slow state machine latch: A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed... Agent: Hoffman, Warnick & D'alessandro LLC

20070101305 - Methods and systems for implementing dummy fill for integrated circuits: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the... Agent: Cadence Design Systems, Inc. C/o Bingham Mccutchen LLP

20070101307 - Design supporting system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, and computer readable medium for supporting design of semiconductor integrated circuit: A design supporting system of a semiconductor integrated circuit includes a unit that converts a defective circuit pattern into computer detectable information when a layout of the chip is determined, and corrects the defective circuit pattern of layout of the chip based on the computer detectable information.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070101306 - Methods, systems, and media to improve manufacturability of semiconductor devices: Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070101309 - Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or... Agent: Hewlett Packard Company

20070101308 - Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junctions: Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a nanowire crossbar comprises two or more layers of approximately parallel nanowires, and a number of configurable, tunneling resistor junctions that... Agent: Hewlett Packard Company

20070101310 - Model of sensitivity of a simulated layout to a change in original layout, and use of model in proximity correction: A memory is encoded with a model of sensitivity of a distorted layout generated by simulation of a wafer fabrication process, with respect to a change in an original layout that is input to the simulation. The sensitivity model comprises an expression of convolution of the original layout with spatial... Agent: Silcon Valley Patent Group LLP