Data processing: design and analysis of circuit or semiconductor mask inventions 04/07

20070094621 - Method and system for converting netlist of integrated circuit between libraries: The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows.... Agent: Lsi Logic Corporation

20070094622 - Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages: Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the... Agent: Myers Bigel Sibley & Sajovec

20070094623 - Timing, noise, and power analysis of integrated circuits: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation... Agent: Courtney Staniford & Gregory LLP

20070094625 - Net/wiring selection method, net selection method, wiring selection method, and delay improvement method: The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to... Agent: Staas & Halsey LLP

20070094624 - Semiconductor device and method for providing a reduced surface area electrode: An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach... Agent: Fitch Even Tabin And Flannery

20070094626 - Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through... Agent: Priest & Goldstein, PLLC

20070094627 - Clock forming method for semiconductor integrated circuit and program product for the method: Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of... Agent: Buchanan, Ingersoll & Rooney PC

20070094629 - Methods and apparatus for making placement sensitive logic modifications: Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned... Agent: Priest & Goldstein, PLLC

20070094628 - Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods: A method of automatically generating planar double gate transistor shapes can include taking an integrated circuit layout design that includes single gate transistors, locating the gate shapes and active shapes for the transistors, generating top gate shapes, planar double gate active shapes, bottom gate shapes, active cavity shapes, source/drain cavity... Agent: Larson Newman Abel Polansky & White, LLP

20070094631 - Method and apparatus for controlling congestion during integrated circuit design resynthesis: The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in... Agent: Tim R. Croll Lsi Logic Corporation

20070094630 - Power grid design in an integrated circuit: An aspect of the present invention computationally determines the metal density of each metal layer supporting a power grid structure providing power to the elements of an integrated circuits. The metal densities are computed such that the power grid would support aggregate power and IR drop constraints. The metal densities... Agent: Texas Instruments Incorporated

20070094632 - Method in an integrated circuit (ic) manufacturing process for identifying and redirecting ics mis-processed during their manufacture: A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on... Agent: Trask Britt, P.C./ Micron Technology

20070094633 - Method and system for mapping netlist of integrated circuit to design: The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the... Agent: Lsi Logic Corporation

20070094634 - Method for checking printability of a lithography target: A technique for determining, without having to perform optical proximity correction, when the result of optical proximity correction will fail to meet the design requirements for printability. A disclosed embodiment has application to a process for producing a photomask for use in the printing of a pattern on a wafer... Agent: Martin Novack

20070094635 - Optical proximity correction system and methods thereof: An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of... Agent: Harness, Dickey & Pierce, P.L.C

20070089074 - Method and apparatus for automated circuit design: Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the subsequent implementation (e.g., placement and routing) of the circuit. In one aspect of the present invention, a method to design a circuit... Agent: Blakely Sokoloff Taylor & Zafman

20070089073 - Shape-based geometry engine to perform smoothing and other layout beautification operations: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously... Agent: Bever Hoffman & Harms, LLP

20070089072 - Signal transmission structure: A signal transmission structure includes an aggressor line and a victim line parallel with the aggressor line, and a number of delay portions formed in the victim line. Noise due to crosstalk passing through the delay portion is delayed an amount of time equal to or greater than a rise... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070089075 - Method for optimizing integrated circuit device design and service: Improved analysis and refinement of integrated circuit device design and other programs is facilitated by methods in reach-ability analysis is performed using hints which define a particular path through a program. To ensure that a reasonable number of states are reached during reach-ability analysis a order to apply the hints... Agent: International Business Machines Corporation

20070089076 - Application of consistent cycle context for related setup and hold tests for static timing analysis: A technique for performing static timing analysis of an integrated circuit design provides a relationship between reference events of a setup test and a hold test for a particular signal path of an integrated circuit design. The relationship between the reference events of the setup and hold tests is used... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20070089077 - System and method for integrated circuit timing analysis: An integrated circuit timing analysis system includes: a first storage section for storing a layout of an integrated circuit including a plurality of transistors; and a processing section for processing the layout stored in the first storage section. The processing section includes a layout dividing section for dividing the layout... Agent: Mcdermott Will & Emery LLP

20070089078 - Variable sigma adjust methodology for static timing: The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070089079 - Method and tool for creating a layout for an electronic circuit: The present invention relates to a method, a tool, and a computer program product for creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by... Agent: International Business Machines Corporation

20070089080 - Automatic layout method and automatic layout device: An automatic layout method for performing an automatic layout of components on a diagram, the automatic layout method includes: generating a layout engine control object based on an operation of an application program; selecting at least one layout engine object from a plurality of layout engine objects for calculating coordinates... Agent: Edwards & Angell, LLP

20070089081 - Net/wiring selection method, net selection method, wiring selection method, and delay improvement method: The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to... Agent: Staas & Halsey LLP

20070089082 - Freeway routing system for a gate array: A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable... Agent: Sierra Patent Group, Ltd.

20070089083 - Method and design system for semiconductor integrated circuit: A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of automatic placement, a standard cell can... Agent: Foley And Lardner LLP Suite 500

20070083830 - Various methods and apparatuses for an executable parameterized timing model: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area and power constraints in an electronic design system. The IP Generator receives a user-supplied file having data describing a configuration of an intellectual property (IP) design, the data includes one or more configuration parameters. The... Agent: Blakely Sokoloff Taylor & Zafman

20070083831 - Various methods and apparatuses for estimating characteristics of an electronic system's design: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied... Agent: Blakely Sokoloff Taylor & Zafman

20070083832 - Method for performing post-synthesis circuit optimization: Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by... Agent: Dillon & Yudell LLP

20070083834 - Method for sram bitmap verification: A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit “defect” is intentionally created in the physical layout. Then, the... Agent: Lsi Logic Corporation

20070083833 - Method to implement metal fill during integrated circuit design and layout: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a... Agent: Garlick Harrison & Markison

20070083835 - Method for the computer-aided ascertainment of a clock tree structure, and integrated semiconductor circuit: A method for the computer-aided ascertainment of a clock tree structure which couples a clock generation unit to a multiplicity of switching elements ascertains first switching elements from the multiplicity of switching elements, the first switching elements infringing a prescribed, first time-based switching criterion. In further method steps, the first... Agent: Baker Botts L.L.P. Patent Department

20070083836 - Method of wiring data transmission lines and printed circuit board assembly wired using the method: A method of wiring data transmission lines between a CPU including CPU data pins identified by a set of pin numbers and a DRAM including DRAM data pins also identified by the set of pin numbers, the method including connecting the CPU data pins to the DRAM data pins with... Agent: Stein, Mcewen & Bui, LLP

20070083837 - Method and placement tool for designing the layout of an electronic circuit: According to the present invention a method for the placement of electronic circuit components is provided that supports design modifications by realizing and maintaining relations between the layouts of the components (i1 to i6). These relations are based on relations between the geometrical shapes represented by the layouts for the... Agent: International Business Machines Corporation

20070083838 - Generating a base curve database to reduce storage cost: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in... Agent: Bever, Hoffman & Harms, LLP

20070083839 - On-the-fly rtl instructor for advanced dft and design closure: A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in... Agent: Lsi Logic Corporation

20070083840 - Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of asic and programmable logic device: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal... Agent: Staas & Halsey LLP

20070083841 - Assessing bypass capacitor locations in printed circuit board design: Systems and methods for assessing bypass capacitor locations in printed circuit board design which are utilized as return current paths are disclosed. In one embodiment a method of assessing bypass capacitor locations in printed circuit board design comprises selecting a first via on a layer of a printed circuit board;... Agent: Hewlett Packard Company

20070083842 - Standard cell library, method of designing semiconductor integrated circuit, semiconductor integrated circuit pattern, and semiconductor integrated circuit: An exemplary cell library includes a first plurality of types of standard cells. Each of the first plurality of types of standard cells includes threshold voltage adjusting patterns. The upper and the lower boundaries of the threshold voltage adjusting patterns contact the upper and lower boundaries of the cell frame... Agent: Oliff & Berridge, PLC

20070083845 - Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of asic and programmable logic device: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal... Agent: Staas & Halsey LLP

20070083844 - Logic circuit design support apparatus, and logic circuit design support method employing this apparatus: A circuit structure analysis unit performs structure analysis for logic circuit information, obtained from an HDL description, and acquires analysis results for function parts, such as a register, an operation unit and a multiplexer. A synthesis instruction generation unit compares the analysis results with a synthesis instruction correlation rule, and... Agent: Mcdermott Will & Emery LLP

20070083843 - Method, system and program product for providing a configuration specification language supporting error checking dials: A digital system includes one or more design entities containing a functional portion of the digital system. Within a configuration database, one or more configuration entities are instantiated. The configuration entities including an Error checking Dial (EDial) having a plurality of input latches within the digital design and a plurality... Agent: Dillon & Yudell LLP

20070083846 - Optimized modules' proximity correction: A method comprising dissecting a photomask pattern layout into a plurality of segments, each segment having at least one evaluation point, applying a rule-based MPC to the photomask pattern layout and generating a rule-based MPC result, and applying a model-based MPC to the plurality of segments of the photomask pattern... Agent: Haynes And Boone, LLP

20070083847 - Designer's intent tolerance bands for proximity correction and checking: A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions,... Agent: International Business Machines Corporation Dept. 18g

20070079261 - Integrated circuit device and method for forming the same: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines... Agent: Jack Q. Lever, Jr. Mcdermott, Will & Emery

20070079262 - Clock tree layout method for semiconductor integrated circuit: By executing the steps of sequentially retrieving buffers on a clock tree from a clock source to input pins of the cells other than the buffers and recognizing the buffer retrieved, organizing a group of the buffers recognized on the clock tree into an instance as a hierarchical block and... Agent: Mcdermott Will & Emery LLP

20070079263 - Design method of semiconductor integrated circuit device, a program, and the support method of measurement evaluation: Sample evaluation is effectively conducted within a short period of time using a general purpose software by changing programs, data files and register libraries in accordance with measuring specifications of semiconductor integrated circuit devices. The automatic measuring program used for sample evaluation includes a basic standard frame and can realize... Agent: Miles & Stockbridge PC

20070079265 - Accurate noise modeling in digital designs: A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters... Agent: Texas Instruments Incorporated

20070079270 - Circuit design method, circuit design system, and program for causing computer to perform circuit design: In a circuit design method, a computer verifies an occurrence of a noise error, specifies a noise allowable value with respect to a cell at which it is determined that the noise error occurs, and determines a parameter value used in a process step. The parameter value satisfies the noise... Agent: Arent Fox PLLC

20070079266 - Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database: A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving... Agent: Lsi Logic Corporation

20070079269 - Method for performing design rule check of integrated circuit: The present invention provides a method for performing design rule check (DRC) of an integrated circuit. A design layout of the integrated circuit is provided. The integrated circuit includes a complex circuit. A DRC tool is used to compare a portion of the design layout with a reference layout containing... Agent: Lsi Logic Corporation

20070079268 - Mixed mode verifier: A method and system for formally verifying designs having elements from more than a single design domain is described. For example, an example system allows formal verification of a design containing mixed analog and digital design.... Agent: Hickman Palermo Truong & Becker, LLP

20070079267 - Multi-format consistency checking tool: A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule... Agent: Hickman Palermo Truong & Becker, LLP

20070079264 - Reducing time to design integrated circuits including performing electro-migration check: The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path... Agent: Texas Instruments Incorporated

20070079272 - Design support system and design method for circuit board, and noise analysis program: A design support system for circuit board includes: a noise source extracting unit for extracting a source of unwanted radiation noise which is generated from a circuit board mounted on an electronic equipment; a noise characteristics input unit for inputting noise characteristics of the unwanted radiation noise which is emitted... Agent: Wenderoth, Lind & Ponack L.L.P.

20070079271 - Design tool, design method, and program for semiconductor device: A design tool, which is capable of designing an IC in which no malfunctions occur during a normal operation and a test, by limiting the amount of noise produced by the operation of an SRAM during the normal operation of the IC itself and during the test of the IC,... Agent: Arent Fox PLLC

20070079273 - Method and computer program for incremental placement and routing with nested shells: A method of placing and routing an integrated circuit design includes steps of (a) generating an initial placement and routing for at least a portion of an integrated circuit design; (b) analyzing the initial placement and routing of the integrated circuit design to find a critical location; (c) partitioning the... Agent: Lsi Logic Corporation

20070079274 - Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints: A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function... Agent: Lsi Logic Corporation

20070079275 - Computer-aided thermal relief pad design system and method: A computer-aided thermal relief pad design system includes a depicting unit, a memory unit and a calculating unit. The depicting unit is used for depicting an elongated oval pattern of a thermal relief pad. The elongated oval pattern includes two perpendicular axes that intersect at a center point, and a... Agent: North America Intellectual Property Corporation

20070079276 - Multilayered circuit board design support method, program, and apparatus, and multilayered circuit board: A multilayered board data input unit inputs design data of a multilayered circuit board provided with through holes penetrating and mutually connecting solid-layer conductors disposed in a multilayer manner. A limitation rule setting unit sets a limitation rule for limiting the number of solid-layer conductors to be connected to the... Agent: Staas & Halsey LLP

20070079277 - Method and system for analyzing the quality of an opc mask: The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target... Agent: Lsi Logic Corporation

20070079278 - Method and apparatus for reducing opc model errors: A method is provided of accessing model error in an optical proximity correction (OPC) model. The method begins by obtaining a preliminary mask using an OPC model, creating an etched wafer from the preliminary mask using lithography, and measuring a specified critical dimension (CD) on the wafer and a second... Agent: Mayer & Williams PC