Data processing: design and analysis of circuit or semiconductor mask inventions 03/07

20070074134 - Semiconductor integrated circuit for reducing leak current through mos transistors: A semiconductor device is composed of: a power control region within which function cells are arranged; a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer; a virtual power supply line arranged in said power control region in a direction perpendicular to... Agent: Mcginn Intellectual Property Law Group, PLLC

20070074135 - Circuit design verification using checkpointing: A design verification method, comprising providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, M checkpointed splits, and N non-checkpointed splits; and executing the stimulus tree diagram, wherein said executing the stimulus tree diagram comprises, for i=1, .... Agent: Schmeiser, Olsen & Watts

20070074137 - Database and method of verifying function of lsi using the same: Provided is a method of verifying the function of the LSI including: a first signal database generating step of registering a first signal data set for associating a first verification target signal of which the operation is defined as the specification of the LSI with a first depended signal group... Agent: Mcdermott Will & Emery LLP

20070074136 - Using constraints in design verification: A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which... Agent: Ibm Corp. (ave) C/o Law Office Of Anthony England

20070074138 - Delay analysis device, delay analysis method, and computer product: A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based... Agent: Staas & Halsey LLP

20070074139 - Method and apparatus for circuit design and retiming: Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the... Agent: Blakely Sokoloff Taylor & Zafman

20070074140 - Systems and methods for writing data with a fifo interface: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal... Agent: William W. Enders O'keefe, Egan & Peterman

20070074141 - Simulation apparatus and simulation method: According to an aspect of the invention, a simulation apparatus includes: a computer configured to execute a program which is formed as an operating description having no temporal restriction; and a programmable circuit configured to be on which a designing object circuit configured to perform a cycle operation is mounted.... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070074143 - Dense opc: A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a layout database on a substantially uniform grid. Contour curves are created from the estimated process conditions. The contour curves are then compared... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070074142 - Integrated circuit layout methods: The present invention provides methods of post-layout processing, such as OPC post-processing, through partitioning of integrated circuit data files. Partitioning methods of the present invention comprise forming partitioned identical cell groups. Each partitioned identical cell group comprises identical cells such that the cells within a partitioned group include identical cell... Agent: Patent Counsel Applied Materials, Inc.

20070074145 - Mask pattern design method and manufacturing method of semiconductor device: To a cell library pattern which makes the basic constitution of a semiconductor circuit pattern, OPC processing is performed beforehand, and a semiconductor chip is produced using this cell library pattern. Since it is influenced by the pattern of the cell arranged to the circumference and the pattern arranged around... Agent: Stanley P. Fisher Reed Smith LLP

20070074144 - Method and system for selective optical pattern compensation: A method and system for making a photographic mask. The method includes determining a first contact area, processing information associated with the first contact area, and determining whether a first optical compensation should be applied to the first contact area based on at least information associated with the first contact... Agent: Townsend And Townsend And Crew, LLP

20070074146 - Method for designing mask pattern and method for manufacturing semiconductor device: A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged... Agent: Stanley P. Fisher Reed Smith LLP

20070067746 - Method and system for performing heuristic constraint simplification: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state... Agent: Dillon & Yudell LLP

20070067747 - Substrate noise tool: System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size,... Agent: Nields & Lemack

20070067748 - Method and system for enhancing circuit design process: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after... Agent: James R. Nock IBM Corporation

20070067749 - Method and system for embedding wire model objects in a circuit schematic design: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in... Agent: James R. Nock IBM Corporation

20070067751 - Computer program product, method, and system for hardware model conversion: A hardware model conversion system includes a logic synthesis tool and a hardware model conversion program. The logic synthesis tool logically synthesizes an HDL-described circuit and then outputs intermediate data. One assign statement described in the intermediate data is associated with one assign cell. The hardware model conversion program creates... Agent: Stanley P. Fisher Reed Smith LLP

20070067750 - Method and system for modeling wiring routing in a circuit design: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring... Agent: James R. Nock IBM Corporation

20070067752 - Method for verifying optical proximity correction using layer versus layer comparison: A method for verifying optical proximity correction (OPC) using a layer-versus-layer (LVL) comparison. The method includes performing optical proximity correction of an original design of a semiconductor device to prepare a revised design of the semiconductor device; comparing the revised design and the original design with each other; dividing deviation... Agent: Townsend And Townsend And Crew, LLP

20070061763 - Method of generating development environment for developing system lsi and medium which stores program therefor: A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070061764 - Keyword-based connectivity verification: Keyword-based verification of proper connectivity of a circuit design including a plurality of cells is disclosed. In one embodiment, a method includes assigning a keyword to each relevant pin of the circuit design, the keyword indicates a verification rule for a domain starting at the relevant pin; tracing the domain... Agent: Hoffman, Warnick & D'alessandro LLC

20070061765 - Method and system for case-splitting on nodes in a symbolic simulation framework: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the... Agent: Dillon & Yudell LLP

20070061766 - Method and system for performing target enlargement in the presence of constraints: A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers... Agent: Dillon & Yudell LLP

20070061767 - Method and system for performing minimization of input count during structural netlist overapproximation: A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of... Agent: Dillon & Yudell LLP

20070061768 - Method of implementing polishing uniformity and modifying layout data: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional... Agent: Freescale Semiconductor, Inc. Law Department

20070061769 - Layout method and layout program for semiconductor integrated circuit device: A plurality of cells are disposed in a chip region and wires are disposed between the cells in order to connect the cells over a plurality of layout steps. The layout method comprises (1) a placement restricted region placement step for disposing, in the chip region, a placement restricted region... Agent: Arent Fox PLLC

20070061770 - Semiconductor integrated circuit and layout designing method of the same: A semiconductor integrated circuit of the present invention comprises a hard macro and a plurality of wirings connected to the hard macro. The hard macro comprises a hard macro main body, and a plurality of pins with a minimum pin width based on a design rule of the semiconductor integrated... Agent: Mcdermott Will & Emery LLP

20070061771 - Method for reticle shapes analysis and correction: A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the... Agent: Schmeiser, Olsen & Watts

20070061773 - Method for selecting and optimizing exposure tool using an individual mask error model: Methods are disclosed for selecting and optimizing an exposure tool using an individual mask error model. In one embodiment, a method includes selecting a model of a lithography process including an optical model of an exposure tool and a resist model, creating an individual mask error model representing a mask... Agent: White & Case LLP Patent Department

20070061772 - System and method for mask verification using an individual mask error model: Methods and systems are disclosed to inspect a manufactured lithographic mask, to extract physical mask data from mask inspection data, to determine systematic mask error data based on differences between the physical mask data and mask layout data, to generate systematic mask error parameters based on the systematic mask error... Agent: White & Case LLP Patent Department

20070055951 - Device and method for measuring microporous film on battery electrode plate, coater equipped with film measuring device, and coating method using film measuring method: There is provided a film measuring device capable of accurately and easily measuring the thickness of a microporous film formed on a battery electrode plate over the entire area of the film. A color CCD sensor 8 shoots the microporous film. A video board 11 converts a color tone of... Agent: Mcdermott Will & Emery LLP

20070055950 - System and method for selecting mosfets suitable for a circuit design: The present invention provides a computer-based method for selecting MOSFETs suitable for a circuit design. The method includes the steps of: providing a database (18) that stores specifications and product information of various MOSFETs; receiving specifications of a circuit design; analyzing the circuit design specifications and determining whether the circuit... Agent: North America Intellectual Property Corporation

20070055952 - Method for physical placement of an integrated circuit based on timing constraints: A method, system, apparatus, and machine-readable medium for physical placement of an integrated circuit based on the timing constraints are provided. The method involves a two-pass physical placement technique. After the first pass of the physical placements of the blocks and the top level, the timing results of the top... Agent: Trellis Intellectual Property Law Group, Pc

20070055953 - Distributed hierarchical partitioning framework for verifying a simulated wafer image: A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070050735 - Method, system and program product for specifying and using register entities to configure a simulated or physical digital system: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first... Agent: Dillon & Yudell LLP

20070050736 - Method of facilitating integrated circuit design: An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry (110). The method utilizes one or more library element (150A-F) to provide a flexible modeling template. Each library element includes one or more module ports (160A-F) each for accepting any... Agent: Downs Rachlin Martin PLLC

20070050737 - Functional cells for automated i/o timing characterization of an integrated circuit: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions... Agent: Texas Instruments Incorporated

20070050738 - Customer designed interposer: A method and system that provides a customer with the ability to design an electrical connector (interposer) that is individualized to the customer's particular application requirements. An interface to a design program providing a plurality of design options is provided to the customer to aid in designing an interposer. A... Agent: Neoconix C/o Intellevate

20070050740 - Method and system for performing functional formal verification of logic circuits: The present invention relates to a method, a computer program product and a system for performing functional formal verification. Error detection logic is verified by injecting errors in a hardware design description without any changes to the original design description. With the present invention both permanent and transient faults can... Agent: International Business Machines Corporation

20070050739 - Method and system for performing verification of logic circuits: The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional... Agent: International Business Machines Corporation

20070050741 - Pattern verification method, program thereof, and manufacturing method of semiconductor device: A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070050742 - Timing verification method for semiconductor integrated circuit: Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial... Agent: Mcdermott Will & Emery LLP

20070050744 - Method of selecting cells in logic restructuring: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set.... Agent: Timothy R. Croll Lsi Logic Corporation

20070050743 - Vertical twist scheme for high density drams: An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070050745 - Timing violation debugging inside place and route tool: A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include... Agent: Lsi Logic Corporation

20070050746 - Method and system product for implementing uncertainty in integrated circuit designs with programmable logic: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic... Agent: Harrington & Smith, LLP

20070050747 - Automatic power grid synthesis method and computer readable recording medium for storing program thereof: An automatic power grid synthesis method and a computer readable recording medium for storing a program thereof for synthesizing power grid in a circuit area are provided. The circuit area has at least one power consuming module therein and at least one power pin disposed around the circuit area. The... Agent: J C Patents, Inc.

20070050748 - Method and algorithm for random half pitched interconnect layout with constant spacing: An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines... Agent: Knobbe Martens Olson & Bear LLP

20070050749 - Method for identifying and using process window signature patterns for lithography process control: A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs... Agent: White & Case LLP Patent Department