Data processing: design and analysis of circuit or semiconductor mask inventions 02/07

20070044044 - Automating power domains in electronic design automation: One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a design element (or to a portion thereof) can indicate, for example, whether the element can be switched... Agent: Klarquist Sparkman, LLP

20070044043 - Dbr film for laser imaging: A system for imaging a substrate can comprise an image data source, an electromagnetic radiation source operatively connected to the image data source and configured to emit electromagnetic radiation in accordance with information provided by the image data source, and a DBR film applied to a substrate. The DBR film... Agent: Hewlett Packard Company

20070044045 - Method and apparatus for optimizing a logic network in a digital circuit: One embodiment of the present invention provides a system that optimizes a logic network. During operation, the system receives a first logic network which defines a logical function, wherein the first logic network cannot be efficiently optimized by directly using an optimization process that preserves the logical function. Next, the... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070044046 - Method for providing a current sink model for an asic: A current sink model is provided by determining the charge consumed by each type of a predetermined group of standard cell types under each of a plurality of conditions, determining the quantity of such standard cells of each type in the region of interest on the chip, and then using... Agent: Avago Technologies, Ltd.

20070044047 - Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program: The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven... Agent: Staas & Halsey LLP

20070044049 - Apparatus and methods for predicting and/or calibrating memory yields: An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated... Agent: Ibm Corporation Intellectual Property Law

20070044050 - Method for searching for potential faults in a layout of an integrated circuit: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by... Agent: Morrison & Foerster LLP

20070044048 - System and method for circuit noise analysis: Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic caused by sources. outside the block. More particularly, these systems and methods may generate an abstract... Agent: SprinkleIPLaw Group

20070044051 - Method and system for validating a hierarchical simulation database: System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit... Agent: Morrison & Foerster LLP

20070044052 - Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect: A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for... Agent: F. Chau & Associates, LLC

20070044054 - Buffering technique using structured delay skewing: A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting... Agent: Dickstein Shapiro LLP

20070044055 - Clock signal driver and clock signal supplying circuit having the same: A clock signal driver and a clock signal supplying circuit having the same are provided. An embodiment of the clock signal driver includes an internal clock driver for receiving a clock signal and a complementary clock signal, buffering the clock signal and inverting the complementary clock signal, and combining phases... Agent: Marger Johnson & Mccollom, P.C.

20070044053 - Multimode delay analyzer: A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning... Agent: Lsi Logic Corporation

20070044056 - Macro block placement by pin connectivity: A design tool includes a first module, a second module, a third module and a fourth module. The first module may be configured to select a platform for implementing an integrated circuit design in response to input from a user. The second module may be configured to select a macro... Agent: Lsi Logic Corporation

20070044057 - Semiconductor device with multiple wiring layers and moisture-protective ring: A semiconductor device with a space-saving design of common power lines shared by a plurality of function macros. An LSI chip has a plurality of wiring layers, a moisture-protective ring, and a plurality of function macros (e.g., I/O macros and I/O macro groups). Each function macro has a VSS power... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070044058 - Enabling efficient design reuse in platform asics: A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and... Agent: Lsi Logic Corporation

20070044059 - Ip placement validation: A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information for an intellectual property (IP) block to be placed on a platform application specific integrated circuit, (B) extracting device data for the platform... Agent: Lsi Logic Corporation

20070044061 - Semiconductor device, layout method and apparatus and program: A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is provided in an interconnect layer different from the interconnect layer of the first conductor and which intersects... Agent: Foley And Lardner LLP Suite 500

20070044060 - System and technique of pattern matching and pattern replacement: A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns.... Agent: Aka Chan LLP

20070044062 - Method for checking return path of printed board and cad apparatus for designing patterns of printed board: A CAD apparatus for designing patterns of a printed board, includes: a signal wiring pattern detecting unit 22 for detecting a signal wiring pattern with reference to wiring information of the printed board; a guard ground detecting unit 23 for tracing the signal wiring pattern along the longitudinal direction thereof,... Agent: Wenderoth, Lind & Ponack L.L.P.

20070044063 - Method for estimating voltage droop on an asic: A simulation circuit model for a region of interest in an integrated circuit chip design is constructed that has a number of tiled, substantially identical sub-region simulation circuit models, each representing the supply voltage (VDD) distribution network in one of a number of corresponding sub-regions of the region. This mosaic... Agent: Agilent Technologies Inc.

20070044064 - Processor network: Processes are automatically allocated to processors in a processor array, and corresponding communications resources are assigned at compile time, using information provided by the programmer. The processing tasks in the array are therefore allocated in such a way that the resources required to communicate data between the different processors are... Agent: Potomac Patent Group, PLLC

20070044065 - Reconfigurable integrated circuit device for automatic construction of initialization circuit: A reconfigurable integrated circuit device, in which an arbitrary operating state is constructed based on configuration data, has a reconfigurable circuit unit, having a plurality of reconfigurable processor elements and a processor element network to connect the processor elements in an arbitrary state, and a reconfiguration control portion, which supplies... Agent: Arent Fox PLLC

20070038966 - Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components: A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with... Agent: Seed Intellectual Property Law Group PLLC

20070038965 - Photo printing system and photo printing method: A photo printing system and a photo printing method are provided. The photo printing system includes a printer for receiving printing data, printing an image on an image portion of a photo printing medium on which an image should be printed, and printing a message on a tear-off portion of... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070038967 - System and method for design, procurement and manufacturing collaboration: A method for designing an electronic component includes receiving a device criteria (e.g., a parametric value, procurement value, etc.) from a designer, querying a database for devices corresponding to the device criteria, querying the database for procurement data and/or engineering data associated with the corresponding devices, presenting the devices to... Agent: Henneman & Associates, PLC

20070038964 - System and method for extracting material differences between different circuit board design diagrams: A system is provided for extracting material changes in different design diagrams of a motherboard. The system includes: an extracting module for extracting a first raw BOM from a first circuit design diagram of the motherboard, and for extracting a second raw BOM from a second circuit design diagram of... Agent: North America Intellectual Property Corporation

20070038968 - Increased power line noise immunity in ic using capacitor structure in fill area: Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a... Agent: Hoffman, Warnick & D'alessandro LLC

20070038969 - Electronic ultimate defects analyzer detecting all defects in pcb/mcm: A system for electric testing PCB/MCM before and after assembly. The system uses energy taken from a heating source, timely applied at certain ports of the PCB/MCM (entry ports). The energy is defused through the board inner layer tracks terminating at the end of the channel tracks of the PCB/MCM... Agent: Bruce E. Lilling Lilling & Lilling P.C.

20070038970 - System and method for testing pattern sensitive algorithms for semiconductor design: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each... Agent: Hoffman, Warnick & D'alessandro LLC

20070038971 - Processing device with reconfigurable circuit, integrated circuit device and processing method using these devices: In the processing device in accordance with the present invention, a plurality of divided circuits obtained by dividing one circuit are successively configured on a reconfigurable circuit, an operation is executed by the divided circuits by feeding back an output of one divided circuit to a next divided circuit, and... Agent: Mcdermott Will & Emery LLP

20070038973 - Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout: One embodiment of the present invention determines the effect of placing an assist feature at a location in a layout. During operation, the system receives a first value which was pre-computed by convolving a model with a layout at an evaluation point, wherein the model models semiconductor manufacturing processes. Next,... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070038972 - Method for optimizing a photolithographic mask: The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided. Based on the desired layout pattern, an optimized reference diffraction coefficient is provided. After selecting an initial mask geometry having polygon-shaped structures, initial diffraction coefficients... Agent: Slater & Matsil LLP

20070033547 - Input capacitance characterization method in ip library: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for... Agent: J C Patents, Inc.

20070033548 - Semiconductor integrated circuit device: In a semiconductor integrated circuit device, a VDD wiring trace and a GND wiring trace are routed along an N-well and a P-well, respectively, within a substrate. A substrate-bias VDD2 wiring trace is routed in a direction that intersects the VDD wiring trace and GND wiring trace in the same... Agent: Mcginn Intellectual Property Law Group, PLLC

20070033549 - Interconnect model-order reduction method: An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order... Agent: Nikolai & Mersereau, P.A.

20070033550 - Automated migration of analog and mixed-signal vlsi design: A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source technology. The source circuit includes source components interconnected at nodes in accordance with a source topology. Source voltages at the nodes of the source circuit... Agent: Stephen C. Kaufman IBM Corporation

20070033551 - Method for simulating hardware: Integrated circuit design often involves combination of blocks of circuit from different sources to create new designs. However, a simulation of a block developed using a given method may not be compatible with another simulation created using another method. A method for modifying hardware simulation having one internal timing regime... Agent: Barnes & Thornburg LLP

20070033554 - Delay distribution calculation method, circuit evaluation method and false path extraction method: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects... Agent: Mcdermott Will & Emery LLP

20070033553 - Inductance analysis system and method and program therefor: System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal... Agent: Sughrue Mion, PLLC

20070033552 - Method for detecting flaws in a functional verification plan: This method uses 2 copies of the design under test. These 2 copies use different values (including primary inputs and initial states) to feed the supposedly irrelevant logic while using the same (or consistent as desired) values to feed the feature being verified. Symbolic method is used to efficiently determine... Agent: Zhe Li

20070033556 - Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout: Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer.... Agent: Texas Instruments Incorporated

20070033558 - Method and system for reshaping metal wires in vlsi design: A method and system for representing metal wires in Very Large Scale Integration (VLSI) circuit design in a simplified form. A pair of metal wires is considered at a time. A plurality of Piece Wise Linear (PWL) equations is created to represent sides each of the pair of metal wires.... Agent: Stainbrook & Stainbrook, LLP

20070033557 - Method for creating constraints for integrated circuit design closure: A method for creating constraints for integrated circuit design closure is provided. Design specifications are captured before a design flow is started. The design specifications are checked for compatibility with the design flow. The design specifications are stored in a database. Output transforms are applied to the design specifications to... Agent: Lsi Logic Corporation

20070033559 - Method for using layout regions to predict single-event effects: A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having... Agent: Honeywell International Inc.

20070033555 - Reliability analysis of integrated circuits: Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined,... Agent: Ryan, Mason & Lewis, LLP

20070033560 - Clock tree adjustable buffer: An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The... Agent: The Law Offices Of Gary R. Stanford

20070033561 - Speeding up timing analysis by reusing delays computed for isomorphic subcircuits: One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20070033562 - Integrated circuit power distribution layout with sliding grids: A method and integrated circuit (IC) configuration/design that provides efficient layout of power distribution wires within the IC. The power busses of each IC layers are configured as moveable segments capable of being shifted away from the normal propagation path of the remainder of the power bus. Circuit elements are... Agent: Dillon & Yudell LLP

20070033563 - Method of semiconductor device and design supporting system of semiconductor device: A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval between adjacent two of interconnections, the interconnection intervals being discrete; and by specifying an interconnection relating an impermissible width and interconnections relating to an impermissible... Agent: Foley And Lardner LLP Suite 500

20070033564 - Analysis method and analysis apparatus: An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into... Agent: Foley And Lardner LLP Suite 500

20070033565 - Basic cell of semiconductor integrated circuit and layout method thereof: Basic cells each including, in addition to logic cells, one or a plurality of capacity cells between a power supply line and a ground line, and the like, are prepared in advance in the form of a logic synthesis cell library. The prepared basic cells are inserted at a logic... Agent: Mcdermott Will & Emery LLP

20070033566 - Storage management unit to configure zoning, lun masking, access controls, or other storage area network parameters: Some of the embodiments disclosed are systems and methods of configuring an access masking structure which include, but are not limited to, selecting at least one computer to participate in an access restriction set, selecting at least one storage unit to participate in the access restriction set, disabling all non-selected... Agent: Conley Rose, P.C.

20070028193 - Multiple voltage integrated circuit and design method therefor: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20070028194 - Semiconductor device: In a semiconductor device having a large-scale arithmetic circuit, when there is delay in clock signals, a malfunction occurs in a circuit. In particular, in an environment where supply voltage varies as in a wireless chip, it is very difficult to precisely estimate delays in clock signals in designing. Further,... Agent: Eric Robinson

20070028195 - Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models: System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction... Agent: Scully Scott Murphy & Presser, PC

20070028198 - Method and apparatus for allocating data paths to minimize unnecessary power consumption in functional units: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises power management formulations can be used to gear the allocation process to generate hardware architecture of minimal spurious switching. Bipartite weighted Assignment is used to determine the sharing of functional units, through cost formulations and the Hungarian... Agent: Greenblum & Bernstein, P.L.C

20070028197 - Method and apparatus for auto-generation of shift register file for high-level synthesis compiler: A method and apparatus for auto-generation of shift register file for high-level synthesis compiler includes parsing input source codes for specific definition of shift register file, a plurality of compiler directives to indicate the shift register file name, shift register file size, shift register file read access order, and shift... Agent: Greenblum & Bernstein, P.L.C

20070028196 - Resource estimation for design planning: A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the integrated circuit design is generally complete, while a second portion of the integrated circuit design is generally incomplete. A second step... Agent: Lsi Logic Corporation

20070028199 - Delay computation speed up and incrementality: A method of computing output delay in a mathematical model of an integrated circuit original design by sorting cells of the original design in a topological order. The original output delays for the cells in the original design are computed in the sorted order, to produce original output ramp times.... Agent: Lsi Logic Corporation

20070028200 - Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements: Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first... Agent: Texas Instruments Incorporated

20070028201 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: J. Scott Denko

20070028202 - Method and apparatus for generating design information, and computer product: An apparatus generates design information on a via hole that passes through predetermined layers of a multilayer wiring board. A storing unit stores information on at least one of a shape and a size of a land to be provided around the via hole. A design-information generating unit generates the... Agent: Staas & Halsey LLP

20070028203 - Apparatus and method for creating function verification description, and computer-readable recording medium in which program for creating function verification description is recorded: To create a function verification description, which is used for verifying a result of simulation performed on a finite state machine, irrespective of description languages of designing an FSM and creating the function verification description even by a person without knowledge of the language and the creation method of the... Agent: Staas & Halsey LLP

20070028204 - Method and program for high-level synthesis, and method for verifying a gate network list using the high-level synthesis method: A method for high-level synthesis includes extracting difference information of a first and a second behavioral description, generating a first register transfer level description from the first behavioral description while generating mapping information of the first behavioral description and the first register transfer level description, modifying the first register transfer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070028205 - Data processing method in semiconductor device, program of the same, and manufacturing method of semiconductor device: A design data processing method in a semiconductor device includes extracting, from design data, a graphic in which there exist a first wiring and a second wiring which is orthogonal to the first wiring, and changing a portion where the first wiring is orthogonal to the second wiring to make... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070028206 - Layout generation and optimization to improve photolithographic performance: Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance... Agent: Haynes And Boone, LLP