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Data processing: design and analysis of circuit or semiconductor mask January USPTO class patent listing 01/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/25/2007 > 11 patent applications in 8 patent subcategories. USPTO class patent listing
20070022392 - Multi-variable polynomial modeling techniques for use in integrated circuit design: Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage slew, capacitive load, supply voltage or temperature. Error values... Agent: Ryan, Mason & Lewis, LLP
20070022393 - Recognition of a state machine in high-level integrated circuit description language code: A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as VHDL and Verilog®, of an IC design and extracts description information corresponding to a state machine. The description information can be,... Agent: Klarquist Sparkman, LLP
20070022394 - Estimating the difficulty level of a formal verification problem: Estimating the difficulty level of a verification problem includes receiving input comprising a design and properties that may be verified on the design. Verification processes are performed for each property on the design. A property verifiability metric value is established for each property in accordance with the verification processes, where... Agent: Baker Botts L.L.P.
20070022396 - Method and apparatus for expanded data rate control indices in a wire less communication system: In one embodiment, the patent application comprises an apparatus, method and means for expanding DRC indices comprising assigning multiple DRC covers to at least one sector. In another embodiment, the apparatus, method and means for expanding DRC indices further comprises creating an expanded DRC indices list, sending a mapping of... Agent: Qualcomm Incorporated
20070022395 - Power estimation employing cycle-accurate functional descriptions: A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.... Agent: Brosemer, Kolefas & Associates, LLC (necl)
20070022397 - Apparatus and method for performing static timing analysis of an integrated circuit design using dummy edge modeling: An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by creating a dummy clock edge that is on the same edge as... Agent: Martin & Associates, LLC
20070022398 - Via/bsm pattern optimization to reduce dc gradients and pin current density on single and multi-chip modules: A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having... Agent: Ibm Corporation (jvm)
20070022399 - Rule-based schematic diagram generator: A schematic diagram generator processes a netlist or similar circuit description to determine how to place and orient symbols representing devices forming the circuit based on a set of placement rules. Each rule corresponds to a separate characteristic pattern of interconnected devices, and specifies a constraint on relative positioning and/or... Agent: Smith-hill And Bedell, P.C.
20070022400 - Method, program, and apparatus for designing layout of semiconductor integrated circuit: In a method for designing a layout for an LSI, library data, which is information on a standard cell with an assigned parameter or parameters each indicating the probability of occurrence of violations of design rules at a pin connection point, is read into a library information read section in... Agent: Mcdermott Will & Emery LLP
20070022401 - Method of correcting mask pattern and correcting apparatus thereof: A method of correcting a mask pattern is provided. First, an original writer drawing data of a circuit layout pattern is inputted. Then, according to the original writer drawing data, a correcting writer rule is selected by searching from a look-up table. According to the correcting writer rule, the original... Agent: Jianq Chyun Intellectual Property Office
20070022402 - System and method for lithography simulation: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present... Agent: Neil A. Steinberg01/18/2007 > 7 patent applications in 6 patent subcategories. USPTO class patent listing
20070016879 - Method for identifying a physical failure location on an integrated circuit: A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or more test patterns to identify a failure port thereon. Hierarchical information of the failure port is generated through the test... Agent: Howard Chen Preston Gates & Ellis LLP
20070016880 - Apparatus and method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip: An apparatus and method are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20070016881 - Automation method and system for assessing timing based on gaussian slack: An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP
20070016882 - Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture: In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for... Agent: Baker Botts L.L.P.
20070016883 - Clock gating circuit: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20070016884 - Apparatus, method, and medium for designing semiconductor integrated circuit: A clock tree configuration is modified so that a branch point of a clock tree is arranged closer to a leaf of the tree, thereby restraining an increase in a clock skew due to variation.... Agent: Foley And Lardner LLP Suite 500
20070016885 - Logic-synthesis method and logic synthesizer: The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes the steps of generating a library having a buffer-tree-characteristic description, determining the position where the fanout value is high by analyzing a... Agent: Staas & Halsey LLP01/11/2007 > 7 patent applications in 6 patent subcategories. USPTO class patent listing
20070011627 - Compilable, reconfigurable network processor: A processor, particularly a network processor, is designed by first writing code to be processed by the processor. That code is then electronically compiled to design hardware of the processor and to provide executable code for execution on the designed hardware. To facilitate compilation, the written code may be restricted... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
20070011628 - Method and apparatus for removing dummy features from a data structure: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and... Agent: Sterne, Kessler, Goldstein & Fox PLLC
20070011629 - Adaptive application of sat solving techniques: A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance... Agent: Stephen C. Kaufman IBM Corporation
20070011631 - Harnessing machine learning to improve the success rate of stimuli generation: Test generation is improved by learning the relationship between an initial state vector for a stimuli generator and generation success. A stimuli generator for a design-under-verification is provided with information about the success probabilities of potential assignments to an initial state bit vector. Selection of initial states according to the... Agent: Stephen C. Kaufman IBM Corporation
20070011633 - Method and system for performing functional verification of logic circuits: A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a... Agent: Ibm Corporation Intellectual Property Law
20070011630 - Methods for computing miller-factor using coupled peak noise: A method for computing a Miller-factor compensated for peak noise is provided. The method includes mapping at least two delays as a function of at least two Miller-factors; determining an equation of the function; computing a peak noise; computing a peak delay resulting from the peak noise; and computing the... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP
20070011632 - System and method for comparing two circuit designs: A method for comparing a new circuit design with a corresponding old circuit design is disclosed. The method includes the steps of: creating two components attributes documentations according to a new circuit design and a corresponding old circuit design; receiving the two components attributes documentations; comparing the two components attributes... Agent: North America Intellectual Property Corporation
20070011634 - Semiconductor testing apparatus: Intends to provide semiconductor testing apparatus that can reduce effort to adjust generating timing of a clock signal to be extracted from data or a time required in adjustment. It includes a timing comparator 154 for receiving data outputted from a DUT 200; a clock generating circuit 120 for generating... Agent: Patenttm.us
20070011635 - Method of selling integrated circuit dies for multi-chip packages: An integrated circuit has a plurality of bonding pads, at least one of which is adapted to be directly electrically connected to a bonding pad of another integrated circuit rather than to an external pin of a package that houses a semiconductor die on which the integrated circuit is fabricated.... Agent: Dr. Mark Friedman Ltd. C/o Mr. Bill Polkinghorn
20070011637 - Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device: At least one cell pair graph is generated for cells of the layout. A partial inverse layout tree is determined from the cell pair graph. For the partial inverse layout tree, only branches of the complete inverse layout tree are considered that describe an interaction between shapes of different cells.... Agent: Slater & Matsil LLP
20070011636 - Method and system for performing non-local geometric operations for the layout design of a semiconductor device: In one embodiment, an automatic check is performed to determine if the output of a parent region is compatible with the output of a current region of a cell. If the output of the parent region is compatible with the output of the current region of a cell, the output... Agent: Slater & Matsil LLP
20070011638 - Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit: A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a second wiring pattern having a second termination pattern and a second line pattern connected to an end of... Agent: Dla Piper Rudnick Gray Cary Us, LLP
20070011639 - Placement methods for standard cell library: Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit layouts for design rule compliance. Upon detection of noncompliance, the macros associated with noncompliance are adapted to bring the layout within the design rules. In a preferred... Agent: Texas Instruments Incorporated
20070011640 - Lsi circuit: A power line for supplying a power supply voltage to a clock buffer and a power line for supplying a power supply voltage to another circuit are isolated from each other in both a semiconductor integrated circuit and a semiconductor package. Accordingly, even when power supply noise occurs in the... Agent: Mcdermott Will & Emery LLP
20070011641 - Semiconductor integrated circuit device: The semiconductor integrated circuit device includes a plurality of grid-like wiring structures 150 arranged as unit regions in an entire circuit area and having the same shape as a clock wiring structure, respectively; a first wiring structure in which the wiring paths from an clock input 110 to the respective... Agent: Mcdermott Will & Emery LLP
20070011642 - Application specific configurable logic ip: An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric,... Agent: Lsi Logic Corporation
20070011643 - Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass: A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first... Agent: Morrison & Foerster LLP
20070011645 - Method for time-evolving rectilinear contours representing photo masks: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati
20070011644 - Optimized photomasks for photolithography: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati
20070011646 - Parallel decoupled mesh generation: A method of mesh generation processing for a bounded domain is provided. The bounded domain is divided into constituent sub-domains with a portion of the sub-domains being assigned to each of a plurality of processors. The processors are operated independently and in parallel. Each processor (i) discretizes the closed boundary... Agent: William And Mary Technology Transfer Office
20070011648 - Fast systems and methods for calculating electromagnetic fields near photomasks: Photomask patterns are represented using contours defined by mask functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati
20070011647 - Optimized photomasks for photolithography: Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to... Agent: Wilson Sonsini Goodrich & Rosati01/04/2007 > 7 patent applications in 6 patent subcategories. USPTO class patent listing
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