Data processing: design and analysis of circuit or semiconductor mask inventions 12/06

20060294478 - Method and system for reducing delay noise in an integrated circuit: A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance... Agent: Freescale Semiconductor, Inc. Law Department

20060294480 - Library creating device and interconnect capacitance estimation system using the same: An interconnect capacitance estimation system includes a first storage device, a library creating device and an interconnect capacitance estimating device. The first storage device stores layout data. The library creating device creates a library used for estimating a capacitance of a net in a semiconductor circuit based on the layout... Agent: Foley And Lardner LLP Suite 500

20060294479 - System for analyzing an electronic circuit described by characterization data: A system for analyzing an electronic circuit described by characterization data forms an interpolation/approximation function over an analysis interval for analyzing the electronic circuit. An edge detection is applied to the characterization data to determine edges in the data, with the detected edges as subinterval limits used to form subinterval... Agent: Brinks Hofer Gilson & Lione Infineon

20060294481 - Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework: A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the... Agent: Dillon & Yudell LLP

20060294482 - Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design: A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net... Agent: Lsi Logic Corporation

20060294483 - Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems: A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level... Agent: Martine Penilla & Gencarella, LLP

20060294484 - Method for auto enlarging bend portion width and computer readable recording medium forstoring program thereof: A method for auto enlarging bend portion width and a computer readable recording medium for storing program thereof are provided. The method can enlarge the bend portion width from an original width to an intended width in layout. Wherein, the terminals of the center line of the bend is a... Agent: Jianq Chyun Intellectual Property Office

20060294485 - Method and apparatus for routing an integrated circuit: A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20060294487 - Auto connection assignment system and method: A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second... Agent: Schmeiser, Olsen & Watts

20060294486 - Manhattan routing with minimized distance to destination points: For routing points to a center point, the points are grouped into a respective set disposed within each quadrant. Each point is Manhattan routed to any other point having a minimum Manhattan distance within a rectangle defined by each point and the center point, to result in at least one... Agent: Law Office Of Monica H Choi

20060294488 - Integrated circuit routing and compaction: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing... Agent: Aka Chan LLP

20060294489 - Pad layouts of a printed circuit board: A pad layout of a printed circuit board includes a first and a second pad symmetrically arranged on the PCB for cooperatively receiving either a first surface mounted component (SMC) or a second surface mounted component (SMC). Each of the SMCs includes a first footprint and a second footprint. The... Agent: Morris Manning Martin LLP

20060294490 - Apparatus for performing computational transformations as applied to in-memory processing of stateful, transaction oriented systems: An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data paths. The plurality of access data paths are also configurable for a... Agent: Martine Penilla & Gencarella, LLP

20060294491 - Methods for creating primitive constructed standard cells: A high-level logic description is developed based on a non-primitive-based standard cell. library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic... Agent: Martine Penilla & Gencarella, LLP

20060288315 - Method and apparatus for compiling a parameterized cell: A method of generating a parameterized cell is disclosed herein. The method comprises performing a compiling interpretation (56) on a structure layout. The compiling interpretation (56) includes i) determining and analyzing shape relationships of the structure layout (72), and ii) mapping shapes and calculating properties of mapped shapes (74). The... Agent: Freescale Semiconductor, Inc. Law Department

20060288316 - Semiconductor device having predictable electrical properties: A circuit element of a semiconductor device is provided. The circuit element has an electrical property and is formed by at least two like individual elements, each of said individual elements having an individual electrical property, the individual electrical property of each individual element including an error portion that is... Agent: Gowling Lafleur Henderson, LLP Suite 2600

20060288317 - Element arrangement check device and printed circuit board design system: An element placement check system for checking element placement on a printed wiring board having wiring by which a power supply terminal of an integrated circuit and a power supply decoupling element for the power supply terminal are connected on a mounting surface on which the integrated circuit is mounted,... Agent: Wenderoth, Lind & Ponack L.L.P.

20060288318 - Method and apparatus for associating an error in a layout with a cell: One embodiment of the present invention provides a system that associates an error in a layout with a cell. During operation, the system receives a layout which is designed to create a target feature with an intended shape. Next, the system determines an error in a critical dimension of the... Agent: Synopsys, Inc C/o Park, Vaughan & Fleming LLP

20060288320 - Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree: In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The... Agent: Baker Botts L.L.P.

20060288319 - Method and system for designing a timing closure of an integrated circuit: Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between... Agent: Rosenberg, Klein & Lee

20060288321 - Method for computer aided design of semiconductor integrated circuits: In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining... Agent: Mcdermott Will & Emery LLP

20060288322 - Incremental geotopological layout for integrated circuit design: Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout... Agent: Lumen Intellectual Property Services, Inc.

20060288323 - High-speed shape-based router: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be... Agent: Aka Chan LLP

20060288324 - Semiconductor device, and design method, inspection method, and design program therefor: A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20060288325 - Method and apparatus for measuring dimension of a pattern formed on a semiconductor wafer: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060282798 - Efficient electromagnetic modeling of irregular metal planes: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using... Agent: Ibm Corporation (jvm)

20060282800 - Bus representation for efficient physical synthesis of integrated circuit designs: A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the compactness of a bus level representation as well as the uniqueness of a bit level representation. Connectivity abstraction significantly reduces network complexity, i.e., the... Agent: Sughrue Mion, PLLC

20060282801 - Enhanced method of optimizing multiplex structures and multiplex control structures in rtl code: A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and... Agent: Lsi Logic Corporation Corporate Legal Department

20060282799 - Method of determining high-speed vlsi reduced-order interconnect by non-symmetric lanczos algorithm: Two-sided projection-based model reductions has become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered... Agent: Nikolai & Mersereau, P.A.

20060282803 - Estimation of average-case activity for digital circuits: A method for estimating the average-case activity in a digital circuit includes the steps of assigning initial activity values to outputs of flops in the digital circuit, and repeatedly updating the activity values in an iterative procedure until a predetermined termination criterion is met, wherein the updating of the activity... Agent: Townsend And Townsend And Crew, LLP

20060282802 - Method of extracting a semiconductor device compact model: This invention is a method of extracting a semiconductor device compact model by using knowledge of the equations used inside the compact model. Starting by fitting a small subset of the model parameters, the remaining model parameters are fitted and as each new subset of model parameters are fitted, the... Agent: Sitaramarao Srinivas Yechuri

20060282804 - Novel test structure for automatic dynamic negative-bias temperature instability testing: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement... Agent: The Law Offices Of Mikio Ishimaru

20060282805 - Method for verifying a circuit design by assigning numerical values to inputs of the circuit design: A method for verifying a circuit design comprises a step of assigning numerical values 1/ai to input ports of the circuit design according to a function ai+1=(ai−1)2+1, wherein represents the number of the input port and the numerical value a1 is not equal to 2 or 1. Preferably, a1 is... Agent: John S. Egbert Egbert Law Offices

20060282807 - Software verification: A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system.... Agent: Brosemer, Kolefas & Associates, LLC (necl)

20060282806 - Software verification using range analysis: A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime.... Agent: Brosemer, Kolefas & Associates, LLC (necl)

20060282808 - Automatic generation of correct minimal clocking constraints for a semiconductor product: A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing... Agent: Lsi Logic Corporation

20060282809 - Logic transformation and gate placement to avoid routing congestion: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage.... Agent: Schmeiser, Olsen & Watts

20060282810 - Fullchip functional equivalency and physical verification: A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived from symbolic connectivity.... Agent: Hamilton & Terrile, LLP

20060282811 - Printed circuit board design support apparatus, method, and program medium therefor: Printed circuit board (PCB) design support apparatus and method are provided. The target element disposed on a front surface of the printed circuit board is mirror-copied, and then the straight line distance between the mirror copied element and a back element disposed on the back surface of the PCB is... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.

20060282812 - Communication network for multi-element integrated circuit system: Embodiments of the invention include a system for communication within an integrated circuit. Hardware object nodes are connected to one another through a system of physical channels. Messages are sent from one node to another over the channels. The messages can be asynchronous in nature, as well as time-insensitive. Different... Agent: Ambric, Inc. C/o Marger Johnson & Mccollom PC

20060282813 - Development system for an integrated circuit having standardized hardware objects: Embodiments of the invention include a system for integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of... Agent: Ambric, Inc. C/o Marger Johnson & Mccollom PC

20060282814 - Method for verifying and choosing lithography model: A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures... Agent: Jerry Richard Potts

20060277505 - Method for automatically designing semiconductor device and automatic designing apparatus thereof: In an area extracting step, areas interposed among tower post rows adjacent to one another, and rectangular areas interposed among the tower post rows and pads at outer peripheral portions of a chip are respectively extracted as areas in which equalization of wire spacings is performed. Areas interposed among tower...

20060277506 - System and method for product yield prediction: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at...

20060277508 - Method and system for enhanced verification through binary decision diagram-based target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is...

20060277507 - Method and system for enhanced verification through structural target decomposition: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more...

20060277509 - System and method for analyzing power consumption of electronic design undergoing emulation or hardware based simulation acceleration: The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the...

20060277510 - Verification support device, verification support method, and computer product: A verification support device supports logic verification of a design object corresponding to modified sequence diagrams obtained by modifying sequence diagrams expressing processes of a design object in a chronological order. A diagram extracting unit extracts the modified sequence diagrams. A modified process detecting unit detects modified processes by comparing...

20060277512 - Engineering change order process optimization: A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff...

20060277513 - System and method for incremental statistical timing analysis of digital circuits: The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing...

20060277511 - System and method for memory element characterization: A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed...

20060277514 - Method and system for distributing clock signals on non-manhattan semiconductor integrated circuits: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that...

20060277515 - Method, system and storage medium for determining circuit placement: A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A...

20060277516 - Digital lien service: A process of digital electronic lien management is provided. Form data is stored in a first electronic database. A user adds lien input data in a second electronic database related to a specific construction lien project. A user then generates at least one lien form through insertion of the lien...

20060277517 - Wire spreading through geotopological layout: The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing. Preferably, the wire spreading is performed on a geotopological layout. Each modifiable wire thereof is processed to generate a geometric bottom-up shape (BUS)...

20060277518 - High order synthesizing method and high order synthesizing apparatus: A signal in a hardware description corresponding to a variable or an expression in an operation description is identified so that a tracing description for hardware description for obtaining a transition history of a signal in the hardware description corresponding to a tracing object in the operation description is generated....

20060277519 - System and method for optical proximity correction: A method of optical proximity correction is described. The method includes selecting all islands, increasing the size of each said island. The facing sides of each island is pulled back equally if island to island spacing is insufficient between two islands. A further step of pulling back equally the facing...

20060277522 - Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs: Optical proximity effects (OPEs) are a well-known phenomenon in photolithography. OPEs result from the structural interaction between the main feature and neighboring features. It has been determined by the present inventors that such structural interactions not only affect the critical dimension of the main feature at the image plane, but...

20060277520 - Method of locating areas in an image such as a photo mask layout that are sensitive to residual processing effects: Images such as mask layouts, signatures, and photographs are compared to identify similarities or dissimilarities in the images. Descriptions of the images use geometric shapes including lines, rectangles, and triangles to facilitate the comparisons and decrease comparison time and decrease stored data describing the shapes. Data for pixels in the...

20060277521 - Method, program product and apparatus for performing double exposure lithography: A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process. The method includes the steps of: defining an initial H-mask corresponding to the target pattern; defining an initial V-mask corresponding to the target...