Data processing: design and analysis of circuit or semiconductor mask inventions 10/06

20060242611 - Integrating programmable logic into personal computer (pc) architecture: A portion of chip die real estate is allocated to blocks of programmable logic (PL) fabric. These blocks can be used to load special purpose processors which operate in concert with the general purpose processors (GPPs). These processors, implemented in PL, may integrate with a PC system architecture. Blocks of...

20060242610 - Systems and methods of data traffic generation via density estimation: Systems and methods for providing density-based traffic generation. Data are clustered to create partitions, and transforms of clustered data are constructed in a transformed space. Data points are generated via employing grid discretization in the transformed space, and density estimates of the generated data points are employed to generate synthetic...

20060242612 - A crosstalk checking method using paralled line length extraction: In a parallel line length extracting procedure, a layout and a reference value per pitch describing a restriction value of a parallel line length different according to a line pitch are input, thereby extracting the parallel line length between adjacent lines. In a parallel line length checking procedure per pitch,...

20060242613 - Automatic floorplanning approach for semiconductor integrated circuit: In an automatic floorplanning approach, flexibility is given to the shape and area of a black-box block set in advance, so that the shape and area of the black-box block are made to reflect influences of line congestion and the like at the chip level, and also become less influential...

20060242614 - Method and mechanism for implementing automated pcb routing: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path...

20060242615 - Printed wiring board design method, program thereof, recording medium storing the program recorded therein, printed wiring board design device using them and cad system: A printed wiring board design method including the steps of designing placement and wiring for circuit components based on circuit information on a mounting surface of the board; excluding a placement region and a wiring region for the circuit components from the mounting surface to thereby calculate a placement and...

20060242616 - Methods and apparatus for design entry and synthesis of digital circuits: Methods and apparatus are provided for design entry and synthesis of components, such as components implemented on a programmable chip. In one example, a design tool receives natural or intuitive parameters describing characteristics of a component in a design. Natural or intuitive parameters include input data rate, output latency, footprint,...

20060242617 - Automatic generation of streaming processor architectures: A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a...

20060242618 - Lithographic simulations using graphical processing units: Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography...

20060242619 - System and method for providing defect printability analysis of photolithographic masks with job-based automation: Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a...

20060236270 - Composable system-in-package integrated circuits and process of composing the same: An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when...

20060236271 - Optical lithography correction process: A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations....

20060236272 - System and method for automatically calculating parameters of an mosfet: A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values input by the users, and for calculating parameters of the MOSFET according to the input values. The parameter calculating system includes a...

20060236273 - System, method and program for designing a semiconductor integrated circuit using standard cells: A computer implemented method for designing a semiconductor integrated circuit includes analyzing information of standard cells to be arranged in a chip area based on circuit behavior information so as to generate standard cell information, generating a mega cell including a group of standard cells, based on the standard cell...

20060236274 - Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms: A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satsifability solver operations with respect to said initial...

20060236275 - Method for determining relevant circuit parts in a circuit in the event of loading with a temporally variable signal: Method for determining relevant circuit parts in a circuit in the event of loading with a temporally variable signal, the circuit having a number of circuit components which are connected up to one another and are in each case connected up by means of connections between at least two circuit...

20060236277 - Method, apparatus, and computer program product for implementing vertically coupled noise control through a mesh plane in an electronic package design: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically...

20060236276 - System and method for evaluating signal coupling between differential traces in a package design: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the...

20060236279 - Design supporting apparatus, design supporting method, and computer product: A design supporting apparatus includes a detecting unit that detects a path constituting a circuit from circuit information of the circuit; a sensitivity-equation producing unit that produces a calculating equation for a sensitivity indicating a change rate of a parameter regarding a delay of a circuit element constituting the path,...

20060236280 - Method and apparatus for analyzing clock-delay, and computer product: An input unit receives circuit information on a circuit. A first calculating unit calculates delay-distribution information of a data path and delay-distribution information of a clock path, based on the circuit information. A second calculating unit calculates delay-difference-distribution information between the data path and the clock path by using the...

20060236278 - Method of automatic generation of micro clock gating for reducing power consumption: A method and apparatus for reducing transitions thereby reducing power consumption for a clocked output state-holding element having inputs that are respective logic functions of one or more clocked input state-holding elements. A respective valid line is associated with each of the clocked input state-holding elements whose value indicates whether...

20060236284 - Design method by estimating signal delay time with netlist created in light of terminal line in macro and program for creating the netlist: A design method that implements automatic layout based on a first netlist created from a design circuit includes laying out a plurality of functional blocks of the design circuit based on the first netlist, creating a second netlist where information on line resistance and line capacitance of a line between...

20060236282 - Layout method of semiconductor integrated circuit and cell frame standardization program: Cells with the same logic and similar driving capability among cells arranged on a substrate of a semiconductor integrated circuit are made into a format comprising terminals at the same position in the same-sized cell frame, and within cells in such a format, by arranging other cells in a redundant...

20060236281 - Logic circuit design method, computer-readable recording medium having logic circuit design program stored therein, and logic circuit design device: A logic circuit design method for use in a logic circuit having a hierarchical structure including an instance, a first block, and a second block is disclosed. The logic circuit design method includes the steps of reading information about the logic circuit, moving an instance which has a signal connection...

20060236283 - Method of designing layout of semiconductor integrated circuit and apparatus for doing the same: A method of designing a layout of functional blocks and on-chip capacitors in a semiconductor integrated circuit, includes the steps of, in sequence, (a) placing a functional block, (b) placing an on-chip capacitor in an area which remains vacant after the step (a) has been carried out, (c) overlapping a...

20060236286 - Cost-optimization method: A method of controlling an optimal cost is proposed, which can be applied to a circuitry designing process for making electronic products, allowing a user in drawing a circuitry to choose elements of identical specification with different unit prices, thereby achieving the objective of cost-optimization. The cost-optimization method comprises the...

20060236289 - Design support apparatus, design support method, and computer product: An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link...

20060236287 - Flexible shape identification for optical proximity correction in semiconductor fabrication: Transient edges are used to define shapes in an integrated circuit layout for optical proximity correction. A first variation of the shape includes a first edge, a second edge satisfying an edge transition angle condition in relation to the first edge, and one or more first transition edges connected between...

20060236285 - Method for improving efficiency in laying out electronic components: A method is proposed for improving the layout efficiency in laying out electronic components, which is applicable to information processing equipment, to accelerate the layout of electronic components. First, a first two-dimensional plan view including various electronic component members is preset using a drafting software platform. Subsequently, the two-dimensional plan...

20060236288 - Window operation interface for graphically revising electrical constraint set and method of using the same: A window operation menu for graphically revising an electrical constraint set and a method of using the same. It may be used to graphically preview and revise the attribute contents of the electrical constraint set analyzed and exported by the wiring software, so that the batch revisions can be performed...

20060236290 - Systems and methods for wiring circuit components: Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to...

20060236291 - Analytical placement method and apparatus: In this equation, n represents a net, p(n) represents a unique pair of pins i and j of the net n, x and y represent the x-, and y-coordinates of a particular pin, and bi,j represents a weighting factor that biases the function based on the desired closeness of pins...

20060236292 - Base platforms with combined asic and fpga features and process of using the same: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory...

20060236293 - Method and apparatus for comparing and synchronizing programmable logic device user configuration dataset versions: A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e.g., the user configuration dataset including old features as well as newly-added features) for the “origin” programmable logic device to the existing user configuration...

20060236294 - Computer-implemented methods for detecting defects in reticle design data: Computer-implemented methods for detecting defects in reticle design data are provided. One method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The...

20060236295 - Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems: Provided is a method and system for developing a lithographic mask layout. The lithographic mask layout is adapted for configuring an array of micro-mirrors in a maskless lithography system. The method includes generating an ideal mask layout representative of image characteristics associated with a desired image. Next, an equivalent mask...

20060236296 - Method and apparatus for identifying assist feature placement problems: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems due to a missing or an improperly placed assist feature. During operation, the system receives an uncorrected or corrected mask layout. The system then dissects the...

20060236298 - Convergence technique for model-based optical and process correction: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping...

20060236299 - Mask creation with hierarchy management using cover cells: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to...

20060236297 - Method and apparatus for assessing the quality of a process model: One embodiment of the present invention provides a system that assesses the quality of a process model. During operation, the system receives a mask layout and additionally receives a process model that models the effects of one or more semiconductor manufacturing processes on the mask layout. Next, the system computes...

20060230364 - Method and computer program product for generation of bus functional models: In accordance with the present invention, there is provided a method for creating a Bus Functional Model of an Integrated Circuit. The method comprises the following steps: providing (102) a detailed specification of said Integrated Circuit, defining (104) an architecture for said Bus Functional Model. In the following step data...

20060230365 - Method for designing a circuit, particularly having an active component: A method for designing a circuit, particularly having an active component, preferably a high-frequency circuit, wherein: (a) a plurality of load lines is determined at least approximately; (b) a course of a small-signal parameter along each load line is determined at least approximately; (c) a region of each load line...

20060230367 - Method and system for reduction of and/or subexpressions in structural design representations: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from...

20060230366 - Method and system for reduction of xor/xnor subexpressions in structural design representations: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set...

20060230368 - Detecting short circuits within an integrated circuit design: In one embodiment, the present invention includes a method for obtaining a physical layout for an integrated circuit (IC) design of a substrate having at least one of an n-well and a deep n-well; and extracting a layout netlist for the IC design from the physical layout by identifying the...

20060230369 - Interface configurable for use with target/initiator signals: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of...

20060230371 - Alternative methodology for defect simulation and system: A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the...

20060230372 - Device and method for testing an electric circuit: A method and device for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner is provided. A marking signal is produced, indicating a predefined circuit state that might occur in specific components of an electric circuit, wherein...

20060230370 - System and method for engine-controlled case splitting within a multiple-engine based verification framework: A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of verification engines divides the verification problem into a set of partitions and passes at least one of the...

20060230373 - Intelligent timing analysis and constraint generation gui: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The...

20060230374 - System and method for analyzing crosstalk occurring in a semiconductor integrated circuit: A system for analyzing crosstalk occurring in a semiconductor integrated circuit, includes calculating timing windows of first and second wires under a first and second analysis conditions, a sequence determination module determining whether a sequence of the timing windows of the first and second wires interchanges, and an analysis module...

20060230375 - Integrated circuit with relocatable processor hardmac: An integrated circuit layout is provided, which includes a base platform for an integrated circuit, a processor hardmac and a support memory. The base platform includes a memory matrix having leaf cells arranged in rows and columns. Each column of leaf cells has interface pins that are routed to a...

20060230376 - Methods for creating and expanding libraries of structured asic logic and other functions: Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured...

20060230377 - Computer-based tool and method for designing an electronic circuit and related system: A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of...

20060225004 - Apparatus for giving assistance in analyzing deficiency in rtl-input program and method of doing the same: An apparatus for giving assistance in analyzing deficiency in a RTL-input program, includes a partial RTL creator which creates partial RTL description data containing logic description identical with logic description extracted from successive portions of input RTL description data, and having correspondence in signals identical with the same in the...

20060225002 - Circuit having hardware threading: Hardware threading optimizes use of hardware resources in a dynamic workload environment. Unutilized hardware resources are dynamically borrowed to increase throughput performance and/or power savings by enabling parallel processing of application pipeline stages....

20060225003 - Engineering design system using human interactive evaluation: A design system includes a design engine for generating designs, an evaluation process for evaluating the generated designs based on human visual inspection and/or domain knowledge, and an optimization process for pruning based at least in part on the evaluation. Generation of additional designs is performed based on optimization. Newly-generated...

20060225007 - Antenna effect prevention by model extraction in a circuit design for advanced processes: A method is disclosed for determining an antenna ratio for an interconnect in a circuit. The interconnect may be routed through one or more connection layers and may be electrically coupled to one or more gate oxide areas. A cumulative antenna ratio for all components on each connection layer is...

20060225006 - Method and apparatus of optimizing the io collar of a peripheral image: An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO...

20060225005 - Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic: Methods, systems and program products are disclosed that prioritize each target via for via redundancy based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic, and attempt to add a...

20060225008 - Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations,...

20060225009 - Computing current in a digital circuit based on an accurate current model for library cells: In one embodiment, a method for computing current in a digital circuit based on an accurate current model for library cells includes accessing a cell library, for each cell in the cell library corresponding to a cell in a digital circuit, generating multiple waveforms of current drawn by the cell...

20060225010 - Semiconductor device and scan test method: A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a second separation clock signal and to supply the second separation clock signal to a test circuit. The logic circuit generates...

20060225012 - Layout verification method and layout design unit: By providing plural layers in which circuit components of an integrated circuit using plural voltages are arranged in accordance with used voltages, separately arranging the circuit component to which a high voltage is applied in a specific layer among the plural layers, recognizing the used voltage for each layer, and...

20060225013 - Method of designing semiconductor integrated circuit and apparatus for designing the same: A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether...

20060225011 - Method of tiling analog circuits: The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in...

20060225014 - Timing analysis method, timing analysis program, and timing analysis tool: This invention intends to provide timing analysis methods, timing analysis programs, and timing analysis tools for the purpose of performing timing verification in optimum conditions without any excessive variations by statistically dealing with variations in elemental devices forming a semiconductor integrated circuit. In order to verify a timing between two...

20060225015 - Various methods and apparatuses for flexible hierarchy grouping: Methods and apparatuses are described for incorporating floor planning information into a configuration process by generating a definition of a floor plan grouping of interconnect components during a front-end view design process for the interconnect. Further, a user is permitted to combine components from separate IP block representations of interconnects...

20060225016 - Method and apparatus for laying out cells in a semiconductor device: A method for generating layout data for macro cells in a core region of a semiconductor device. The method includes generating wiring margin-added macro cells, calculating the area of a maximum standard cell region by excluding the area of the wiring margin-added macro cells from the area of the core...

20060225017 - Integrated circuit layout design system, and method thereof, and program: There is provided an integrated circuit layout design method capable of performing LVS verification in an early stage of layout design. Placement and routing means provides wiring and outputs a layout in which short circuits are possibly left uncorrected. Short-circuit correcting means performs rewiring by using a newly defined tentative...

20060225018 - Automatic trace determination method and computer program thereof: An automatic trace determination apparatus comprises: first means that performs a first process sequentially for all intersections formed between tentative traces connecting between pads and corresponding vias, wherein the first process determines distances from an intersection formed between two tentative traces to the corresponding vias, respectively, and allows one of...

20060225019 - Assisting printed board design process: An apparatus, method, system, computer program and product, each capable of assisting a printed board design process. A predetermined combination including information regarding at least two of a board material, board sheet, and a printed circuit board is prepared before performing the printed board design process....

20060225021 - Automatic adjustment of optimization effort in configuring programmable devices: User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of...

20060225020 - Methods and apparatus for 3-d fpga design: Methods, apparatus, and systems are directed to an FPGA that includes a three-dimensional architecture having a component coupled to at least five components across two or more strata. In one embodiment, a FPGA includes a three dimensional switch that can be coupled to at least the five switches, wherein switches...

20060225022 - Method, apparatus and program for determining the relationship of correspondence between register transfer level description and behavioral description: The relationship of correspondence between the RTL description and the behavioral description is extracted with ease. A behavioral synthesis device analyzes how the scheduling, preparation of a control data flow graph and the sharing of arithmetic processing units and registers are carried out. The behavioral synthesis device then formulates a...

20060225025 - Dual phase shift photolithography masks for logic patterning: A pair of phase shift photolithography masks and a process for deriving them is described. In one embodiment, the invention includes deriving a complex electric field estimate for an intended pattern to be produced by phase shift photolithography masks, optimizing the complex electric field estimates, generating a first phase shift...

20060225023 - Method of adding fabrication monitors to integrated circuit chips: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions...

20060225024 - Modification of pixelated photolithography masks based on electric fields: Faster synthesis of photolithography mask modifications is described. In one embodiment, the invention includes synthesizing a first binary photolithography mask, developing perturbations to an estimated electric field generated by the first mask in use, and synthesizing a second binary photolithography mask by applying the perturbations to the first mask....