Data processing: design and analysis of circuit or semiconductor mask inventions 09/06

20060212837 - System and method for verifying a digital design using dynamic abstraction: A method for verifying a digital system design is provided. A first abstraction of a digital system design is performed to obtain an abstract model of the digital system design. One or more first steps of a multiple-step model checking process are performed using the abstract model, the multiple-step model...

20060212838 - System and apparatus for in-system programming: Embodiments of the present invention relate to machines that perform in-system programming of programmable devices that are attached to assembled printed circuit boards. In accordance with one aspect, multiple nonvolatile devices may be programmed in a single session at their normal maximum programming speeds. Different nonvolatile devices on a board...

20060212839 - Method and apparatus for modifying a layout to improve manufacturing robustness: One embodiment of the present invention provides a system that modifies a layout to improve manufacturing robustness. During operation, the system receives a layout. The system then selects a segment in the layout. Next, the system determines a target location in the proximity of the segment where the value of...

20060206839 - Method and system for evaluating design costs of an integrated circuit: Method and system for evaluating design costs of an integrated circuit are disclosed. The method includes choosing a design point for evaluation, dividing circuit specifications of the design point into at least two groups comprising a first group of specifications and a second group of specifications, computing a first set...

20060206844 - Crosstalk error control apparatus, method, and program: A crosstalk error controller includes a crosstalk analyzer for detecting a crosstalk error net in which a crosstalk error has occurred, a noise source detector for detecting noise source nets being noise sources to the crosstalk error net, and a reducing unit for lowering a signal level of a noise...

20060206841 - Method and apparatus for computing equivalent capacitance: One embodiment of the present invention provides a system that estimates the equivalent capacitances for a set of conductors within an electrical structure. During operation, the system constructs a Gaussian surface that encloses a first conductor, but does not contain any other conductor. The system then computes the equivalent capacitance...

20060206842 - Method for retiming in the presence of verification constraints: A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming...

20060206843 - Probabilistic noise analysis: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design...

20060206840 - Systems and methods for design verification using selectively enabled checkers: Systems and methods for performing design verification testing in which test cases are analyzed to determine the characteristics that will be verified in a module under test, and in which the identified characteristics are used to selectively enable checker modules needed to verify the characteristics implicated by the test cases,...

20060206846 - Apparatus and method for verification support, and computer product: A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus includes an input receiving unit that receives logical circuit description information on the object; a specifying unit that specifies at least two...

20060206845 - Hybrid linear wire model approach to tuning transistor widths of circuits with rc interconnect: A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes...

20060206847 - Layout optimizing method for a semiconductor device, manufacturing method of a photomask, a manufacturing method for a semiconductor device, and computer program product: A layout optimizing method for a semiconductor includes preparing design rule of a semiconductor device, circuit connection information or layout data of the semiconductor device, and circuit characteristic information of the semiconductor device, and optimizing a layout of the semiconductor device using the design rule, the circuit connection information or...

20060206848 - Method and apparatus for considering diagonal wiring in placement: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each...

20060206849 - System, method and program for designing a semiconductor integrated circuit using standard cells: A system for designing a semiconductor integrated circuit includes an extraction module for extracting through wiring tracks linearly passing through each of area priority cells and yield priority cells, a layout data generator for generating second layout data from first layout data by replacing the area priority cells with the...

20060206850 - Automated system for designing and developing field programmable gate arrays: An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined...

20060206851 - Determning lithographic parameters to optimise a process window: For determining best process variables (E, F, W) setting that provide optimum process window for a lithographic process for printing features having critical dimensions (CD) use is made of an overall performance characterizing parameter (Cpk) and of an analytical model, which describes CD data as a function of process parameters,...

20060206853 - Method of producing mask inspection data, method of manufacturing a photo mask and method of manufacturing a semiconductor device: There is disclosed a method of producing mask inspection data, including preparing design data of a semiconductor device preparing a lithography condition relevant to a lithography process for transferring a mask pattern formed on a photo mask onto a wafer, preparing a wafer processing condition relevant to wafer processing using...

20060206852 - System and method for designing semiconductor photomasks: A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor...

20060206854 - Assist feature placement using a process-sensitivity model: One embodiment of the present invention provides a system that determines an assist feature placement. During operation, the system receives an initial assist feature placement for a layout. Next, the system determines assist feature perturbations using the initial assist feature placement. An assist feature perturbation typically comprises a few simple...

20060200783 - Decoupling capacitance analysis method: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable...

20060200784 - Determining equivalent waveforms for distorted waveforms: An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first...

20060200785 - Method and apparatus for the design and analysis of digital circuits with time division multiplexing: Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of...

20060200786 - Static timing analysis and dynamic simulation for custom and asic designs: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient...

20060200787 - Method for tracing paths within a circuit: A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a transistor level data structure. Then, convert the transistor level data structure to a set of channel connect groups (CCG). A directed graph...

20060200788 - Method for describing and deploying design platform sets: A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design platform descriptions provide design information...

20060200789 - Connectivity verification of ic (integrated circuit) mask layout database versus ic schematic; lvs check, (lvs: ic layout versus ic schematic) via the internet method and computer software: This paper describes an EDA (Electronic Data Automation) method and computer software invention for connectivity verification of IC mask Layout database versus IC Schematic; LVS Check (LVS: IC Layout versus IC Schematic) over the internet. The technique takes advantage of a unique algorithm to check the mask layout database connectivity,...

20060200790 - Model-based sraf insertion: A system for producing mask layout data retrieves target layout data defining a pattern of features, or portion thereof and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more subresolution assist features (SRAFs) is then defined to approximate...

20060200783 - Decoupling capacitance analysis method: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable...

20060200784 - Determining equivalent waveforms for distorted waveforms: An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first...

20060200785 - Method and apparatus for the design and analysis of digital circuits with time division multiplexing: Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of...

20060200786 - Static timing analysis and dynamic simulation for custom and asic designs: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient...

20060200787 - Method for tracing paths within a circuit: A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a transistor level data structure. Then, convert the transistor level data structure to a set of channel connect groups (CCG). A directed graph...

20060200788 - Method for describing and deploying design platform sets: A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design platform descriptions provide design information...

20060200789 - Connectivity verification of ic (integrated circuit) mask layout database versus ic schematic; lvs check, (lvs: ic layout versus ic schematic) via the internet method and computer software: This paper describes an EDA (Electronic Data Automation) method and computer software invention for connectivity verification of IC mask Layout database versus IC Schematic; LVS Check (LVS: IC Layout versus IC Schematic) over the internet. The technique takes advantage of a unique algorithm to check the mask layout database connectivity,...

20060200790 - Model-based sraf insertion: A system for producing mask layout data retrieves target layout data defining a pattern of features, or portion thereof and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more subresolution assist features (SRAFs) is then defined to approximate...