Data processing: design and analysis of circuit or semiconductor mask inventions 08/06

20060195803 - Method and apparatus for computing feature density of a chip layout: One embodiment of the present invention provides a system that computes feature density for a number of areas within a layout by moving a window across the layout, which allows the system to identify areas in the layout that violate a design rule. During operation, the system receives a layout....

20060195804 - Method and apparatus for configurable circuitry: A method and apparatus for configurable circuitry have been disclosed....

20060195806 - Method and apparatus for quantifying the timing error induced by an impedance variation of a signal path: In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the signals having different pulsewidths. After driving each signal, the signal is sampled at or...

20060195805 - Method and apparatus for quantifying the timing error induced by crosstalk between signal paths: In one embodiment, each of a plurality of stimulus signals is sequentially driven onto a number of stimulus signal paths. Each of the plurality of stimulus signals has a trigger edge. As each stimulus signal is driven onto the number of stimulus signal paths, a victim signal having a sensor...

20060195807 - Method and system for evaluating timing in an integated circuit: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the...

20060195808 - Method for correcting the optical proximity effect: A respectively separate optical proximity correction (OPC) process model and method is formed for selected structure classes or partial patterns of a layout is disclosed. For this purpose, the corresponding structure elements are treated separately as early as during the modeling. During the modeling and also for OPC correction, the...

20060195809 - Circuit layout methodology: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying...

20060195810 - Aligned logic cell grid and interconnect routing architecture: A method (150) for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell (12) is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch (24) of the interconnect layout and a transistor...

20060195811 - System and method for reducing design cycle time for designing input/output cells: I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell...

20060195812 - Designing system and method for designing a system lsi: A method for designing a system LSI includes the steps of dividing an algorithmic description (D1) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior synthesis to create an RTL description ((D5) and a simulation description (D6), examining the circuit scale of the system...

20060195813 - Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit: Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an integrated circuit. When the connectivity of elements of the functional block need to be changed later, the dummy stacks enable masks, which would otherwise need to be...

20060195814 - System and method for using mpw integration service on demand: A system for multi-project wafer service is provided. The system contains integrator and designer interfaces, an account managing device, a mask tooling information processor, a mask database checking device, and a mask tooling information convertor. The integrator and the designer interfaces provide first and second users with access to the...

20060195815 - Exposure data generator and method thereof: A plurality of patterns placed within an target region are classified by their placement positions, a pattern adjacent to each side of each pattern is searched for by using the classification results, and adjacent pattern information is obtained. Next, a back-scattering intensity at an evaluation point on a pattern is...

20060190846 - Building metal pillars in a chip for structure support: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip...

20060190847 - Ic compaction system: An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding...

20060190848 - Low power consumption designing method of semiconductor integrated circuit: In a standard cell synthesizing step 101, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance name contained in the net list; in a simulation step 103, an operation simulation written by the RTL...

20060190850 - Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask: A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns. Subsequently, the circuit pattern of the circuit design is iteratively decomposed into corresponding basic patterns in order to classify those parts...

20060190849 - Micro computer and method of optimizing microcomputer: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency...

20060190851 - Asynchronous circuit design tool and computer program product: It is the object of the present invention to provide asynchronous circuit design tools for those engineers who are versed in standard hardware description languages (HDLs), which is widely used in industry mainly for synchronous circuit design, to design asynchronous circuits with relative ease. To accomplish the object, the asynchronous...

20060190852 - Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives...

20060190862 - Event driven switch level simulation method and simulator: A method for simulating an integrated circuit includes performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement, identifying a weak signal node based on the simulation result, and performing a...

20060190855 - Identifying high e-field structures: Power plane structures that may generate high E-fields can be identified and flagged for additional review by representing a boundary of the structures as a function, and evaluating the second derivative of that function. The result can be compared against a threshold value to determine if further review of the...

20060190861 - Method and apparatus for evaluating coverage of circuit, and computer product: An apparatus for evaluating coverage includes a determining unit that checks description rules when a receiving unit receives hardware description data. If the hardware description data matches a first or a second description rule, an optimizing unit performs a logic optimization by rewriting of the hardware description data according to...

20060190856 - Method and apparatus to generate circuit energy models with clock gating: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power...

20060190860 - Method and system for debugging using replicated logic and trigger logic: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of...

20060190853 - Method for estimating a frequency-based ramptime limit: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal...

20060190863 - Method for improving accuracy of mosfet models used in circuit simulation integrated circuits: Disclosed is a method of modeling submicron MOSFETs for the purpose of circuit simulation. This invention is capable of accurately predicting performance of a MOSFET with complex geometry closely approximating the actual geometry of a device manufactured as part of an integrated circuit. Actual device geometry is predicted using physical...

20060190854 - Method for incorporating pattern dependent effects in circuit simulations: Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of...

20060190857 - Methods, systems and media for functional simulation of noise and distortion on an i/o bus: Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the...

20060190859 - Negative bias temperature instability modeling: A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in...

20060190858 - System and method for accurately modeling an asynchronous interface using expanded logic elements: A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration...

20060190877 - Decoupling capacitance analysis method: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable...

20060190869 - Design verification using sequential and combinational transformations: System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded...

20060190864 - Efficient modeling of embedded memories in bounded memory checking: A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is...

20060190873 - Exploiting suspected redundancy for enhanced design verification: A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of an XOR gate are sourced by the representative gate...

20060190870 - Latch modeling technique for formal verification: A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using...

20060190874 - Method and system for formal unidirectional bus verification: A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal...

20060190868 - Method and system for optimized handling of constraints during symbolic simulation: A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more...

20060190867 - Method for reconfiguration of random biases in a synthesized design without recompilation: A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion...

20060190871 - Methods, systems and media for managing functional verification of a parameterizable design: Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the...

20060190875 - Pattern extracting system, method for extracting measuring points, method for extracting patterns, and computer program product for extracting patterns: A pattern extracting system includes a sampler configured to sample test candidate patterns from a circuit pattern, based on a lithographic process tolerance, a space classification module configured to classify the test candidate patterns into space distance groups depending on a space distance to an adjacent pattern, a density classification...

20060190865 - Quantified boolean formula (qbf) solver: Quantified Boolean formula (QBF) techniques are used in determining QBF satisfiability. A QBF is broken into component parts that are analyzable by a satisfiability (SAT) solver. Each component is then independently, and perhaps in parallel, analyzed for satisfiability. If a component is unsatisfiable, then it is determined that the QBF...

20060190866 - Resistance extraction for hierarchical circuit artwork: In one embodiment, a method is disclosed for extracting resistance from hierarchical circuit artwork having parent and child circuit blocks. In accordance with the method, and for each child block, at least one portion of signal trace artwork to which a parent circuit block may connect is identified; the identified...

20060190876 - Semiconductor device design system and method, and software product for the same: A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured...

20060190872 - System and method for signal integrity testing of electronic circuits: A system and method are disclosed for measuring signal crosstalk in an electronic circuit device or Integrated Circuit (IC) device, correlating the results with modeled information, and accurately identifying one or more levels of coupling noise in the device. For example, a system is disclosed that provides data on levels...

20060190884 - Apparatus and method for analyzing post-layout timing critical paths: A critical path detecting unit for detecting critical paths for a design in which cells are placed on an integrated circuit and information concerning timing constraints. A representative-critical-path extracting unit extracts a representative critical path by having one critical path represent critical paths which share more intervals than a certain...

20060190879 - Frequency dependent timing margin: A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the integrated circuit timing design. The circuit simulator path delays are plotted in a first plot versus a percentage difference...

20060190878 - Method and circuit arrangement for determining power supply noise: The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used...

20060190881 - Method for estimating propagation noise based on effective capacitance in an integrated circuit chip: A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring...

20060190885 - Method of displaying delay: There is provided a method of displaying calculated delay which can easily grasp the state of the entire logical block and acquire the detailed information on delay violation paths. A display screen has a first window displaying a path delay list of a combination of a source and a sink...

20060190886 - Optimizing ic clock structures by minimizing clock uncertainty: A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting...

20060190880 - Output buffer with slew rate control utilizing an inverse process dependent current reference: An output driver circuit that provides more constant slew rates in the presence of process, voltage, or temperature variations that affect performance. An open ended (no feedback) solution is utilized that provides more constant slew rates in spite of PVT variations. A first performance dependent current and a reference current...

20060190882 - System and method for generating assertions using waveforms: Systems and methods for generating a Hardware Design Language (HDL) assertion from a waveform diagram are disclosed. One method comprises: identifying a timing relationship between first and second signals in the diagram; and generating an HDL assertion corresponding to the relationship. The relationship comprises a portion of the first signal,...

20060190883 - System and method for unfolding/replicating logic paths to facilitate propagation delay modeling: A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source....

20060190888 - Apparatus and method for electronic device design: A system and method is disclosed for computer-assisted transistor design. A new transistor design can be generated based on characteristics of an existing transistor. The system for transistor design receives a first set of parameters for an existing transistor design that are functions of a first geometry that is descriptive...

20060190889 - Circuit floorplanning and placement by look-ahead enabled recursive partitioning: Placement or floorplanning of an integrated circuit is performed by constructing legal layouts at every level of a hierarchy of subsets of modules representing the integrated circuit, by scalably incorporating legalization into each level of the hierarchy, so that satisfiability of constraints is explicitly enforced at every level, in order...

20060190887 - Method for realizing circuit layout: A method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contacts/vias in the layout of each cell. While realizing the layout of an integrated...

20060190890 - Cell instance generating method: By a hierarchical structure developing process at Step S1, layout pattern data possessing hierarchical structure is developed to flat layout pattern data. An optimizing process at Step S2 generates optimized flat layout pattern data accompanying a new inserted cell. By a hierarchical structure cell instance allotting process at Step S3,...

20060190894 - Area-efficient distributed device structure for integrated voltage regulators: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas...

20060190893 - Logic cell layout architecture with shared boundary: Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method (200) for designing a logic cell library having a shared boundary between at least two cells (12,32) is disclosed for increasing packing density and limiting the occurrence of stress between...

20060190895 - Method and program for designing semiconductor device: A method for designing a semiconductor device by using a computer, includes steps (a) to (b). The step (a) is the step of placing a power line and a ground line along a first direction. The step (b) is the step of placing a capacity cell which includes a bypass...

20060190891 - Method for placing probing pad and computer readable recording medium for storing program thereof: A method for placing probing pad and a computer readable recording medium for storing a program thereof are provided. The method is suitable for placing the probing pads in an integrated circuit (IC). Wherein, appropriate grid spacing is determined and a plurality of grids with fixed grid spacing is generated....

20060190892 - System and method for automatic insertion of on-chip decoupling capacitors: A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of...

20060190896 - Method for reducing the size and nanowire length used in nanowire crossbars without reducing the number of nanowire junctions: Various embodiments of the present invention provide methods for designing multilayer nanowire crossbars that are functionally equivalent to two-layer nanowire-crossbar designs. Given a two-layer nanowire-crossbar design having two or more columns of microregions, in certain embodiments, the method conceptually folds the two-layer nanowire crossbar between columns of microregions. The folded...

20060190897 - Methods of routing an integrated circuit design: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing...

20060190898 - Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing: A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal...

20060190901 - Method of buffer insertion to achieve pin specific delays: A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total...

20060190899 - Method of clock tree distribution generation by determining allowed placement regions for clocked elements: A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set...

20060190902 - Method, apparatus and program for automatically routing semiconductor integrated circuit: Disclosed is an apparatus for performing automatic routing of a semiconductor integrated circuit, including an automatic routing and search processing unit for outputting post-routing layout data upon receiving inputs of post-routing layout data, circuit data and differential-signal information. The automatic routing and search processing unit includes: a differential-signal routing setting...

20060190900 - Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout: A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least...

20060190903 - Asics having programmable bypass of design faults: A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to...

20060190904 - Common interface framework for developing field programmable device based applications independent of a target circuit board: A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD). According to one embodiment, a field programmable device (FPD) comprises at least one hardware design language (HDL)...

20060190908 - Coding of fpga and standard cell logic in a tiling structure: A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types,...

20060190906 - Efficient method for mapping a logic design on field programmable gate arrays: An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing...

20060190909 - Method for designing a system lsi: A method for designing a system LSI includes the step of defining, for each of instructions of the processor, a behavior function description and an instruction description specifying the behavior function description, and the step of synthesizing the instructions by behavior synthesis to define the processor. The behavior function description...

20060190910 - Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs: A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of...

20060190907 - Methods and apparatus for implementing parameterizable processors and peripherals: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically...

20060190905 - System for designing re-programmable digital hardware platforms: A digital design system and method are provided for re-programmable hardware platforms, such as field programmable gate arrays (FPGAs) and other re-programmable system designs. The design system and method bridge the gap between what has previously been a development and prototyping platform used during the design phase of an electronic...

20060190915 - Machine specific and machine group correction of masks based on machine subsystem performance parameters: Determining corrections for a mask used in photolithography includes assembling characteristics of a mask design and an as-drawn specification into a virtual reticle. Assembling characteristics of machine subsystem parameters into a virtual wafer. Emulating machine performance on the virtual reticle and virtual wafer and accumulating the results in an updated...

20060190913 - Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one...

20060190912 - Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one...

20060190914 - Method and apparatus for identifying a problem edge in a mask layout using an edge-detecting process-sensitivity model: One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or...

20060190911 - Translation generation for a mask pattern: Generation of one or more translations is described. The generated translations may be applied to a mask pattern so that the pattern may be moved to cover one or more mask defects in part or in totality....

20060190921 - Manufacturing method of semiconductor device: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second...

20060190919 - Method of locating sub-resolution assist feature(s): A method of operating a computing system to determine reticle data. The reticle data is for completing a reticle for use in projecting an image to a semiconductor wafer. The method receives circuit design layer data comprising a desired circuit layer layout, and the layout comprises a plurality of lines....

20060190920 - Optical proximity correction performed with respect to limited area: A method of performing optical proximity effect correction includes defining a partial area of an entire area of a mask pattern, the mask pattern including a real pattern and a dummy pattern, and performing optical proximity effect correction only with respect to the partial area....

20060190916 - Semiconductor substrate processing method and apparatus: According to one aspect of the invention, a semiconductor substrate processing apparatus and a method for processing semiconductor substrates are provided. The method may include providing a semiconductor substrate having a surface and a plurality of features on the surface, each feature being positioned on the surface at a first...

20060190917 - System and process for manufacturing application specific printable circuits (aspc's) and other custom electronic devices: A system and process for manufacturing custom printed circuit boards on pre-provided substrates, wherein the substrate can be pre-provided with electronic devices. The electronic devices can be pre-provided on the substrate by direct printing, or in a more conventional manner, such as by standard integrated circuit technologies, in many different...

20060190918 - System and process for manufacturing custom electronics by combining traditional electronics with printable electronics: A system and process for manufacturing custom printed circuit boards on pre-provided substrates, wherein the substrate is pre-provided with standard integrated circuits. The standard integrated circuits are pre-provided on the substrate in a conventional manner, such as by standard integrated circuit technologies, in many different packing technologies. The user designs...

20060184903 - Logical equivalence verifying device, logical equivalence verifying method, and logical equivalence verifying program: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs...

20060184904 - Analyzing substrate noise: In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation...

20060184905 - Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip: A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal...

20060184906 - Method and device for designing semiconductor integrated circuit: A method for designing a semiconductor integrated circuit includes steps of (a) to (e). The step (a) is a step of placing a plurality of elements based on circuit data including data of the plurality of elements to be placed on a semiconductor integrated circuit. The step (b) is a...

20060184907 - Extracting/reflecting method and hierarchical circuit information with physical information and circuit designing method using the same: By reflecting physical information extracted from layout information on hierarchical circuit information while maintaining its hierarchical structure and creating the hierarchical circuit information with the physical information, to reflect the physical information with its accuracy kept on the hierarchical circuit information, thereby realizing high speed of circuit simulation and reduction...

20060184908 - Method and program for generating layout data of a semiconductor integrated circuit and method for manufacturing a semiconductor integrated circuit with optical proximity correction: A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating...

20060184909 - Semiconductor integrated circuit routing method and recording medium which stores routing software: According to the present invention, there is provided a method of routing a semiconductor integrated circuit by using a routing apparatus having an input unit, a storage unit, and an arithmetic unit, comprising: receiving, by the input unit, for respective terminals of a plurality of elements contained in the semiconductor...

20060184910 - Reconfigurable interconnect for use in software-defined radio systems: A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for each of the P possible configuration, determining a list of required interconnections...

20060184911 - Labeling method and software utilizing the same, and pcb and electronic device utilizing the same: A labeling method for a printed circuit board comprising a first layout face and a second layout face opposite to the first layout face. The labeling method comprises defining a track region in the first layout face, defining a first mapping region mapped by the track region on the second...

20060184912 - Automatic design apparatus for semiconductor integrated circuits, method for automatically designing semiconductor integrated circuits, and computer program product for executing an application for an automatic design apparatus for semiconductor integrate: An automatic design apparatus for semiconductor integrated circuits including a first acquisition module configured to acquire a first function description describing an arrangement of a plurality of data processors, and a second function description describing an arrangement of a plurality of connection selectors for switching the connection among the data...