Data processing: design and analysis of circuit or semiconductor mask inventions 07/06

20060168551 - Integrated circuit having a multi-layer structure and design method thereof: An integrated circuit has a multi-layer wiring structure formed on a substrate. The integrated circuit comprises wiring patterns provided to multiple wiring layers so as to extend as signal paths in generally the same direction in a manner in which the images of the wiring patterns projected onto the substrate...

20060168552 - Substrate mapping: A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites,...

20060161873 - Method for designing integrated circuit package and method for manufacturing same: A new IC package 12 is designed as follows. That is, a circuit block 2 is omitted from an existing IC package 11 including a package 11a having a circuit block 1 and the circuit block 2 which are connected to a plurality of terminals including high-frequency terminals, but the...

20060161874 - Printed circuit wiring board designing support device, printed circuit board designing method, and its program: A printed circuit wiring board designing support device includes a layout data receiving section receiving printed circuit board layout data through an input/output section, a section for extracting structures of power supply/ground planes, a via hole extracting section for extracting a via hole interconnecting the wirings extending over power supply/ground...

20060161875 - Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method: There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including...

20060161876 - Array-based architecture for molecular electronics: An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array...

20060161877 - Device and method for data-processing: A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions...

20060156260 - Behavioral transformations for hardware synthesis and code optimization based on taylor expansion diagrams: A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated with any suitable architectural synthesis system. It can also be built into a compiler tool for general purpose processor or into a specific...

20060156261 - Design verification technique: A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is in impact checker to determine the impact of portions of the design on the operation of the design....

20060156264 - Method and apparatus for supporting verification of system, and computer product: In a verification support apparatus, an input unit accepts input of an unverified specification description representing an unverified design object constituted by unverified model elements. A searching unit searches, from verified specification descriptions representing verified design objects constituted by verified model elements, a verified specification description identical or similar to...

20060156262 - Method and apparatus for supporting verification, and computer product: A verification supporting apparatus includes an acquiring unit that acquires a first verification-item list for a verification target, a functional specification of the verification target, and a sequential specification of the verification target; a keyword extracting unit that extracts a keyword about the verification target from the first verification-item list;...

20060156263 - Method for designing semiconductor device and method for evaluating reliability thereof: A semiconductor device 100 has a configuration having a via 124 formed on a first interconnect 112. A method for designing the semiconductor device 100 includes: calculating an anticipated value xopen of a dimension of a growing region of a void 150 expanding in a stress induced voiding (SIV)-ensured time...

20060156265 - Method and system to redistribute white space for minimizing wire length: Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined optimal wire length. In accordance with the...

20060156266 - Probabilistic congestion prediction with partial blockages: A method of estimating routing congestion between pins in a net of an integrated circuit design, by establishing one or more potential routes between the pins which pass through buckets in the net, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in...

20060156267 - Recording medium recording a wiring method: It is determined whether a short-run rule can be adapted into a position, where a via cell is parallel and adjacent to a portion of wiring or another via cell. The via cell and the portion of the wiring is arrayed at the smallest space in the wiring. When determined...

20060156268 - Circuit design platform: The circuit design platform of this invention comprises: a portal provided with a network platform to install functional modules and to allow users to utilize said functional modules after login; a circuit design tool module to connect at least one circuit design software and to generate a circuit design descriptive...

20060156269 - Selecting data to verify in hardware device model simulation test generation: Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands...

20060156270 - Method and apparatus for correcting 3d mask effects: One embodiment of the present invention provides a system that improves lithography performance by correcting for 3D mask effects. During operation the system receives a mask layout that contains etched regions, called shifters, which can have a phase shift relative to other regions. Next, the system chooses a shifter in...

20060150126 - Hardware verification scripting: Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data...

20060150127 - Method of achieving timing closure in digital integrated circuits by optimizing individual macros: Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than...

20060150128 - Method of fabricating and integrated circuit to improve soft error performance: The present invention provides, in one aspect, a method of designing an integrated circuit 500. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit 500 by locating a structure 526, 528 relative to a node 516 of the integrated circuit 500 to reduce a...

20060150129 - Stochastic analysis process optimization for integrated circuit design and manufacture: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a...

20060150130 - Integrated circuit yield enhancement using voronoi diagrams: A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said...

20060150132 - Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit: The present invention provides a method and a system for designing an integrated circuit comprising a plurality of elements. The method includes obtaining a lithography-simulated layout corresponding to at least one element. The lithography-simulated layout accounts for lithography effects on the element. The method further includes determination of an equivalent...

20060150131 - Method for generating design rules for a lithographic mask design that includes long range flare effects: A method is described for computing distance based and pattern density based design rules for the mask layout design of a VLSI chip so that the design satisfying the above design rules when manufactured on a wafer do not violate the specified tolerance on the critical dimensions (CD). The design...

20060150133 - Integrated circuit (ic) chip design method, program product and system: A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the...

20060150134 - Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media: In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a...

20060150135 - Circuit information generating apparatus and circuit information generating method: Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure...

20060150136 - Systems and methods for designing integrated circuits: Systems and methods for designing integrated circuits (ICs) are provided. A representative method includes: providing a netlist; determining components required to implement test of at least a portion of the integrated circuit defined by the netlist; provide a revised netlist including the components determined; and performing a place and route...

20060150137 - Three dimensional integrated circuits: A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer....

20060150138 - Method of creating optimized tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the same: Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the...

20060150139 - Circuit element function matching despite auto-generated dummy shapes: Methods, systems, program products are disclosed that control placement of dummy shapes about sensitive circuit elements such that the dummy shapes are at least substantially similar for each circuit element even though the dummy shapes are auto-generated. In one embodiment, the invention includes providing dummy shape pattern pitch information to...