Data processing: design and analysis of circuit or semiconductor mask inventions 06/06

20060143581 - Method and device for electronic circuit designing, and computer product: Noise related to a part of electronic circuits that are to be designed is computed. If the computed noise exceeds a limiting value, parameters of the electronic circuits are modified by using a predetermined method (simple noise check) so that the noise is less than or equal to the limiting...

20060143582 - Generating testcases based on numbers of testcases previously generated: A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases...

20060143583 - Methods and apparatus to maintain and utilize mobile power profile information: A controller in PSE (Power Sourcing Equipment) controls how to provision uninterruptible power through corresponding data ports (and cables) of the PSE to network devices. For example, the controller receives power profile information associated with the network devices indicating how to provision power to the network devices during a power...

20060143584 - Method and device of analyzing crosstalk effects in an electronic device: For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model description allowing for simulating the dynamic response behaviour at an output of the victim net with respect to...

20060143585 - Method of designing a semiconductor integrated circuit: In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power...

20060143586 - Synthesis strategies based on the appropriate use of inductance effects: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the...

20060143587 - Method and device for synthesising an electrical architecture: The invention relates to a method of synthesising an electrical or electronic architecture of at least one part of a product comprising electrical wires and electrical and electronic components, such as sensors, actuators and computing devices. The inventive method comprises the following steps: the geometry of the product, which is...

20060143588 - Video processing architecture definition by function graph methodology: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource...

20060143590 - Method and apparatus for determining a proximity correction using a visible area model: One embodiment of the present invention provides a system that determines a proximity correction for an integrated circuit layout. During operation, the system receives a layout. Next, the system receives an evaluation point within the layout. The system then determines a visible area associated with the evaluation point. Next, the...

20060143589 - Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design: A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based...

20060136848 - Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which...

20060136849 - Selectively reducing the number of cell evaluations in a hardware simulation: An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time....

20060136851 - Method for the generation of static noise check data: In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and DA, when a plurality of cores, comprising the same sub-chips, are present, the static noise check data for the whole chip is...

20060136850 - Method of parasitic extraction from a previously calculated capacitance solution: A method and computer program product for parasitic extraction from a previously calculated capacitance solution include steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated...

20060136852 - Method and apparatus for mixing static logic with domino logic: An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits for the clock in the domino...

20060136853 - Timing skew measurement system: An improved timing skew measurement system includes a selector receiving a plurality of input signals whose relative skew is to be measured, a selection controller connected to the select inputs of the selector for selecting one of the input signals and a sequential logic element having a first input connected...

20060136854 - Method for placement of pipeline latches: An integrated chip die comprises a data source connected to a data sink by way of a signal path wherein one or more pipeline latches are automatically inserted into the signal path at predetermined intervals when the length of the signal path is greater than a predetermined maximum signal propagation...

20060136855 - Method of implementing an engineering change order in an integrated circuit design by windows: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated...

20060136856 - Unit-based layout system for passive ic devices: A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnected instances of a device unit,...

20060136857 - System and method for designing electrical trace lengths on printed circuit boards between impedance discontinuities: Described is a system and method of designing a length of an electrical trace used to implement a point-to-point serial link for conveying a digital signal between a transmitter and a receiver. A trace segment of the electrical trace is identified. The trace segment has a first endpoint determined by...

20060136858 - Utilizing fuses to store control parameters for external system components: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused...

20060136860 - Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies: Methods and apparatus are described that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single master design environment. The master design environment is achieved, in part, by the creation of a centralized master database that comprises device models belonging to more...

20060136859 - Method to unate a design for improved synthesizable domino logic flow: A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthesized and a set of...

20060136861 - Layout modification using multilayer-based constraints: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces...

20060136862 - Pattern data verification method, pattern data creation method, exposure mask manufacturing method, semiconductor device manufacturing method, and computer program product: A pattern data verification method includes preparing exposure data related to a circuit pattern to be formed on a substrate, calculating a characteristic of an image of an exposure pattern on a resist film to be applied on the substrate, the exposure pattern corresponding to the exposure data, calculating a...

20060129952 - Method for incremental design reduction via iterative overapproximation and re-encoding strategies: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design...

20060129953 - Method for verifying and representing hardware by decomposition and partitioning: A system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions. Decision diagrams are built for the digital circuit or system and pseudo-variables are introduced at decomposition points to reduce diagram size. Pseudo-variables...

20060129957 - Method and computer program product for register transfer level power estimation in chip design: A method for register transfer level power estimation in chip design includes the steps of: (A) parsing all possible condition branches of conditional statements in a register transfer level code, and establishing power modes inducible by each of the possible condition branches; (B) selecting a plurality of representative input vector...

20060129956 - Method for generating hints for program analysis: The present invention provides a method, apparatus and article of manufacture for generating hints for use when performing reach-ability analysis of a program such as programmatic representations of hardware circuits. The hints are generated from external inputs to the program which are used in conditional statements of the program. Further...

20060129954 - Method, apparatus, and computer program product for rtl power sequencing simulation of voltage islands: A method, apparatus and computer program product are provided for implementing RTL power sequencing simulation of voltage islands for application specific integrated circuit (ASIC) designs. RTL sequential state saving elements in a voltage island hierarchy are identified. A state is invalidated for each identified RTL sequential state saving element during...

20060129955 - Printed circuit board development cycle using probe location automation and bead probe technology: Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probes insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in...

20060129959 - Abstraction refinement using controllability and cooperativeness analysis: One embodiment of the present invention provides a system that refines an abstract model. Note that abstraction refinement is commonly used in formal property verification. During operation, the system receives an abstract model which is a subset of a logic design which can be represented using a set of variables...

20060129958 - Method for verification using reachability overapproximation: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is...

20060129960 - Layout-driven, area-constrained design optimization: In one embodiment, a method for layout-driven, area-constrained design optimization includes accessing a design and a layout of the design. The design includes one or more gates and one or more nets coupling the gates to each other. The layout includes blocks that partition a chip area of the design....

20060129961 - Skew reduction for generated clocks: There is disclosed systems and processes for optimizing circuit descriptions by reducing clock skew, re-organizing and/or converting gated and generated clock circuits, and reconnecting clock nets and other related nets. A transformed circuit design may be produced from an initial circuit design and having a reduced number of secondary clocks...

20060129962 - Cell builder for different layer stacks: A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for...

20060129963 - Floorplan visualization method: A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates...

20060129964 - Net list generating method and layout designing method of semiconductor integrated circuit: A placement 103 of a macrocell is applied to a net list 102 formed by the logic synthesis by using the automatic layout tool, physical information of the macrocell is extracted in a physical information extracting step 104, and a net list 106 including the physical information is generated by...

20060129965 - Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications: A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a...

20060129966 - Opc edge correction based on a smoothed mask design: A method and system is provided for performing edge correction on a mask design. Aspects of the invention include initially fragmenting boundaries of the mask design for optical proximity correction, whereby edge segments of the boundaries are moved by a distance value; interpreting the moved edge segments by defining a...

20060129967 - System, method and program for generating mask data, exposure mask and semiconductor device in consideration of optical proximity effects: A system for generating mask data includes an extracting module extracting a block necessary to correct process proximity effects as a wide correction area from a plurality of blocks by comparing parameter, a wide correction data generator generating wide correction data to make the correction applied to the wide correction...

20060129968 - Effective proximity effect correction methodology: Proximity effect correction has become a necessary step in the fabrication of integrated circuit in order to improve the pattern fidelity of current lithography processes. Current methodology is limited by data volume increase and correction inaccuracy due to extrapolation of the correction. The invention describes a methodology based on the...

20060117275 - Asynchronous communication network for multi-element integrated circuit system: Embodiments of the invention include a system for communication within an integrated circuit. Hardware object nodes are connected to one another through a system of physical channels. Messages are sent from one node to another over the channels. The messages can be asynchronous in nature, as well as time-insensitive. The...

20060117274 - Behavior processor system and method: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software....

20060117276 - Semiconductor integrated circuit designing method and program: An object of the present invention is to prevent occurrence of an unconnected terminal during arrangement and connection, shorten the time required for automatic arrangement and connection, improve a yield, and improve the properties of a cell. A recognized object-of-wiring thinning cell (minimum-rule cell) is temporarily replaced with a preferred-rule...

20060117277 - Circuit design support methods and systems: A method for circuit design support. A netlist file is received. A first 4-terminal device is acquired from the netlist. A second 4-terminal device with the same specifications as the first 4-terminal device is acquired. A first determination is performed to determine whether all control terminals of the first device...

20060117280 - Digital circuit layout techniques using binary decision diagram for identification of input equivalence: A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the regions are decomposed into a directed graph of the logic functions. A swap structure is created in accordance with...

20060117279 - Method for storing multiple levels of design data in a common database: An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The...

20060117283 - Integrated circuit verification method, verification apparatus, and verification program: A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical information on routing of the input/output buffer into a library of the input/output buffer and verifies a placement of the input/output buffer...

20060117282 - Method that allows flexible evaluation of power-gated circuits: A method and a design automation tool are provided for use in conjunction with designing logic circuits that implement virtual power signals. The method includes providing in a model for each virtual power signal an attribute that distinguishes the virtual power signal from both a logic signal and a power...

20060117281 - Verification of rram tiling netlist: The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean function 0 is assigned to all ground...

20060117287 - Method and device for checking a circuit for adherence to set-up and hold times: A method and a device for checking a circuit path of a circuit for adherence to set-up and hold times are provided. A timing behavior of the circuit path is designated as being correct if at least one pair of set-up and hold times from predefined set-up and hold times...

20060117286 - Method for correcting timing error when designing semiconductor integrated circuit: A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of...

20060117285 - Method for designing semiconductor integrated circuit, semiconductor integrated circuit and program for designing same: In lower hierarchy design in which a plurality of circuit blocks are independently designed, a reset adjustment circuit propagating deactivation transition of a reset signal to flip-flops in synchronization with a clock signal is inserted immediately after a reset input pin in each circuit block, and timing adjustment using the...

20060117284 - Rram memory timing learning tool: A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database....

20060117288 - Lsi physical designing method, program, and apparatus: In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit forms a floor plan for arranging a plurality of circuit blocks including a non-rectangular area into the chip....

20060117289 - Wiring method, program, and apparatus: A problem is efficiently solved by giving a proper adjacent spacing condition only to nets having such a problem that a wiring delay and crosstalks are caused. A wiring processing unit executes a wiring process by giving a first adjacent spacing condition that does not become a wiring violation on...

20060117290 - Wiring method, program, and apparatus: When one net is wired, by restricting a wiring area, the net is efficiently wired in a short time. A wiring area setting unit sets a maximum rectangle including a set of terminals constructing the net into a wiring area. A wiring deciding unit decides the wiring between the nets...

20060117291 - Layout of network using parallel and series elements: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing...

20060117292 - Automatic recognition of geometric points in a target ic design for opc mask quality calculation: A method and system is provided for automatically recognizing geometric points of features in a target design for OPC mask quality calculation. For each feature in the target design, x, y points comprising the feature are traversed and each neighboring pair of points is connected to define respective segments, wherein...

20060117293 - Method for designing an overlay mark: Precision in scatterometry measurements is improved by designing the reticle, or the target grating formed by the reticle, for greater overlay measurement sensitivity. Parameters of the structure and material of the substrate are first determined. These parameters may include the material composition, thickness, and sidewall angles of the sample substrate....