Data processing: design and analysis of circuit or semiconductor mask inventions 05/06

20060112355 - Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that...

20060112356 - System and method for converting a flat netlist into a hierarchical netlist: System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing...

20060112357 - Sensitivity-current-based model for equivalent waveform propagation in the presence of noise for static timing analysis: A system and a method are disclosed for modeling an electronic element. Sensitivity of an output current to an input voltage without noise is determined. Output current is calculated in the event noise is present at an input using sensitivity. An output voltage is derived from the output current. The...

20060112358 - System and method for designing a delayer emulation model: A system for designing a delayer emulation model (1) includes a delayer emulation model generating apparatus (2). The delay emulation model generating apparatus includes: a delay circuit defining module (20) for defining delay parameters of a delay circuit, and generating the delay circuit; a delay signal setting module (21) for...

20060112360 - Layout design method for semiconductor integrated circuits: A method of designing a semiconductor integrated circuit creates a net list with cells from a low-threshold-voltage cell library, then arbitrarily replaces some or all of the cells with cells from a high-threshold-voltage cell library. A timing analysis is performed, and if necessary, the net list is further modified by...

20060112359 - Pessimism reduction in crosstalk noise aware static timing analysis: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing...

20060112362 - Design method, design apparatus, and computer program for semiconductor integrated circuit: The relative placement orders of cells with respect to circuit diagram information received are automatically determined, and the cells are automatically placed in relative positional relationships according to the placement orders given to the circuit diagram information...

20060112361 - Method of selecting cells in logic restructuring: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set....

20060112363 - Multiple buffer insertion in global routing: Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit...

20060112364 - Techniqes for super fast buffer insertion: A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from...

20060112365 - Design support apparatus, design support program and design support method for supporting design of semiconductor integrated circuit: A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output...

20060112366 - Method and system for optimized automated ic package pin routing: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide an IC package routing solution. The global topological solution is used in conjunction with necessary design parameters to determine the...

20060107239 - Standard cell library having cell drive strengths selected according to delay: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional...

20060107240 - Logic injection: A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data...

20060107241 - Evaluation device and circuit design method used for the same: There is provided an evaluation apparatus capable of measuring the I-V characteristic in the MOSFET AC operation with a high accuracy. There are also provided a circuit design method and a circuit design system used for the evaluation apparatus. In the evaluation apparatus (1), an AC input signal superimposing circuit...

20060107242 - Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment: A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature...

20060107244 - Method for designing semiconductor intgrated circuit and system for designing the same: A total random number sequence generator generates a total random number sequence of an entire circuit, as fabrication variation. A signal path random number sequence extracting section extracts, from the total random number sequence, a signal path random number sequence for a partial circuit obtained by dividing the entire circuit....

20060107243 - Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects: The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical...

20060107246 - Designing method for high-frequency transistor and high-frequency transistor having multi-finger gate: The present invention provides a designing method for a high-frequency transistor, which includes a transistor section, a drain region, and a gate electrode, a source wiring line, a drain wiring line, and a gate wiring line, for optimizing wiring lines and contacts from voltage supplying nodes to electrode lead nodes....

20060107245 - System and method for suppressing crosstalk glitch in digital circuits: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net...

20060107247 - Memory generation and placement: A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool....

20060107248 - Generating mask patterns for alternating phase-shift mask lithography: A system, method and recording medium are provided for generating patterns of a paired set of a block mask and a phase shift mask from a data set defining a circuit layout to be provided on a substrate. A circuit layout is inputted and critical segments of the circuit layout...

20060107249 - Optimization of multiple feature lithography: According to one embodiment of the invention, a method for enhancing multiple feature lithography is provided. The method includes generating a plurality of maps each associated with a particular one of a plurality of circuit features. Each map maps an illumination field comprising a plurality of point sources and indicates,...

20060101355 - Yield improvement: An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is...

20060101356 - Technology migration for integrated circuits with radical design restrictions: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of...

20060101357 - Technology migration for integrated circuits with radical design restrictions: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to...

20060101358 - Circuit design simulation: Various approaches for simulating a circuit design are described. In one approach, charge-holding combinations of connected circuit components in a non-hierarchical representation of a circuit design are identified as known circuit components. Each identification is made as a function of characterized responses of the combinations. Identification information of the known...

20060101359 - Method and device for verifying digital circuits: For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of...

20060101360 - Systems and methods of simulating signal coupling: Systems and methods for simulating signal coupling in electronic devices are disclosed. In an exemplary implementation a computer program product executes a computer process to simulate a victim signal having a toggling bit pattern relative to a quiet culprit signal. The process also simulates a culprit signal having a toggling...

20060101362 - Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits: A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack...

20060101363 - Method of associating timing violations with critical structures in an integrated circuit design: A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing...

20060101361 - Slack sensitivity to parameter variation based timing analysis: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing,...

20060101364 - Method and apparatus for data distribution in a high speed processing unit: A method, an apparatus, and a computer program are provided for distributing data in a high speed processing unit. Traditionally, true readout data from multiport register files are inverted multiple times when transmitting the readout to data latches, located at multiple physical layers. The inversion of the readout data can...

20060101365 - Method and apparatus for partitioning an integrated circuit chip: A system that partitions an integrated circuit. First, the system receives a placement for an integrated circuit. The system then calculates a joint-utilization ratio for pairs of logic modules in the placement. Next, the system sorts the pairs of logic modules based on the joint-utilization ratio. The system then selects...

20060101367 - Design method of semiconductor device and semiconductor device: In an error analysis step, analysis of an antenna effect error, a timing constraint violation and the like is performed for layout data in which redundant via conversion has been performed. Then, whether or not an error exists is judged and, among redundant vias located on a signal line in...

20060101366 - Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines: A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines...

20060101368 - Distributed electronic design automation environment: PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate data structures. Those structures may be edited by users at separate clients during concurrent editing sessions. Profile data for each...

20060101369 - Automated processor generation system for designing a configurable processor and method for the same: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that...

20060101370 - Method for improving optical proximity correction: A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a...

20060095872 - Integrated circuit devices and methods and apparatuses for designing integrated circuit devices: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC...

20060095869 - Nonlinear driver model for multi-driver systems: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used...

20060095871 - Nonlinear receiver model for gate-level delay caculation: A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more...

20060095870 - Power network analyzer for an integrated circuit design: A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing...

20060095873 - Apparatus and method for detecting body diode conduction in a semiconductor device: An apparatus is for detecting body diode conduction in a semiconductor device that includes first regions fixed with a substrate having an upper surface to establish a source, gate and drain with drain-to-source current flow parallel with the surface. The first regions experience body diode conduction in a first inter-region...

20060095875 - Design method of semiconductor integrated circuit: General-purpose software is used to efficiently perform sample evaluation in a short period of time by changing a register library in accordance with register configuration of a semiconductor integrated circuit device. A register setup program is used for sample evaluation and is composed of a register setup main program and...

20060095874 - Power network synthesizer for an integrated circuit design: A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the simplified plans are evaluated to select...

20060095876 - Method and apparatus for full-chip thermal analysis of semiconductor chip designs: A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to...

20060095877 - Fast evaluation of average critical area for ic layouts: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of...

20060095878 - Method and system for design verification of video processing systems with unbalanced data flow: In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to...

20060095879 - Method and apparatus to estimate delay for logic circuit optimization: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to...

20060095881 - Power pad synthesizer for an integrated circuit design: A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two stages as follows. In a first stage, a number of pads are proposed around a periphery of the...

20060095880 - Process for designing base platforms for ic design to permit resource recovery and flexible macro placement, base platform for ics, and process of creating ics: Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified, and a common element is...

20060095884 - Design analysis workstation for analyzing integrated circuits: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one...

20060095882 - Distributed electronic design automation environment: PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate data structures. Those structures may be edited by users at separate clients during concurrent editing sessions. Profile data for each...

20060095883 - Method of automating place and route corrections for an integrated circuit design from physical design validation: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the...

20060095885 - Systems and methods for storage area network design: Systems and methods for designing storage area network fabric. Preferably included are an arrangement for collecting user requirements on data flows to be supported by the fabric, an arrangement for grouping the data flows into flow groups according to at least one physical location parameter, an arrangement for designing components...

20060095886 - Architecture and interconnect scheme for programmable logic circuits: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer...

20060095887 - Process window-based correction for photolithography masks: A correction for photolithography masks used in semiconductor and micro electromechanical systems is described. The correction is based on process windows. In one example, the invention includes evaluating a segment of an idealized photolithography mask at a plurality of different possible process variable values to estimate a corresponding plurality of...

20060095888 - Statistical optimization and design method for analog and digital circuits: A computer implemented method of performing projection based polynomial fitting. The method includes generating a plurality of sampling points as a function of variables. The method also includes forming a polynomial model template representative of the plurality of sampling points. According to embodiments of the present invention, the polynomial model...

20060095889 - Silicon tolerance specification using shapes as design intent markers: Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping...