Data processing: design and analysis of circuit or semiconductor mask inventions 04/06

20060090144 - Method of automating place and route corrections for an integrated circuit design from physical design validation: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the...

20060090145 - Method of optimizing critical path delay in an integrated circuit design: A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for...

20060090146 - In-line xor checking of master cells during integrated circuit design rule checking: Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and...

20060090147 - Inspection method and inspection apparatus for semiconductor integrated circuit: In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit comprising plural transistors according to which a test pattern generated for the semiconductor integrated circuit is input to an input terminal of the semiconductor integrated circuit, the time during which a voltage applied upon each of the...

20060090148 - Wide geometry recognition by using circle-tangent variable spacing model: Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A...

20060090150 - Method and apparatus for reducing timing pessimism during static timing analysis: One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies...

20060090149 - Simulation testing of digital logic circuit designs: A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified...

20060090151 - Detailed placer for optimizing high density cell placement in a linear runtime: A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two...

20060090153 - Method and apparatus for reducing power consumption in an integrated circuit chip: A system that reduces power consumption in an integrated circuit. During operation the system receives a placement for the integrated circuit. The system then groups registers in the placement into clusters and builds a temporary clock tree for the registers within the placement. Next the system assigns net weights to...

20060090152 - Schematic diagram generation and display system: A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations...

20060085769 - Improving systematic yield in semiconductor manufacture: Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are...

20060085768 - Integrated circuit selective scaling: Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the...

20060085770 - A method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains: Level shifter modules, used in integrated circuits (ICs), are automatically inserter and their correctness verified. A level shifter module for signals crossing voltage domains is generated, and instances thereof are inserted in a pre-determined voltage domain. Several checks ensure the correctness of the inserted level shifter module. The level shifter...

20060085773 - Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity: An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield acceptable results. This category of rules provides more degrees of freedom in actual application so that the rule-based OPC tool can...

20060085771 - Method of screening asic defects using independent component analysis of quiescent current measurements: A method and computer program for screening defects in integrated circuit die includes steps of: (a) receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die; (b) generating a test matrix from the quiescent current measurements for each die in the sample lot;...

20060085772 - Model-based pattern characterization to generate rules for rule-model-based hybrid optical proximity correction: A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by...

20060085774 - Method and apparatus for evaluating and debugging assertions: Roughly described, assertion expressions are evaluated against the binary signal values of a circuit simulation in such a way as to be able to report status information at intermediate levels of assertion subexpressions. In one embodiment, the status information reported for an intermediate subexpressions contains the final status of that...

20060085776 - Method for circuit sensitivity driven parasitic extraction: The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive...

20060085775 - System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis: There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one...

20060085777 - Compact custom layout for rram column controller: The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the...

20060085778 - Automatic addition of power connections to chip power: The present invention relates to a method for designing a hierarchical, multi-layer integrated circuit (IC) chip design in which a first stage design at a lower level of the hierarchical design provides details of circuit features that occupy areas of the design, and in a higher level stage of the...

20060085779 - Representing device layout using tree structure: Methods are described herein for using a tree structure representation for searching selected areas of a programmable device layout in order to determine the existing component configuration of a device. The tree structure may be generated by assigning root nodes, branch nodes and leaf nodes to portions of a tree...

20060085780 - System and method for vlsi cad design: A VLSI CAD system includes formulaic representations of grid lines to form grid boxes in a manner that enhances expressivity and reduces the amount of required processing resources....

20060085781 - Library for computer-based tool and related system and method: A library includes one or more circuit templates and an interface template. The one or more circuit templates each define a respective circuit operable to execute a respective algorithm or portion thereof. And the interface template defines a hardware layer operable to interface one of the circuits to pins of...

20060085782 - Method for optimizing integrated circuit device design and service: Improved analysis and refinement of integrated circuit device design and other programs is facilitated by methods in which an original program is partitioned into subprograms representing valid computational paths; each subprogram is refined when cyclic dependencies are found to exist between the variables; computational paths whose over-approximated reachable states are...

20060080623 - Efficient large-scale full-wave simulation: Significant improvement is achieved in the analysis of IC layout by utilizing the fact that IC designs exhibit a large amount of regularity. By employing a unique mesh generation approach that takes advantage of the regularity, combined with the use of a limited number of different shapes for the majority...

20060080624 - Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips: In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout...

20060080625 - Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores: A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test...

20060080627 - Crosstalk-aware timing analysis: In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and,...

20060080626 - Visualization method and apparatus for logic verification and behavioral analysis: A logic verification tool detects and flags a logic operation with high probability to cause a fault in an electronic system. An efficient logic debug method utilizes a partial sequence of signal outputs and state transitions to extrapolate a verification result with equivalent robustness to full regression testing....

20060080628 - Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus: A semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus are provided that implement automatic placement that reflects constraints provided regarding parasitic elements and inter-element variation provided in a real-valued range. A netlist is prepared in advance, a permissible range setting process sets a permissible range relating to...

20060080629 - Method and system for generating an initial layout of an integrated circuit: A system for generating a layout of an integrated circuit is disclosed. The system includes at least one processing unit for executing computer programs, a graphical-user-interface for viewing representations of the integrated circuit on a display and observing the layout of the integrated circuit, and a memory for storing databases...

20060080630 - Power/ground wire routing correction and optimization: A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a power and ground network for unacceptable IR-drops or electromigration problems. If one or more problems are...

20060080631 - Asics having more features than generally usable at one time and methods of use: More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different...

20060080632 - Integrated circuit layout having rectilinear structure of objects: An integrated circuit layout pattern is formed from a plurality of objects placed within the layout pattern. Each object has a homogenous communications interface, which is a rectilinear donut structure formed of communications elements surrounding a central object logic area. The communications elements are adapted to route data between the...

20060080633 - Method for performing full-chip manufacturing reliability checking and correction: A method of generating a mask for use in an imaging process pattern. The method includes the steps of: (a) obtaining a desired target pattern having a plurality of features to be imaged on a substrate; (b) simulating a wafer image utilizing the target pattern and process parameters associated with...

20060080634 - Edge-based proximity correction: One embodiment of the present invention provides a system that calculates an edge-based proximity correction which is applied to a region in the proximity of an evaluation point. During operation the system receives a layout. Next, the system decomposes polygons in the layout into edges. The system then computes the...

20060075364 - Method and apparatus for driving on-chip wires through capacitive coupling: One embodiment of the present invention provides a system which drives on-chip wires using capacitive coupling. During operation, the system drives a signal onto a driven wire. This signal feeds from the driven wire through a coupling capacitor onto a coupled wire, which is an on-chip wire that routes the...

20060075365 - Novel optimization for circuit design: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result....

20060075366 - Test structures for feature fidelity improvement: Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more...

20060075367 - Racecheck: a race logic ana,yzer program for digital integrated circuits: This invention describes a race logic audit program, RaceCheck, which is unique from the prior arts. Specifically, RaceCheck can perform both static and dynamic race logic analysis, and it works with a plurality of hardware description languages (HDL), which include but not limited to: VHDL, Verilog, SystemVerilog, and SystemC. Furthermore,...

20060075369 - Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design: A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor...

20060075368 - Method for placing electrostatic discharge clamps within integrated circuit devices: A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is...

20060075372 - Electronic device connectivity analysis methods and systems: Techniques for determining and verifying connectivity in an electronic device from a representation of the electronic device are disclosed. Connectivity is determined by identifying electronic components and signals in the electronic device and providing an indication of the identified electronic components and signals. Based on identified components and signals, a...

20060075370 - Method and apparatus for automating post-tape release vlsi modifications: A method and an apparatus for automatically making changes to one or more metal layers of an IC design after the IC design has been tape released. The apparatus includes an ECO tool configured to receive a directive or a list of directives and to automatically make modifications described by...

20060075371 - Method and system for semiconductor design hierarchy analysis and transformation: A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed...

20060075373 - Method and device for the computer-aided design of a supply network: A supply network is designed for a microelectronic circuit by a method for computer-aided design, in that an outline of the microelectronic circuit is detected and the supply network is generated with this outline. In the process, the supply network is designed with a structure in which a pattern is...

20060075374 - Apparatus and method for licensing programmable hardware sub-designs using a host-identifier: Methods and apparatuses for enforcing terms of a licensing agreement between a plurality of parties involved in a particular hardware design through the use of hardware technologies. According to one embodiment, a hardware sub-design includes a license verification sub-design that is protected from user modification by encryption. In one embodiment,...

20060075375 - Technology dependent transformations for cmos in digital design synthesis: The present invention pertains to automated technology dependent transformations for CMOS digital design synthesis resulting in a combination of CMOS interconnected standard-cells from a target CMOS library being mapped and transistor-level representation for all or portion of the input design specification, the transistor level type and portion or portions to...

20060075377 - Method, program product and apparatus for model based scattering bar placement for enhanced depth of focus in quarter-wavelength lithography: A method of generating a mask having optical proximity correction features. The method includes the steps of: (a) obtaining a desired target pattern having features to be imaged on a substrate; (b) determining a first focus setting to be utilized when imaging the mask; (c) determining a first interference map...

20060075376 - System and method for phase shift assignment: A semiconductor design is provided having at least one feature at one of a line end and a line junction, and phase regions. At least one cut line is added to at least one of such features at line ends and such features at line junctions. Phases are assigned to...

20060075378 - Calculating etch proximity-correction using image-precision techniques: One embodiment of the present invention provides a system that calculates etch proximity-correction during an OPC (Optical Proximity Correction) process. During operation, the system receives a layout for an integrated circuit. Next, the system selects a target point on an edge in the layout. The system then casts a plurality...

20060075380 - Calculating etch proximity-correction using object-precision techniques: One embodiment of the present invention provides a system that calculates etch proximity-correction during an OPC (Optical Proximity Correction) process. During operation, the system receives a layout for an integrated circuit. Next, the system selects a target point on an edge in the layout. The system then creates a list...

20060075379 - Method and system for managing design corrections for optical and process effects based on feature tolerances: A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and/or processing effects...