Data processing: design and analysis of circuit or semiconductor mask inventions 03/06

20060070015 - Circuit board design system, design data analysis method and recording medium with analysis program recorded thereon: The design system, which is equipped with capability to analyze circuit board design data, comprises a storing section for recording design data, including structure data, circuit data, and element data; a selection section for selecting a pair of circuit elements subject to interference analysis among circuit elements placed on a...

20060070014 - Real time monitoring system of semiconductor manufacturing information: The present disclosure provides a system for monitoring semiconductor manufacturing in real time which includes an icon module with a database for storing a plurality of icons to provide stored icons that use vector data to represent respective pieces of equipment employed in semiconductor manufacture, a layout module which includes...

20060070016 - Data processing in digital systems: A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can...

20060070017 - Signal processing system: A signal processing system comprises multiple signal processors, each having functional blocks. A control circuit selects one of the signal processors as a target processor, and configures an inspection circuit having equivalent functions to the target processor in a reconfigurable circuit, and retrieves input/output data from each functional block of...

20060070018 - Method for producing a mask layout avoiding imaging errors for a mask: A final mask layout (20′) is produced by producing a provisional auxiliary mask layout in accordance with a predefined electrical circuit diagram and converting it into the final mask layout (20′) with the aid of an OPC method. Before carrying out the OPC method, with the provisional auxiliary mask layout...

20060059443 - Hierarchical feature extraction for electrical interaction: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the...

20060059444 - High level validation of designs and products: A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a relationship of messages communicated between multiple processes; resolving at least one scenario from the message diagram, wherein the scenario...

20060059445 - Method of designing wiring structure of semiconductor device and wiring structure designed accordingly: m

20060059446 - Sensitivity based statistical timing analysis: One disclosed embodiment may comprise a system that includes design data that describes at least a portion of a circuit design. An analysis system determines timing information for a node associated with a first component of the circuit design relative to variations in a parameter associated with at least one...

20060059447 - Integrated circuit design support apparatus, integrated circuit design support method, and integrated circuit design support program: In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a...

20060059448 - Method for production of a standard cell arrangement, and apparatus for carrying out the method: A standard cell arrangement can be produced by automatically determining a distance between at least two standard cells in at least one standard cell row. The method also automatically determines whether at least one of the determined distances is less than a predetermined minimum distance. If the distance is less...

20060059449 - Line layout structure of semiconductor memory devices: A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section...

20060059450 - Transparent re-mapping of parallel computational units: An design architecture for an application specific integrated circuit (ASIC) is disclosed. The design architecture of the ASIC includes a pre-determined number of redundant computational units such that when defective computational units are found during testing, full functionality of the ASIC is maintained by re-mapping functionality from the defective units...

20060059451 - Method for creating and synthesizing multiple instances of a component from a single logical model: Methods for creating and synthesizing multiple instances of a component from a single logical model are provided. In general, a flag is provided which designates a design methodology for use in instantiating the component. Depending on the value of the flag, a block of hardware design code defining an instance...

20060059452 - Pattern component analysis and manipulation: A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree...

20060053393 - Method of improving routes of nets in circuits: One disclosed method for improving the route of at least one net of a circuit comprises: receiving a circuit design that includes a plurality of circuit elements and at least one communication carrier element; determining a location for each circuit element; determining an original route for the communication carrier element;...

20060053394 - Method and apparatus for estimating parasitic capacitance: One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the...

20060053395 - Clock tree synthesis for low power consumption and low clock skew: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given...

20060053396 - Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information: An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes a RTL model of an electronic design and maps it into an efficient, high level hierarchical...

20060053397 - Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system: Embodiments of the present invention include dense, but accessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a “flat components,” are arranged into local blocks of intercommunicating flat components....

20060053400 - Method for correcting layout errors: A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout (10) is examined for the presence of layout errors (20, 30)...

20060053401 - Methods and apparatuses for designing integrated circuits: Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netiist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description...

20060053398 - Methods, systems, and data models for describing an electrical device: A method and system are described for creating a metadata text file corresponding to a geometry of a physical layout and/or a circuit layout of an electrical device. The layouts are defined in a user interface. A text file having metadata elements in a hierarchical format is produced that can...

20060053399 - Semiconductor device, designing device, layout designing method, program and storage medium: A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator...

20060053402 - Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device: There is provided a method of correcting pattern data for a semiconductor device, including acquiring pattern data for a lower layer, pattern data for an upper layer, and pattern data for a connecting layer containing connecting patterns to connect patterns contained in the lower layer and patterns contained in the...

20060053403 - System and method for routing clock signals from a clock trunk: According to at least one embodiment, a system comprises a region generation engine operable to create a region automatically around a portion of a clock trunk in a block, wherein the region defines an area for placement of selected cells, an automatic cell placer operable to place the cells in...

20060053404 - Methods and apparatus for implementing parameterizable processors and peripherals: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically...

20060053405 - Integrated circuit design method: A design method for designing an integrated circuit (IC) and a corresponding integrated circuit design tool are presented. An IC design having a plurality of building blocks (121-129) being interconnected by a plurality of interconnection wires (131-139) is represented by a two-dimensional representation (200) mimicking the positions of the building...

20060053406 - Healing algorithm: An aspect of the present invention includes a method for reshaping sub-objects in at least one object in pattern design data to be presented to a mask writer or a direct writer for producing a pattern onto a workpiece, where said object comprises a plurality of slivers in a first...

20060048079 - Special tie-high/low cells for single metal layer route changes: A method for implementing a circuit design is disclosed. The method generally includes the steps of identifying, replacing and routing. The first step may identify a first cell of the circuit design having (i) a function and (ii) an input pin connectable to one of a first power rail and...

20060048080 - Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip: A method for computer aided design of semiconductor chips which minimizes sensitivity to latchup is provided. The method evaluates electron transmission, reflection and absorption at geometric shapes that represent components of the semiconductor....

20060048081 - System and method for modeling an integrated circuit system: The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method includes generating a configuration file including parasitics regarding ball grid arrays and vias intended for use in design of the integrated...

20060048083 - Chip development system enabled for the handling of multi-level circuit design data: A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be...

20060048082 - Test-cases for functional verification of system-level interconnect: Generation of test cases for functional verification of a complex system-under-test is achieved by the use of a probability matrix. The probability matrix represents a non-uniform distribution function of resource combinations used in the transactions, and can be created randomly, or by application of various types of testing knowledge. The...

20060048086 - Integrated circuit analysis method and program product: A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global...

20060048085 - Method and system for performing timing analysis on a circuit: A method and apparatus for analyzing a circuit are described herein. The circuit may comprise at least two nodes, wherein each of the nodes has timing requirements associated therewith. An embodiment of the method comprises receiving a failure time of first node, wherein the failure time represents the time within...

20060048084 - System and method for repairing timing violations: One disclosed method for repairing min-time timing violations comprises receiving a circuit design to analyze, analyzing the circuit design to determine if a min-time timing violation is present in the circuit design, and fixing a determined min-time timing violation by replacing an appropriate element of the circuit design with a...

20060048087 - Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position...

20060048088 - Computer automated design method, program for executing an application on a computer automated design system, and semiconductor integrated circuit: A computer automated design method includes defining rectangular areas serving as a starting point area and an ending point area of a wiring; accumulating wiring costs whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area, multiplying the wiring...

20060048091 - Method for correcting position-dependent distortions in patterning of integrated circuits: A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the...

20060048090 - Simulation of aerial images: A method for generating a simulated aerial image of a mask projected by an optical system includes determining a coherence characteristic of the optical system. A coherent decomposition of the optical system is computed based on the coherence characteristic. The decomposition includes a series of expansion functions having angular and...

20060048089 - System and method for simulating an aerial image: A method for generating a simulated aerial image includes forming a reference aerial image of a first mask using an optical system, and capturing and processing the reference aerial image so as to generate a set of expansion functions representative of the optical system. The simulated aerial image of a...