Data processing: design and analysis of circuit or semiconductor mask inventions 02/06

20060041849 - Method and apparatus for reducing redundant data in a layout data structure: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the...

20060041851 - Renesting interaction map into design for efficient long range calculations: Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions...

20060041850 - Test method for unit re-modification: The present invention described a test method for unit re-modification, in which there is a test end and a host end. The method generated a sample pattern at a test end, generates a control pattern and modifies a re-modification unit. Otherwise, an experimental pattern is generated and then whether or...

20060041852 - Targeted optimization of buffer-tree logic: Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays...

20060041853 - Cad apparatus, symbol creation device, cad program storage medium and symbol creation program storage medium: The present invention provides a CAD apparatus having high plotting efficiency, a symbol creation device facilitating symbol creation, a CAD program storage medium storing a CAD program incorporated into a computer to enable the computer to operate as the CAD apparatus, and a symbol creation program storage medium storing a...

20060036972 - Interchangeable integrated circuit building blocks: Interchangeable integrated circuit building blocks include functionally equivalent integrated circuit building blocks, having similar footprints, and having one or more dissimilar features or operational characteristics. The functionally equivalent integrated circuit building blocks are interchangeable in a design layout without having to re-place and re-route. The functionally equivalent integrated circuit building...

20060036973 - Method and an apparatus to design a processing system using a graphical user interface: A method and an apparatus to design a processing system using a graphical user interface (GUI) are described. The method includes allowing a user to define a transfer function via a GUI. The method may further include submitting the transfer function to a processing device maker associated with a processing...

20060036974 - Ip-based lsi design system and design method: An IP database includes a system level IP used in system level design. IPs A and B in the system level IP are divided into processing algorithm description portions, input data structure definition portions and output data structure definition portions. When a communication channel is provided between the IPs communicating...

20060036978 - Board design aiding apparatus, board design aiding method and board design aiding program: A board design aiding apparatus that simplifies a designed printed wiring board to predict a displacement quantity of the printed wiring board includes a layer thickness calculation section 21 for obtaining a mean thickness of an area of a board by a prescribed rule for an essential material forming a...

20060036979 - Computer-implemented methods for generating input for a simulation program or generating a simulated image of a reticle: Various computer-implemented methods are provided. One computer-implemented method for generating input for a simulation program includes combining information about a defect detected on a partially fabricated reticle with information about phase assigned to an area of the reticle proximate to the defect. The phase is to be added to the...

20060036975 - Defect diagnosis for semiconductor integrated circuits: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail,...

20060036980 - Method and apparatus for jitter analysis and program therefor: A method, an apparatus and a program for comprehensively analyzing the power supply noise and consequent jitter for external output signals of the LSI in real time. From LSI layout designing data 601, the resistance, capacitance and inductance of the power supply interconnection are extracted to formulate a power supply...

20060036976 - Method for designing an integrated circuit defect monitor: A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and...

20060036977 - Physical design system and method: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target...

20060036981 - Validation of electrical performance of an electronic package prior to fabrication: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the...

20060036984 - Device and method for extracting parasitic capacitance of semiconductor circuit: A device for extracting parasitic capacitance including the influence of a dummy metal pattern inserted between the circuit wires of a semiconductor device comprises a permittivity correction unit for correcting the permittivity of a dielectric existing between the circuit wires in accordance with the insertion of the dummy metal and...

20060036983 - Logic verification device, logic verification method, and computer product: A logical verification device includes an input unit, a generator, an input constraint information calculator, an output constraint information calculator, an input/output constraint information calculator, a determining unit, and a logic verifying unit. The input unit inputs hardware description information and interface specification description information concerning a communication procedure of...

20060036982 - Method and apparatus for detecting nets physically changed and electrically affected by design eco: A method for detecting nets physically changed and electrically affected by a design ECO includes steps as follows. An ECO is executed on an IC design to produce a post-ECO IC design. A first group of nets of the IC design physically changed by the ECO is identified by comparing...

20060036985 - Compacting circuit responses: Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to...

20060036986 - Overlapping shape design rule error prevention: A method, system and program product are disclosed that create new shapes at detected shape overlaps and includes those new shapes during routing and net checking when the new shapes require a larger space than any of the overlapping shapes. The invention thus detects and prevents spacing errors without the...

20060036987 - Methods for optimizing package and silicon co-design of integrated circuit: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed....

20060036988 - Methods and apparatus for implementing parameterizable processors and peripherals: Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically...

20060031789 - Built-in self-test emulator: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST...

20060031788 - Optimization algorithm to optimize within substrate uniformities: A method to optimize semiconductor processing equipment (hardware settings and process conditions) to minimize non-uniformities within a wafer based on linescan measurements and a calculation of or prediction for a polar map. Measurements of a metrology value are taken at a number of points along a linescan (or two orthogonal...

20060031790 - Trusted computing platform: In more detail, the main processing unit (21) of the computing platform is directed to address the trusted hardware device (24), in advance of the BIOS memory, after release from ‘reset’. The trusted hardware device (24) is configured to receive memory read signals from the main processing unit (21) and,...

20060031791 - Compiling memory dereferencing instructions from software to hardware in an electronic design: Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory...

20060031792 - Method and apparatus for locating short circuit faults in an integrated circuit layout: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming...

20060031794 - Method and apparatus for thermal modeling and analysis of semiconductor chip designs: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures...

20060031793 - Spice simulation system for diode and method of simulation using the same: A system and method for simulating a diode device measures electrical characteristics of a plurality of diodes; normalizes the measured electrical characteristics of the diode; extracts a plurality of device parameters of each of the diodes from the normalized characteristics; converts the device parameters of each of the diodes to...

20060031795 - Methods and apparatuses for transient analyses of circuits: Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group...

20060031800 - Design method for semiconductor integrated circuit device: A design method for a semiconductor integrated circuit device. For a path having a signal arrival time exceeding a desired value, among paths in the semiconductor integrated circuit device, a path separation is performed so that the number of other components to be connected to the output of a component...

20060031796 - Method for swapping circuits in a metal-only engineering change: A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing...

20060031797 - Method of timing model abstraction for circuits containing simultaneously switching internal signals: The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is...

20060031798 - Special engineering change order cells: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second...

20060031799 - Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices: A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing...

20060031801 - Method and apparatus for generating a wafer map: A system is provided to aid in the laying out of circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with the goal to maximize yield probability. The subject system accommodates different chip types and arrangements within...

20060031804 - Clustering techniques for faster and better placement of vlsi circuits: A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects...

20060031802 - Clustering-based multilevel quadratic placement: A method of designing a layout of an integrated circuit, by grouping a plurality of logic cells in a region of the integrated circuit into at least two separate clusters, placing the clusters in the region of the integrated circuit to optimize total wire length between the clusters (e.g., using...

20060031803 - Trial placement system with cloning: In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated...

20060031805 - Regular routing for deep submicron chip design: A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore...

20060031806 - Differential delay-line: A printed circuit board is built including metal traces for a differential clock. Within a break in each metal trace pads for a delay line socket are included along with pads for two 0-ohm resistors in series. In between the two 0-ohm resistors metal traces are build in a configuration...

20060031807 - Assertion checking: An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire...

20060031808 - System and method for creating timing constraint information: A method of creating a timing constraint information which provides a timing constraint value of a cell, includes: (a) a processor setting a predetermined range including the timing constraint value as a scope; (b) the processor executing a simulation by using a preliminary timing constraint value within the scope to...

20060031809 - Method for interlayer and yield based optical proximity correction: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with...

20060026538 - Relational database storage and retrieval of circuit element classifications: Various embodiments of a system, method and database for storing circuit element classification information in a relational database are disclosed. One database embodiment comprises a block relation, a structure relation, a FET relation, a NET relation and an association relation....

20060026539 - Method of automated repair of crosstalk violations and timing violations in an integrated circuit design: A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according...

20060026540 - Electro-migration (em) and voltage (ir) drop analysis of integrated circuit (ic) designs: Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of...

20060026541 - Method and apparatus for expediting convergence in model-based opc: One embodiment of the invention provides a system that expedites or stabilizes convergence in a model-based optical proximity correction (OPC) process. During operation, the system receives a layout for an integrated circuit. Next, the system dissects shapes in the layout into a number of segments, and then runs a number...

20060026542 - Systems and methods for generating node level bypass capacitor models: Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a...

20060026543 - Accurate timing analysis of integrated circuits when combinatorial logic offers a load: The accuracy of timing analysis of an integrated circuit is enhanced based on an observation that the capacitive load offered by a combinatorial element (e.g., logic gate) is more when the value on the output path switches, compared to in a scenario when the output path does not switch. In...

20060026544 - Variable sigma adjust methodology for static timing: The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage...

20060026545 - Integrated circuit macro placing system and method: A method (300) of placing a to-be-placed integrated circuit macro (404) adjacent one or more already-placed macros (400) aboard an integrated circuit chip (100). The method includes the step of performing a canonical ordering of the edges of the to-be-placed and already placed macros. Then, an edge constraint vector (500,...

20060026546 - Engineering change order scenario manager: A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by a user, (B) analyzing the circuit design with all of the change orders implemented and (C) generating a...

20060026547 - Circuit layout structure: Main-transistors M1 and M2 are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the sub-transistors that have a common center. This can realize a layout configuration that is...

20060026548 - Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files,...

20060026550 - Mask for fabricating semiconductor devices and method for designing the same: The present method for designing a mask includes calculating the maximum layout number of patterns on a mask substrate, calculating a first mask cost and a second mask cost, calculating the total cost for fabricating a predetermined number of wafers using the first mask and the second mask, and selecting...

20060026549 - Method and system for conducting an online transaction of multi-project wafer service: An online multi-project wafer method comprises providing, via an online interface, a template, receiving, via the online interface, at least two sets of completed templates each having information descriptive of an integrated circuit, checking the received at least two sets of completed templates, providing feedback for respective ones of the...

20060026551 - Accurate density calculation with density views in layout databases: Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area...