Data processing: design and analysis of circuit or semiconductor mask inventions 01/06

20060015828 - Method for designing structured asics in silicon processes with three unique masking steps: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition...

20060015829 - Method and apparatus for designing electronic circuits using optimization: Methods and apparatus for designing electronic circuits, including analog and mixed signal (AMS) circuits, based on an evolutionary optimization approach. In one exemplary embodiment, the optimization approach is implemented using a computer program running on one or more computers. The optimization program receives inputs from the designer regarding (i) optimization...

20060015830 - Systems, methods, and articles of manufacture for flexible path optimization: A flexible transportation optimization approach is described that can easily be implemented on multi-tiered computer systems and that does not unnecessarily consume processing and memory resources. On a database tier a data model is defined. The data model comprises master data including a state set with a plurality of states...

20060015832 - Method of moment computations in r(l)c interconnects of high speed vlsi with resistor loops: A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can...

20060015831 - Minimizing computational complexity in cell-level noise characterization: Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and output pin) of a cell is determined, and NP characteristics and NIC are generated only for the worst case...

20060015834 - Method for correcting crosstalk: In a semiconductor integrated circuit, there is provided a method for correcting crosstalk, which exerts an influence via coupling capacitance between wiring by the signal transitions between adjacent wiring, comprising the step of creating a candidate for buffer division, the step of creating a candidate for cell movement, or the...

20060015833 - System and method for verifying trace lengths and trace spaces in a circuit: The present invention provides a method for verifying trace lengths and trace spaces in a circuit. The method includes the steps of: retrieving information of a trace layout of the circuit; retrieving preset design rules on the trace lengths and the trace spaces of the trace layout; computing trace lengths...

20060015835 - Placement method for decoupling capacitors: A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid...

20060015836 - Negative slack recoverability factor - a net weight to enhance timing closure behavior: More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather...

20060015837 - System and method for designing and manufacturing lsi: An LSI designing system includes a memory;, a database configured to store a layout layer definition file, and a control section configured to refer to the database to build up a plurality of layout layers in the memory based on the layout layer definition file. The plurality of layout layers...

20060010406 - Method of verification of estimating crosstalk noise in coupled rlc interconnects with distributed line in nanometer integrated circuits: A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform...

20060010407 - System and method for operation verification of semiconductor integrated circuit: A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit which stores therein design layout information including the design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated, and a predicted final layout...

20060010410 - Genie: a method for classification and graphical display of negative slack timing test failures: Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of...

20060010411 - Method for netlist path characteristics extraction: A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to...

20060010408 - Placement of a clock signal supply network during design of integrated circuits: A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying...

20060010409 - Semiconductor integrated circuit design method, design support system for the same, and delay library: In a semiconductor integrated circuit design method for simulating a delay of a logic circuit based on delay values which are calculated for each kind of a plurality of cells composing the logic circuit or for each signal path of the logic circuit and which are stored in a delay...

20060010412 - Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each...

20060010413 - Methods for placement which maintain optimized behavior, while improving wireability potential: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths,...

20060010414 - Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration: A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given...

20060010415 - Method, system and storage medium for determining circuit placement: A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A...

20060010416 - System and method for searching for patterns of semiconductor wafer features in semiconductor wafer data: A system for searching for patterns of semiconductor wafer features for use in silicon manufacturing and device fabrication processes, the system including: a data acquisition system 00 for acquiring scan data from differing types of semiconductor wafer scanning tools such as wafer dimensional tools 10, wafer inspection tools 12, and...

20060010417 - Apparatus, method and program product for suppressing waviness of features to be printed using photolithographic systems: A method for minimizing rippling of features when imaged on a surface of a substrate using a mask. The method includes the steps of determining a deviation between a first representation of the design and a second representation of an image of the design at each of a plurality of...

20060005152 - Method and device for designing semiconductor integrated circuit and logic design program: A method for designing a semiconductor integrated circuit includes performing logic design and physical design. The method estimates whether logic design data generated in the logic design is appropriate for use in the physical design before the physical design is started. The result of the estimation is fed back to...

20060005153 - Device, method and program for estimating the number of layers of bga component mounting substrate: To estimate the number of layers required for drawing wirings out of a BGA component at a high speed. A layer number estimation device includes: a bottleneck line detection means, a wiring layer adding means, and a repeating means. The bottleneck line detection means detects a line as a bottleneck...

20060005154 - Integrated opc verification tool: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction,...

20060005155 - Time separated signals: One exemplary system includes a delay circuit configured to copy a signal and to introduce a timing delay into the copy....